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Survey On VLSI Design For Artificial Intelligence And Machine Learning


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© 2023 IJRAR April 2023, Volume 10, Issue 2 www.ijrar.org (E-ISSN 2348-1269, P- ISSN 2349-5138)

Survey On VLSI Design For Artificial Intelligence


And Machine Learning Applications
Arun Tigadi Vaishnavi
Electronics and communication Electronics and Communication
KLE Dr. M S Sheshgiri College of KLE Dr. M S Sheshgiri College of
Engineering & Technology Engineering & Technology
Belgaum, India Belgaum, India

performance ICs used in AIML applications. The process


begins with designing and optimising the circuit with HDLs
Abstract - VLSI creates AIML applications, emphasising their and CAD tools, followed by chip fabrication and testing.
impact on various stages of the design flow. The paper starts with an
overview of VLSI design and its various stages, then moves on to an II. LITERATURE SURVEY
overview of AIML concepts and their relevance to VLSI design. The
paper then delves into the use of AIML at various stages of the design The concept of Artificial Intelligence (AI) has captivated
process. In addition, the paper discusses the challenges and technology across industries. The global market for AI
limitations of using AIML in VLSI design, such as data availability accelerator chipsets is expected to increase from $8 billion in
and scalability. Overall, the paper emphasises the power of AIML 2019 to $70 billion by 2026. [1]. Improve business revenue and
techniques in VLSI design and how they can significantly improve efficiency by automating repetitive tasks, recommending
the performance and efficiency of modern integrated circuits. Many products, and streamlining customer service. The evolving
problems in various fields have been solved by artificial intelligence neural network (NN) models running on CPUs, GPUs, FPGAs,
(AI). The AI principle is based on human intelligence, which is
and ASICs have been successfully adapted in field applications
interpreted.
such as computer vision, natural language processing (NLP),
and personal recommendation. [2] Intelligence can be found
anywhere. From an efficiency standpoint, ASICs are the most
outstanding method. The total power consumption of edge AI
Keywords – VLSI design, AIML algorithms, flow diagram, devices is in the single to double digits mini-watt range, and the
chip size is small.
I. INTRODUCTION
VLSI design is a specialised field of electrical engineering that Ease of Use
deals with the design and implementation of integrated circuits
A. VLSI design for AIML
(ICs) that contain thousands, if not millions, of transistors on a
single chip. VLSI design is essential in the advancement of Several materials are used in the Very Large Scale Integration
advanced technologies such as Artificial Intelligence (AI) and design flow, including silicon, copper, aluminium, silicon
Machine Learning. AIML applications are driving the dioxide, polysilicon, photoresist, tungsten, and nitride, to name
development of advanced computing systems with increased a few. Dopants, metals, and insulators are among the other
processing power, memory capacity, and energy efficiency, materials used. The materials used are determined by the
which are all made possible by VLSI design techniques. VLSI specific requirements of the semiconductor device being
design for AIML applications entails the creation and manufactured. The following steps are involved in the VLSI
optimisation of integrated circuits (ICs) that are specifically design process for AIML applications:
designed for processing large amounts of data and performing
complex computations. Requirement Analysis: Understanding the specific
To ensure future viability, advanced and affordable design requirements of the AI/ML application, such as the type of
techniques with finer optimization must be implemented in the algorithms to be executed, desired performance goals, and
VLSI design flow. power constraints, is part of this step.
The circuit layout is created using computer-aided design Architecture Design: The overall architecture of the hardware
(CAD) tools in physical design. This entails positioning the accelerator or processor is designed in this step.
transistors and interconnects on the chip and optimizing the Algorithm Mapping: Algorithm mapping is the process of
layout for performance, power, and area. Following the mapping AI/ML algorithms onto hardware architecture.
completion of the physical design, the circuit is fabricated using RTL Design: RTL design is the process of creating a hardware
semiconductor manufacturing processes. After that, the chip is description of a design using a hardware description language
tested to ensure that it meets the required specifications. In (HDL) such as Verilog or VHDL.
conclusion, VLSI design is critical for the creation of high-
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© 2023 IJRAR April 2023, Volume 10, Issue 2 www.ijrar.org (E-ISSN 2348-1269, P- ISSN 2349-5138)
Simulation and Verification: To ensure the RTL design's enforcing a set of rules that govern the behaviour of virtual ants.
correctness and functionality, it is simulated using specialised The rules are based on the natural behaviour of ants, who use
software tools. pheromone trails to communicate with one another and find the
Synthesis: After the RTL design has been validated, it is shortest path to food sources. In the case of VLSI design, the
synthesised into a gate-level netlist, which represents the design algorithm generates a graph, with nodes representing
in terms of gates and flip-flops.. components and edges representing connections between them.
Physical Design: Physical design entails laying out the gates The ants move along the perimeter.
and interconnects on the silicon area of the chip to meet the
performance and power targets.
Verification: To ensure that the physical design meets the
required specifications, it is verified using various techniques
such as design rule checking (DRC), layout versus schematic
(LVS) checking, and timing analysis.
Tape-out and Manufacturing: Once the design has been
validated, it is ready for tape-out, which is the process of
creating the final design files for fabrication.
Testing and Validation: The chips are tested and validated
after they are manufactured to ensure their functionality and
performance.
Integration and System-level Testing: Finally, the chips are
integrated into the overall system, and system-level testing is
performed to validate the entire AI/ML application and ensure
its proper operation.

B. Brief on AIML Algorithms Fig 2. Ant Colony Optimization

1.Neural Networks (NNs) Algorithm 3. Transfer Learning Algorithm


Deep learning inspired by the structure and function of the A pre-trained model is used as a starting point for a new task or
human brain is made up of interconnected nodes called neurons domain in transfer learning. Typically, the pre-trained model
that collaborate to process input data and produce an output. has been trained on a large dataset of related tasks or domains
Artificial Neural Networks (ANNs), Convolutional Neural and has learned general features that can be applied to the new
Networks (CNNs), and Recurrent Neural Networks (RNNs) are task or domain. A pre-trained model, for example, can be used
the three types of neural networks. By adjusting the weights of to improve the performance prediction of a new analogue
the connections between neurons based on input data, ANNs circuit by learning features from a large set of analogue circuits.
can be trained to recognise patterns, make predictions, or It reduces the amount of data needed to train a new model,
perform other tasks. By training the network on a large dataset which is especially useful in VLSI design where data collection
of lithography images, CNNs can be used to identify patterns can be costly or time-consuming. It also improves electronic
and defects in lithography images. The output of each neuron circuit performance by leveraging knowledge from related
in an RNN is influenced not only by the current input, but also tasks or domains, which can lead to improved performance.
by the output of the previous neuron.

Fig 1. Neural Network

2. Ant Colony Optimization Algorithm Fig 3. Transfer Learning

ACO can be used in VLSI design to solve problems such as the


placement and routing of electronic components on a chip. The
placement problem is concerned with determining the best
locations for each component on the chip, whereas the routing
problem is concerned with determining the best connections
between the components. The ACO algorithm operates by
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© 2023 IJRAR April 2023, Volume 10, Issue 2 www.ijrar.org (E-ISSN 2348-1269, P- ISSN 2349-5138)
III. FLOW DIAGRAM Logic synthesis

Synthesis is the process by which a synthesis tool, such as a


design compiler, takes the RTL, target technology, and
constraints as inputs and maps the RTL to primitives in the
target technology. After synthesis, functional equivalence
checks are performed to ensure that the input RTL model and
the output gate level model are functionally equivalent.

Placement and Routing

The synthesis tool's gate-level netlist is imported into the place


and route tool in Verilog netlist format. All of the gates and flip-
flops have been placed, and the clock tree synthesis and reset
have been routed. Following the routing of each block, the P&R
tool generates a GDS file, which is used by a foundry to
fabricate the ASIC.

Gate level Simulation

The Placement and Routing tool creates an SDF (Standard


Delay File) with gate timing information. This is annotated
back along with the gate level netlist, and some functional
patterns are run to validate the design's functionality. Static
timing analysis checks can also be performed using a static
timing analysis tool such as Prime time.
Each step in the VLSI Design Flow is briefly described below:
Fabrication
Specification
After the Placement and Routing phase, the gate level
This is the first stage of the design process in which we simulations validate the functional correctness of the gate level
define the important system parameters that must be design, and the design is ready for manufacturing. Normally,
designed into a specification. the final GDS file (a binary database file format that is the
industry standard for data exchange of integrated circuit or IC
High level design layout artwork) is sent to a foundry that fabricates the silicon.
After fabrication, the chip is properly packaged and ready for
Various details of the design architecture are defined at this testing.
stage. Details about the various functional blocks, as well as the
interface communication protocols between them, are defined Post silicon Validation
at this stage.
Once the chip has been returned from fabrication, it must be
Low level design tested in a real-world environment before it can be widely used
in the market. This stage entails lab testing with real hardware
This phase is also referred to as the microarchitecture phase. boards and software/firmware that programmes the chip.
Lower level design details for each functional block Because the speed of simulation with RTL is very slow when
implementation are designed during this phase. Details such as compared to testing in the lab with real silicon, there is always
modules, state machines, counters, MUXes, decoders, internal the possibility of discovering a bug in silicon validation, which
registers, and so on can be included. is why it is critical before qualifying the design for a market.

RTL coding
IV. DESIGNING VLSI CIRCUITS FOR AIML APPLICATIONS
During the RTL coding phase, the micro design is modelled in PRESENTS SEVERAL CHALLENGES
a Hardware Description Language, such as Verilog/VHDL,
using synthesizable language constructs. Synthesizable Power Efficiency: Because AI and ML systems require a
constructs are used so that the RTL model can be fed into a significant amount of computational power, they can consume
synthesis tool, which will later map the design to actual gate a lot of power. Power-efficient designs, achieved through
level implementation. techniques such as voltage scaling, clock gating, and power
gating, are critical for extending battery life in portable devices
and lowering energy consumption in data centres.
Functional verification
Memory Hierarchy: Because AI and ML systems process
The process of verifying the functional characteristics of a large datasets, efficient memory hierarchy design is critical.
design by generating different input stimuli and checking for Memory placement, cache design, and memory bandwidth
correct behaviour of the design implementation is known as management are critical for minimising data movement and
functional verification. lowering memory access latency.

Data Privacy and Security: In AI and ML applications, data


privacy and security are critical concerns. To protect sensitive
data and ensure the secure operation of AI and ML systems,

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VLSI circuits with robust security features such as hardware VI. CONCLUSION
encryption, secure boot, and tamper detection are required. Finally, AI/ML algorithms play an important role in VLSI
design and optimisation. AI/ML can help address the
Scalability: AI and ML models are constantly evolving, and the challenges and capitalise on the opportunities presented by the
demand for more computational power is increasing. To meet increasing complexity of VLSI circuits, from improving circuit
the performance demands of future applications, it is critical to performance to optimising manufacturing processes and
design scalable VLSI solutions that can handle the increasing accelerating hardware. VLSI engineers and researchers can use
computational requirements of AI and ML workloads. AI/ML to design and optimise circuits that are more efficient,
V. SEVERAL VLSI TECHNIQUES ARE BEING USED IN AIML reliable, and secure, while also lowering design and
APPLICATIONS TO OVERCOME THE DESIGN CHALLENGES manufacturing costs and shortening time-to-market. AI/ML
technologies are expected to become an increasingly important
tool in the VLSI design and optimisation process as they evolve
Low-power design: VLSI techniques are used to optimise AI and mature.
and ML systems' power consumption, which is critical for Many tasks in the VLSI design process, such as layout
mobile and edge devices with limited battery life. Power gating, optimisation, timing analysis, and power optimisation, can be
dynamic voltage scaling, and clock gating are used to reduce automated and optimised with AI/ML. This can aid in the
power consumption without sacrificing performance. reduction of design time and costs while also improving
performance and reliability. VLSI designers will create
Hardware-software co-design: Hardware-software co-design customised circuits for AI/ML applications. With the rapid
entails creating customised hardware accelerators that work in growth of the Internet of Things (IoT) and other embedded
tandem with optimised software algorithms to enable the systems, VLSI circuits optimised for low power and energy
efficient execution of AI and ML workloads. efficiency are in high demand.
Memory-centric Design: Memory-centric design techniques VII. FUTURE SCOPE
optimise the memory hierarchy to minimise data movement,
reduce memory access latency, and improve overall system Healthcare: The introduction of health care applications
performance. has resulted in a complete transformation of the
traditional healthcare industry. The use of AI and ML in
Reconfigurable Computing: FPGAs provide reconfigurable healthcare is currently combined with a mobile
hardware that can be tailored to specific AI and ML workloads, application that aids in the organisation of better
allowing for flexible and efficient implementations. treatment plans for patients while under the supervision
of a physician.

APPLICATIONS Transportation: AI and machine learning have enormous


potential in the transportation sector. Autopilot has been
Artificial Intelligence (AI) and Machine Learning (ML) have a used in ships, aircraft, and spacecraft since 1922. Another
variety of applications in VLSI design and testing. These are example of AI's advancement is autonomous vehicles.
some of the applications: Several companies around the world are working on self-
driving or autonomous vehicles that rely heavily on
Design optimisation: AI/ML algorithms can be used to machine learning and artificial intelligence.
optimise VLSI circuit design. These algorithms can learn from
previous designs and make suggestions for new ones. This can
help reduce design time and improve VLSI circuit efficiency. Manufacturing industry: A number of global startups that
serve the manufacturing industry are based on artificial
Layout optimisation: AI/ML algorithms can also be used to intelligence and machine learning. These businesses are
optimise VLSI circuit layout. These algorithms can generate now developing AI-based revenue-boosting solutions.
layouts that minimise the circuit's area, power consumption, One of the most unique AI techniques in the
and delay. manufacturing industry is data analysis to make the best
future predictions.
Fault detection: AI/ML algorithms can be used to detect flaws Cybersecurity: AI in cyber security is beneficial when
in VLSI circuits. These algorithms are capable of learning from organisations transfer data through cloud networks. As the
previous fault data and predicting the most likely cause of a threat of hackers grows, AI in cyber security is playing an
fault. This can help to reduce the time and cost associated with important role in keeping data transfers secure. Cognitive AI is
testing VLSI circuits. an excellent example of this. It not only detects threats but also
analyses them, providing insights to analysts to help them make
Improved yield: AI/ML algorithms can be used to boost the better decisions. AI is improving and becoming more durable
yield of VLSI circuits. These algorithms can analyse data from as deep learning networks and machine learning algorithms are
previous manufacturing runs and make recommendations for used. This makes it possible for people to recognise potential
improvements in the next run. This can reduce the number of threats in the future.
defective chips while also increasing overall yield.
ACKNOWLEDGEMENT
Power optimisation: AI/ML algorithms can be used to
optimise VLSI circuit power consumption. These algorithms We want to thank the Principal, management of KLE Dr MSS
can learn from the behaviour of the circuit and make CET and VGST for providing the necessary infrastructure for
suggestions to reduce power consumption while maintaining completing this work.
performance.

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© 2023 IJRAR April 2023, Volume 10, Issue 2 www.ijrar.org (E-ISSN 2348-1269, P- ISSN 2349-5138)
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