Professional Documents
Culture Documents
6ML Ai Vlsi
6ML Ai Vlsi
net/publication/370519687
CITATIONS READS
0 18
2 authors, including:
SEE PROFILE
All content following this page was uploaded by Arun SADANAND Tigadi on 04 May 2023.
RTL coding
IV. DESIGNING VLSI CIRCUITS FOR AIML APPLICATIONS
During the RTL coding phase, the micro design is modelled in PRESENTS SEVERAL CHALLENGES
a Hardware Description Language, such as Verilog/VHDL,
using synthesizable language constructs. Synthesizable Power Efficiency: Because AI and ML systems require a
constructs are used so that the RTL model can be fed into a significant amount of computational power, they can consume
synthesis tool, which will later map the design to actual gate a lot of power. Power-efficient designs, achieved through
level implementation. techniques such as voltage scaling, clock gating, and power
gating, are critical for extending battery life in portable devices
and lowering energy consumption in data centres.
Functional verification
Memory Hierarchy: Because AI and ML systems process
The process of verifying the functional characteristics of a large datasets, efficient memory hierarchy design is critical.
design by generating different input stimuli and checking for Memory placement, cache design, and memory bandwidth
correct behaviour of the design implementation is known as management are critical for minimising data movement and
functional verification. lowering memory access latency.
[6] Suresh Krishna; Ravi Krishna, "Accelerating Recommender [14] Detection of Pedestrian, Lane and Traffic Signal for Vision
Systems via Hardware “scale-in”," 11 Sep. 2020. [Online]. Based Car Navigation
Available: https://arxiv.org/pdf/2009.05230.pdf. NM Gohilot, A Tigadi, B Chougula - 2021 2nd International
Conference for Emerging …, 2021
[7] Naumov, Maxim, John Kim, Dheevatsa Mudigere, Srinivas
Sridharan, Xiaodong Wang, Whitney Zhao, Serhat Yilmaz et [15] Chao-Yang Kao, Huang-Chih Kuo, Jian-Wen Chen,
al., "Deep Learning Training in Facebook Data Centers: Design ChiungLiang Lin, Pin-Han Chen, Youn-Long Lin, "RNNAccel:
of Scale-up and Scale-out Systems.," arXiv: 2003.09518, 2020. A Fusion Recurrent Neural Network Accelerator for Edge
Intelligence," arXiv: 2003.09518, 202
IJRAR23B1953
View publication stats
International Journal of Research and Analytical Reviews (IJRAR) 740