Study on Spurious Suppression Behavior
of Fractional-N and DDS Based PLL Synthesizers
2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT) | 979-8-3503-3887-4/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICMMT58241.2023.10277622
with Fine Frequency Resolution
Shiqi Jiang, Yuwei Zhang, Jinping Xu*
State Key Laboratory of Millimeter Waves, Southeast University
Nanjing 210096, China E-mail: jpxu@seu.edu.cn
Abstract-A comparison study on spurious suppression
behavior of fractional-N and direct digital synthesizer (DDS)
based phase-locked loop (PLL) Synthesizers is reported in this
paper. It is well-known that a fractional-N synthesizer with delta-
sigma modulator (DSM) suffers serious problem of integer
boundary spurious and fractional spurious. A hybrid scheme of
DDS and integer-division PLL is an effective way to alleviate this
problem in the development of frequency sweeping synthesizers
with high frequency resolution. To quantitatively evaluate the
improvement of the spurious suppression of the DDS based PLL
to fractional-N synthesizer, a comparison study of the two schemes
of the frequency synthesizers has been carried. ADI’s HMC778
was adopted to generate form the fractional-N PLL, by adjusting
the frequency ratio of the fractional divider in the chip, a fine-
resolution sweeping frequency source working in X-band was
implemented. A hybrid frequency synthesizer scheme, where
HMC778’s internal VCO is combined with ADI’s DDS AD9910 as
the reference source to the integer frequency division PLL, is
adopted. In this way, the expected signal with ultra-fine frequency
step size can be delivered from the DDS and multiplied by the fixed
integer frequency division ratio to the same frequencies of the
fractional-N PLL. The two frequency synthesizers are measured
and compared in regard to spurious suppression behavior. The
fabricated hybrid frequency synthesizer avoids the integer
boundary spurious and fractional spurious caused by fractional
frequency ratio, which basically has 39dB better integer boundary
spurious suppression at the frequency from 9.9 to 10.7GHz.
Simultaneously, it is observed that the noise floor is improved by
5dB in 200KHz bandwidth. The results of this work are valuable
to balance system complexity and spurious suppression
requirement in practical applications.
Keywords-spurious suppression, fractional-N PLL, hybrid
frequency synthesizer, fine frequency resolution
I. INTRODUCTION
Frequency synthesizer systems are widely used in wireless
communication, electronic countermeasures and measurement
instruments [1]. As a core component of modern practical
electronic systems, frequency synthesizer has the
characteristics of low phase noise [2], low spurious [3], wide
bandwidth [4], small step [5] and high degree of integration [6].
When the step frequency of the frequency sweeping source is
required as low as Hz order, the spurious of fractional-N
frequency synthesizer mainly include integer boundary
spurious and fractional spurious. Much of the spurious
components appear in the desired frequency band, and usually
they are unable to be filtered out by loop filter. Therefore, it is
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worthwhile to quantitatively investigate the amplitude and
location of the spurious in frequency synthesizer [7].
In this paper, the spurious of fractional-N and DDS based
PLL frequency synthesis are measured and compared. The
experiment shows the effectiveness of hybrid frequency
synthesizer scheme in suppressing the proximal spurious.
II. DESIGN SCHEMES OF FREQUENCY SYNTHESIZERS
Two different frequency synthesizer schemes are designed to
compare their performance of spurious suppression. The first
one is a fractional-N PLL frequency synthesizer with ultra-fine
frequency step. Fractional division generates integer boundary
spurious and fractional spurious that are difficult to suppress.
The second one is a DDS based PLL frequency synthesizer, the
DDS generates fine step frequencies and the PLL's dividing
ratio is set to an integer. The hybrid frequency synthesizer
scheme suppresses both types of spurious, effectively.
A. Fractional-N PLL Frequency Synthesizer
In this subsection, the details of fractional-N PLL frequency
synthesizer are described. As shown in Fig.1, the designed
frequency synthesizer consists of a phase and frequency
discriminator (PFD), a charge pump (CP), a loop filter, a VCO
and a fractional-N frequency divider. The frequency
synthesizer is fulfilled with a commercially chip HMC778
delivered by ADI.
Figure 1. Block diagram of fractional-N PLL frequency synthesizer
The input reference signal of the fractional-N PLL frequency
synthesizer is a fixed frequency signal, and fine steps are
achieved by changing the value of frequency division ratio.
When the frequency division ratio is set to a fractional one, it
alternates between two consecutive integers N and N+1, and a
multiple bit digital accumulator is utilized to control the
sequence of the two-division ratio. In each control cycle, the
divider has 2 − K times N divisions and K times (N+1)
k
divisions. Under this condition, the division frequency ratio can
be calculated by:
(2k − K )  N + K  ( N + 1) K
N frac = =N+ k
2k 2
where k is the bits of the digital accumulator, and K is
determined by the frequency to be generated.
Fractional-N PLL synthesizers have the advantage of
generating fine resolution frequency signal, but it also brings
the problem of serious spurious. Due to the phase errors that
generated by the periodic variation of the fractional division
frequency ratio, fractional spurious are caused by the periodic
jitter of the VCO tuning voltage. To improve the spurious
suppression caused by fractional dividers, DSM breaks the
periodic variation of the division ratio by oversampling
technique and spreads the fractional spurious into a wider
frequency band, which is generally integrated in fractional-N
PLL.
In addition, the frequencies output from VCO are not the
integral multiple of the PFD frequency in fractional mode.
Intermodulation between the N-divide frequency and (N+1)-
divide frequency will lead to integer boundary spurious. When
VCO frequency is very close to the integral multiple of PD
frequency, integer boundary spurious becomes more and more
strong in amplitude. The diagram of integer boundary spurious
is shown in Fig.2 and the spurious’ offset frequency to the
center frequency can be calculated as:
 = m  ( fVCO − n  f PFD )
where m is the order of integer boundary spurious and n is the
integer division ratio.
Figure 2. Diagram of integer boundary spurious
The fractional-N PLL frequency synthesizer possesses
several advantages such as: miniaturized structure, low power
consumption and low cost. However, its fractional frequency
division scheme characteristics and DSM limitations do not
make it suitable for high resolution frequency sweeping source
systems due to its serious fractional spurious. Therefore, a
hybrid frequency synthesizer based on PLL and DDS is adopted
to alleviate this problem.
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B. DDS-based PLL Frequency Synthesizer
(1)
Figure 3. Block diagram of hybrid frequency synthesizer
As shown in Fig.3, the main difference between this scheme
and the fractional-N PLL scheme in Fig.2 is that the fixed
reference frequency is replaced by a DDS with ultra-fine
frequency step. Meanwhile, PLL's dividing ratio is set to a fixed
integer instead of variable fractional. Therefore, the fine-
resolution DDS based PLL frequency synthesizer avoids
integer boundary spurious and fractional spurious when
stepping at fine frequencies. Moreover, the out-of-band
spurious of the DDS output signal can be filtered out by the
loop filter of the PLL.
III. MEASUREMENT AND ANALYSIS
To compare the spurious of fractional-N PLL frequency
synthesizer and DDS based PLL frequency synthesizer, the
spectral characteristics of the output signal are measured at
fixed frequency points within the range of frequency sweeping.
To reduce the effect of extraneous variables, both frequency
synthesis schemes use a 100 MHz crystal (OXLN50D-S-HP-V)
as the external reference signal, the fractional-N PLL frequency
(2) synthesizer is fulfilled with HMC778. The hybrid frequency
synthesizer scheme is adopted, where HMC778’s internal VCO
is combined with ADI’s DDS AD9910 as the reference source
to the integer frequency division PLL. Similarly, AD9910 is
used as the reference source to the fractional frequency division
PLL in the fractional-N PLL frequency synthesizer. The
measurement setup of the frequency synthesizer is presented in
Fig.4.
Figure 4. Measurement setup of the frequency synthesizer
In our experiment, setting for the Fractional-N PLL
frequency synthesizer scheme is as follows: DDS output
frequency is set to be 130MHz, the fractional division
frequency ratio of is set to be 82.0006308. According to
Equation 2, the calculation results are:  = 20KHz . The 1st to
4th order integer boundary spurious with a frequency spacing
of  , which is about 20KHz, are uniformly distributed on both
sides of the output signal at 10660.082MHz. The worst integer
boundary spurious suppression is only 28dBc over 200KHz
bandwidth. At the same frequency bandwidth, the noise floor is
-80dBm. As the measured results shown in Fig.5(a).
The setting for the hybrid frequency synthesizer based on
PLL and DDS scheme is as follows: DDS output frequency is
set to be 130.0001 MHz, the integer division frequency ratio of
the PLL is 82. The integer boundary spurious will not exist. The
spurious suppression is better than 67dBc over 200KHz
bandwidth. At the same frequency bandwidth, the noise floor is
-85dBm, which is 5dBc lower than Fractional-N PLL frequency
synthesizer scheme. As the measured results shown in Fig.5(b).
(a) (b)
Figure 5. Frequency spectrums of (a) fractional-N PLL frequency synthesizer
and (b) DDS-based PLL frequency synthesizer at 10660.082MHz
In fractional-N PLL frequency synthesizer scheme, the DDS
output frequency is fixed at 130 MHz, frequency sweeping is
implemented by changing the fractional division frequency
ratio of the PLL. In DDS based PLL frequency synthesizer
scheme, the integer division ratio is fixed at 76 and DDS output
serves as the sweeping reference frequency in a specific band.
In Fig.6, it can be clearly observed that hill-like proximal
spurious on both sides of each output spectrum over 9.9-
10.7GHz. The spurious suppression is worse for fractional
frequency division in this frequency band.
(a) (b)
Figure 6. Frequency spectrums of (a) fractional-N PLL frequency synthesizer
and (b) DDS-based PLL frequency synthesizer over 9.95 to 10.65GHz
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IV. CONCLUSION
Two kinds of frequency synthesizer’s spurious suppression
are measured and compared. The fractional-N and DDS-based
PLL frequency synthesizers are implemented by ADI’s
HMC778 and ADI’s AD9910. In the case of fine-resolution
frequency sweeping source, the hybrid frequency synthesize
scheme avoids integer boundary spurious and fractional
spurious that may appear in fractional-N PLL synthesizer. The
measured results show that the hybrid synthesizer, compared
with the fractional-N synthesizer, basically has 39dB better
integer boundary spurious suppression from 9.9 to 10.7GHz. It
is observed that the noise floor is improved by 5dB in 200KHz
bandwidth. In the applications of wide band frequency
sweeping source with fine frequency resolution, the fractional-
N PLL frequency synthesizer is more suitable with low
requirements for spurious suppression with minimized size, and
the DDS-based PLL frequency synthesizer has a significant
spurious suppression at the expense of system complexity.
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