Physics

Paper No. : 09 Electronics

Module: 1.2Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)

Development Team
Prof. Vinay Gupta ,Department of Physics and Astrophysics,
Principal Investigator University of Delhi, Delhi

Dr. Monika Tomar ,Physics Department ,Miranda House

Paper Coordinator
University of Delhi, Delhi

Prof. Vinay Gupta, Department of Physics and Astrophysics, University of Delhi, Delhi
Content Writer
Dr. Ayushi Paliwal, Department of Physics, Deshbandhu College, University of Delhi, Delhi

Prof. R. P. Tondon,Department of Physics and Astrophysics,

Content Reviewer 1
University of Delhi, Delhi

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 Description of Module
Subject Name Physics
Paper Name Electronics
Module Name/Title Metal-semiconductor junctions, Metal-oxide semiconductor junctions
(MOS diode)

Module Id 1.2

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 Contents of the unit
1. Introduction
2. Energy band diagram of an isolated metal adjacent to an isolated n-type semiconductor
3. Energy band diagram of metal-n semiconductor contact in thermal equilibrium.
4. CURRENT TRANSPORT
5. MOS DIODE
6. Different Biasing conditions of an ideal MOS diode
7. Interface traps and oxide charges
8. C-V characteristics of Ideal MOS capacitor
9. Summary

Learning Objectives
 Energy band diagram of an isolated metal adjacent to an isolated n-type semiconductor
 Energy band diagram of metal-n semiconductor contact in thermal equilibrium.
 CURRENT TRANSPORT in metal-semiconductor junction
 MOS DIODE
 Different Biasing conditions of an ideal MOS diode
 Interface traps and oxide charges
 C-V characteristics of Ideal MOS capacitor

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 1. Introduction
First practical semiconductor device was the metal-semiconductor contact in the form of a point contact
rectifier. In 1938, Schottky suggested that the rectifying behavior could arise from a potential barrier as
a result of a stable space charges in the semiconductor due to metal contact (known as Schottky barrier)
where IV characteristics are very similar to those of p-n diode. Metal – Semiconductor contacts can also
be non-rectifying i.e. the contact has a negligible resistance regardless of the polarity of the applied
voltage [Ohmic Contact]. All semiconducting devices as well as IC’s need Ohmic contacts to make
connections to other devices in an electronic system. Let us see how does the energy band diagram of
the metal in contact with the semiconductor gets modified.
2. Energy band diagram of an isolated metal adjacent to an isolated n-type semiconductor

Figure 1: Isolated metal and n-type semiconductor

Figure 1 represents the energy band diagram of two isolated metal and an n-type semiconductor placed
close to each other. The symbols used in the figure represents the following:

= Work function of metal

= Work function of semiconductor

 = Electron affinity
EC = Conduction band energy level
EV = Valence band energy level
EF = Fermi energy level
In this certain assumption are taken for a Schottky contact which are

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 1. An isolated n-type semiconductor is selected.
2. Work function of metal is greater than that of semi-conductor.
Condition for integration
Initially metal and Semiconductors are isolated, but when both are integrated, then the following
conditions should always be considered:
I. Fermi energy level should align.
II. Vacuum level should remain continuous.

3. Energy band diagram of metal-n semiconductor contact in thermal equilibrium.

Figure 2: Metal and n-type semiconductor in thermal equilibrium

Figure 2 represents the Metal and n-type semiconductor junction in thermal equilibrium. In order to align
Fermi levels, the conduction and valence band on the semiconductor side bend upwards. Electron on
metal side have lower energies than electrons on semiconductor. Thus, electrons transfer from
semiconductor to metal. Electrons move from SC to metal leading to space charge region due to mobile
carriers in metal side and a depletion region SC side due to immobile carriers.

Figure 3: Charge and electric field distribution across the junction

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 4. CURRENT TRANSPORT
On forward biasing semiconductor (-ve) and metal (+ve), width V is reduced, electrons can flow easily
from semiconductor to metal. While, in reverse biased width V is increased, thus less electrons are
transferred from semiconductor to metal as they cannot flow easily. If some forward biasing is applied,
then there is no change for barrier height for electrons on metal side because of shift of Fermi energy
level. But more current flows as more electrons are transferred from semiconductor to metal. So, net
current flows in forward direction. If some reverse biasing is applied, then current from metal to
semiconductor remains the same. But the electrons from semiconductor to metal decreases, so a very
less current in reverse biasing.

Figure 4: Current transport in forward and reverse bias

Thus, n-type semiconductor with work function of metal greater than the work function of semiconductor
is a SCHOTTKY contact since it offers resistance for the flow of electrons from semiconductor to metal.
Certain assumption are taken for a Ohmic contact which are
1. An isolated n-type semiconductor is selected.
2. Work function of metal is less than that of semi-conductor.

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 Figure 5: Energy band diagram of an isolated metal adjacent to an isolated n-type semiconductor
• Electrons will transfer from metal to SC, till the Fermi energy levels of both are aligned.
• A positive space charge region will be formed in metal due to transfer of electrons.
• The electrons cannot be transferred from SC to metal, as work function of metal is less than that
of semiconductor.
• As electrons in metals are more energetic and can transfer from metal to SC.
• Thus, Space charge region is formed on both sides, so it do not show rectifying behavior.
• It does not offer any resistance whether it is forward biased or reverse biased.
• Thus, the contact is ohmic.

Figure 6: Energy band diagram of metal-n semiconductor contact in thermal equilibrium

As a conclusion, the electrical nature of ideal MS contacts are as follows:

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 Work n-type p-type
function
Φ𝑀 > Φ𝑆 Rectifying Ohmic

Φ𝑀 < Φ𝑆 Ohmic rectifying

5. MOS DIODE
MOS diode is a very useful component of most of the VLSI-MOSFET devices. A basic MOS consisting of three
layers. The top layer is a conductive metal electrode, the middle layer is an insulator of glass or silicon dioxide,
and the bottom layer is another conductive electrode made out of crystal silicon. This layer is a semiconductor
whose conductivity changes with either doping or temperature. The schematic of the MOS diode is as follows:

Figure 7: Schematic of an MOS diode

Ideal MOS diode:

Ideal MOS diode is defined as:
1. At the applied bias of zero volts, the band gap is flat or it is generally referred as flat band condition. In
other words, the energy difference between metal work function qm and semiconductor work function
qs is zero.
2. Under any biasing condition the only charge that exits are those which are there in any semiconductor and
an equal and opposite sign charges on the metal surface adjacent to the oxide.
3. here is no carrier transport through the oxide under dc biasing conditions, or the resistivity of the oxide is
infinite, i.e., oxide is perfect insulator devoid of any charges.

The energy band diagram of an ideal MOS diode under zero applied bias is shown in figure 1 below:

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 Figure 8: Energy band diagram of an ideal MOS diode at V = 0

When biasing is applied across an ideal MOS diode, there may be three case which can exist namely:
 Accumulation
 Depletion
 Inversion

6. Different Biasing conditions of an ideal MOS diode:

Case I V< 0: When a small and negative bias is applied on the metal side fermi level is raised by an amount qV.
The schematic under this negative biasing condition is shown in figure 9(a) and the energy band diagram is
shown in figure 9(b).

Figure 9: (a) Schematic of an ideal MOS diode when V < 0, (b) Energy band diagram of an ideal MOS diode
when V < 0

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 On application of applied V. the vaccum level rises by an amount qV as m &  should remain unaffected. Bands
near semiconductor surface are bent upward (Ev, Ei, Ec). No current flows in MOS irrespective of V; the Fermi
level in semiconductor will remain constant. The vacuum level must bend up gradually to accommodate applied
V (from semiconductor side). Since, oxide is assumed to be charge free, the lower edge of the oxide conduction
band will bend linearly.
The negative applied bias voltage (-V) on the gate implies that negative charge on gate producing equal and
opposite charges in the semiconductor by attracting holes near the oxide-semiconductor interface. Therefore, there
is an enhanced concentration of holes occurs near semiconductor surface with a consequent upward bending of
energy levels. This is called as Surface accumulation condition.
According to the expression of carrier density in the semiconductor is
𝑝𝑝 = 𝑛𝑖 𝑒 (𝐸𝑖−𝐸𝐹 )/𝐾𝑇 (3)
the upward bending of energy band causes the increase in (Ei - EF) implying enhanced concentration of holes
near oxide-semiconductor interface which is called as Accumulation condition.
Case II: in this case, holes are pushed away from oxide interface by applying a small positive applied voltage V
> 0. This lead to the formation of depletion region in semiconductor near interface, having mainly negative charged
acceptor (Na) ions termed as Depletion Condition. The schematic under this biasing condition is shown in figure
10(a) and the energy band diagram is shown in figure 10(b).

Figure 10: (a) Schematic of an ideal MOS diode when V > 0, (b) Energy band diagram of an ideal MOS diode
when V > 0
Since hole concentration in depletion region is very much less than the concentration of holes in neutral region of
semiconductor, separation between EF and Ev is increased at interface causing a downward bending of energy
levels Ec , Ev and Ei..

Case III: For a large positive applied voltage V >> 0, there is a downward bending of bands occurs and when Ei
touches EF at surface, then semiconductor surface becomes intrinsic (np = ni). For large V, Ei crosses EF and
conduction band comes closer to EF instead of valence band i.e. minority carriers (electrons) are attracted to
10

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 interface, semiconductor surface contains more electrons than holes. [Surface gets inverted from p-type to the n-
type]. The thin region (xi) where electrons concentration exceeds the hole concentration is called the inversion
layer. The schematic under this biasing condition is shown in figure 11(a) and the energy band diagram is shown
in figure 11(b).

Figure 11: (a) Schematic of an ideal MOS diode when V >> 0, (b) Energy band diagram of an ideal MOS diode
when V >> 0

In this biasing condition, minority carriers (ns) becomes more than majority charge carriers.

Once, inversion occurs at the surface: Further increase in V will induce practically all additional negative
charges in the inversion layer.
7. Interface traps and oxide charges

The MOS Diode is generally affected by the Charges present in the oxides and traps at Si-SiO2 interface.

Figure 12: Different charges present at the interface

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Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 1. Interface-trapped charge Qit

|It is due to the SiO2-Si interface properties and dependent on the chemical composition of this interface |The
interface trap density is orientation dependent for example in <100>orientation the interface trap density is about
an order of magnitude smaller than that in <111>orientation |450℃hydrogen annealing the value of Interface-
trapped charges for <100>orientation silicon can be as low as 1010cm-2
2. Fixed-oxide charge Qf
|the fixed-oxide charge is located within approximately 3 nm of the SiO2-Si interface. this charge is fixed and
cannot be charged or discharged over a wide variation of surface potential. Generally, Qf is positive and depends
on oxidation and annealing conditions and on silicon orientation |It has been suggested that when the oxidation is
stopped, some ionic silicon is left near the interface. It may result in the positive interface charge Qf |Typical fixed-
oxide charge densities for a carefully treated SiO2-Si interface system are about 1010cm-2 for a <100>surface and
about 5x 1010cm-2 for a <111>surface
3. Oxide-trapped charge Qot
Oxide-trapped charge are associated with defect in the silicon dioxide. These charges can be created, for example,
by X-ray radiation or high – energy electron bombardment the trap are distributed inside the oxide layer. Most of
process-related oxide trapped charge can be removed by low-temperature annealing
4. Mobile ionic charge Qm
|The mobile ionic charges Qm, such as sodium or other alkali ion are mobile within the oxide under raise
temperature (e.g.>100℃) and high electric field operation |It may cause stability problem in device.

8. C-V characteristics of Ideal MOS capacitor:

MOS can be said as parallel plate capacitor with SiO2 dielectric surface charge layer in semiconductor under
metal gate is modified by V. Hence, the total voltage will be the sum of the voltage across the oxide (Voxide) and
across semiconductor (𝜓𝑠𝑒𝑚 ).
Thus, total applied voltage is 𝑉 = 𝑉𝑜𝑥𝑖𝑑𝑒 + 𝜓𝑠𝑒𝑚 (17)
where, 𝑉𝑜𝑥𝑖𝑑𝑒 is the voltage across oxide
𝜓𝑠𝑒𝑚 in semiconductor
Where potential across oxide is given by
−|𝑄𝑠 | −|𝑄𝑠 |𝑑𝑜
𝑉𝑜𝑥𝑖𝑑𝑒 = 𝜉𝑜 𝑑𝑜 = 𝐶 = 𝜖𝑜𝑥𝑖𝑑𝑒
(18)
𝑜𝑥𝑖𝑑𝑒

𝜖𝑜𝑥𝑖𝑑𝑒
where o is field in oxide of thickness do, Qs is charge per unit area in semiconductor, 𝐶𝑜 = 𝑑𝑜
is oxide
capacitance per unit area. 𝜖𝑜𝑥𝑖𝑑𝑒 is permittivity of oxide layer.
−|𝑄𝑠 |
Thus, total voltage V, 𝑉 = + 𝜓𝑠 (19)
𝐶𝑜

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Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 Differentiate equation 18 w.r.t. to V and rearranging terms, we get
1 1 𝑑𝜓𝑠𝑒𝑚
−(|𝑑𝑄𝑠 /𝑑𝑉|)
=𝐶 − 𝑑𝑄𝑠
𝑜𝑥𝑖𝑑𝑒

Small signal capacitance C of MOS capacitor is

𝑑𝑄𝑚 −𝑑𝑄𝑠
𝐶= = 𝑤ℎ𝑒𝑟𝑒 𝑄𝑚 = −𝑄𝑠 , 𝑎𝑛𝑑 𝑄𝑚 𝑖𝑠 𝑐ℎ𝑎𝑟𝑔𝑒 𝑜𝑛 𝑚𝑒𝑡𝑎𝑙 𝑠𝑖𝑑𝑒
𝑑𝑉 𝑑𝑉
1 1 1
Therefore, 𝐶 = 𝐶 + 𝐶 (20)
𝑜 𝑗

𝑑𝑄 𝜖
where, 𝐶𝑗 = − 𝑑𝜓𝑠 = 𝑊𝑠 is semiconductor space-charge layer capacitance, 𝜖𝑠 is the permittivity of
𝑠
semiconductor, and W is the depletion width.
𝐶 1
=> = 𝐶 (21)
𝐶𝑜 1+ 𝑜
𝐶𝑗

For a given oxide thickness (d), Co is constant and independent of applied voltage (V). => if voltage dependent
Cj is known, ratio C/Co can be plotted with V.
Using the expression of total voltage in terms of maximum depletion width,
𝐶 1
= (30)
𝐶𝑜
2𝑉𝐶𝑜𝑥𝑖𝑑𝑒 2
√1+
𝑞𝜀𝑠 𝑁𝐴

𝐶𝐶𝑜𝑥𝑖𝑑𝑒
𝐶𝑗 =
𝐶𝑜𝑥𝑖𝑑𝑒 − 𝐶
Total capacitance (C) decreases with increase in voltage while surface is being depleted.
When V < 0, no depletion region => accumulation of holes at semiconductor surface.
𝜀𝑜𝑥
=>Total capacitance 𝐶 ≈ 𝐶𝑜 = 𝜒𝑜

𝜖
Here, Cj increases [𝐿 𝑠 ] and 𝐶 ≈ 𝐶𝑜
𝐷

𝜖
When V > 0, W increases, 𝐶𝑗 = 𝑊𝑠 decreases

 C decreases

When V >> 0 ( VT), W  Wm. No change in W with V. Therefore, at

V = VT, sem  sem (inv.)
The threshold voltage at on-set of strong inversion.
𝑞𝑁𝐴 𝑊𝑚
𝑉𝑇 = + 𝜓𝑠𝑒𝑚 (𝑖𝑛𝑣)
𝐶𝑜 𝑥𝑖𝑑𝑒
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Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 √2𝜖𝑠 𝑞𝑁𝐴 (2𝜓𝐵 )
= 𝐶0
+ 2𝜓𝑠𝑒𝑚 (31) (from
equation 28 and 27)
𝑄𝑠
=− + 𝜓𝑠𝑒𝑚 (𝑖𝑛𝑣)
𝐶𝑜
𝜖 𝜀𝑜 𝑥
At strong inversion: 𝐶𝑗 = 𝑊𝑠 and 𝐶𝑜 = 𝜒𝑜

Minimum capacitance is
𝜀 𝜀 𝑥
𝐶𝑜 𝐶𝑗 (𝑤𝑠 ) ( 𝑜 ) 𝜀𝑜 𝑥
𝑑
𝐶𝑚𝑖𝑛 = = 𝜀𝑚 𝜀 𝑥 = 𝜀 𝑥 (32)
𝐶𝑜 +𝐶𝑗 𝑠 𝑜
𝑑 + ( 𝑜 ) 𝑤𝑚
𝑤𝑚 + 𝑑 𝑑
CV curve is measured by superimposing a small ac signal ( 5 mV) on dc bias a shown in figure 13. In depletion
or accumulation regimes, change in charge in response to applied signal requires the flow of majority carriers
(holes in p-type) i.e. moves in or out of space space-charge region.
The relaxation time, c, (time constant for charge transport)  10-12 sec for signal frequency. When
where c << 1, thus C-V curve (accumulation of depletion) is frequency independent.
However, in INVERSION regime: charge flow in response to applied signal may also occur by movement of
minority carriers between inversion layer and the neutral semiconductor, and MOS shows strong frequency
dependence.
If frequency is low so that generation-recombination rates in surface depletion region are equal or faster than
gate.
Voltage variation, then minority carriers (electrons) can follow the applied signal and lead to charge exchange
with inversion layer in step with signal. If e-h pairs generated in Wm before VG goes to zero, the generated holes
will fill hole vacancy in Wm, while generated electron will move into inversion layer. Wm decreases, therefore Cj
= s/Wm start increasing, and total capacitance C will be equal to Co at low frequency (< 100 Hz). All these
considerations are also valid for n-type substrate with proper change in signs and symbols. C-V curve will be of
identical shape (mirror images of each other), and threshold voltage (VT) is a negative quantity for an ideal MOS
diode on an n-type substrate.

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Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)
 Figure 13: CV curve of an ideal MOS capacitor

9. Summary

 Energy band diagram of an isolated metal adjacent to an isolated n-type semiconductor

 Energy band diagram of metal-n semiconductor contact in thermal equilibrium.
 CURRENT TRANSPORT in metal-semiconductor junction
 MOS DIODE
 Different Biasing conditions of an ideal MOS diode
 Interface traps and oxide charges
 C-V characteristics of Ideal MOS capacitor

15

Electronics
Material Science Metal-semiconductor junctions, Metal-oxide semiconductor junctions (MOS
diode)