KSZ8863

KSZ8863 Daughter Board Information Sheet

Abstract

The KSZ8863 Daughter Board (AC320004-7) enables Ethernet communication with a variety of Microchip
starter kits. This information sheet provides an overview and a detailed schematic of the KSZ8863
Daughter Board.
This daughter board is designed specifically to be used with the PIC32 Ethernet Starter Kit II
(DM320004-2) or the PIC32MZ Embedded Connectivity with Floating Point Unit (EF) Starter Kit
(DM320007); however, it can also be used with other Microchip development hardware.
For additional information about the KSZ8863 Daughter Board, visit Microchip web site: http://
www.microchip.com.

1 Features
The KSZ8863 Daughter Board features a 22-pin header for connecting the board into compatible PIC32
starter kits. The board has a KSZ8863 Ethernet Physical Layer Chip, configured to use RMII. The
KSZ8863 Daughter Board is suitable for use with the PIC32 Ethernet Starter Kit II and PIC32MZ EF
Starter Kit.
The following are features of the KSZ8863 Daughter Board:
• RMII interface with MDC/MDIO management interface for register configuration
• Fast start-up and link
• Loopback modes for diagnostics
• Integrated 3-Port 10/100 Managed Switch with PHYs
• IEEE 802.1q VLAN Support
• Optional SPI interface
• Compliant with IEEE 802.3u standard

2 Applications
• VoIP Phone
• Set-Top/Game Box
• Automotive
• Industrial Control
• IPTV POF
• SOHO Residential Gateway
• Broadband Gateway/Firewall/VPN
• Integrated DSL/Cable Modem

© 2019 Microchip Technology Inc. DS50002767B-page 1

 KSZ8863

• Wireless LAN Access Point + Gateway

• Standalone 10/100 Switch

3 Additional Information
For additional information on drivers and examples, follow these links:
• https://www.microchip.com/wwwproducts/en/KSZ8863
• http://www.microchip.com/mplab/mplab-harmony

© 2019 Microchip Technology Inc. DS50002767B-page 2

 1.
J1
VCC_3P3 C1
7499151120 1_1 TX2_P R9 49.9R
GND C4
2_1 TX2_P 10uF
J1 TX2_N R10 49.9R
0.1uF
25V

J2 75Ω 3_1 TX2_N RX2_P R11 49.9R

C5
4_1 RX2_P
J3 RX2_N R12 49.9R 0.1uF
25V
Schematics

J6 75Ω 7_1 RX2_N

5_1 GND TX2_P

TX2_P
J4

TX2_N
TX2_N
J5 75Ω 6_1

© 2019 Microchip Technology Inc.

8_1 RX2_P
RX2_P
J7

Transformers
Compatible Isolation Transfor
f mers RX2_N
RX2_N
J8 75Ω 9_1
Pulse H1102
NC 10_1 Transpower HB726
VCC_3P3
1000 pF 14_1 Bel Fuse S558-5999-U7
Yel R1 YCL PT163020
13_1 P2LED0
SHIELD DELTA LF8505
330R
11_1 P2LED0
P2LED0
Gre R2
12_1 P2LED1 P2LED1
P2LED1
330R
15_1 P1LED0
SHIELD P1LED0
EGND
P1LED1
SHIELD 16_1 P1LED1

VCC_3P3 C2
1_2
GND
2_2 TX1_P 10uF
J1 DNP TX1_P
TX1_P
C3
J2 75Ω 3_2 TX1_N TX1_N
4700pF TX1_N
4_2 RX1_P
R13
J3 RX1_P
RX1_P
0R
J6 75Ω 7_2 RX1_N RX1_N
RX1_N
5_2 EGND GND
J4

J5 75Ω 6_2

8_2
J7
TX1_P R5 49.9R
C6
J8 75Ω 9_2
TX1_N R6 49.9R 0.1uF
10_2 25V
NC
VCC_3P3
1000 pF 14_2 RX1_P R7 49.9R
C7
Yel R3
13_2 P1LED0
49.9R
SHIELD
RX1_N R8 0.1uF
330R
11_2 25V
Gre R4
12_2 P1LED1
330R
15_2 GND
SHIELD
EGND
16_2
SHIELD

DS50002767B-page 3
Schematics
KSZ8863
 Decoupling for
f VCC_3P3 and VDDA_3P3 Decoupling for
f VDDIO and ADDIO
Components close to pins Decoupling for
f VDDA_1P8
Components close to pins 22 & 40
Components close to pin 7
VCC_3P3
_
FB1
VCC_3P3
_ VDDA_3P3
A_ GND GND
FB2
VDD_1P8
_ VDDA_1P8
A_
220R
C17 C18 C19
220R
C8 C9 C10 C12 R16 R17 0.1uF
10uF 0.1uF
1k GND C15 C16
10uF 0.1uF 10uF 0.1uF DNP
1k
10uF 0.1uF

GND
G
GND
GND
G
GND GND
G
GND
GND
G
GND

48 FXSD1
46 P2LED0
45 P2LED1
44 P1LED0
43 P1LED1
42 VDD_1P8
41
40 VCC_3P3
39 SPISN
38 SPIQ
37 SDA_MDIO
U1

GND
SPIQ

RSTN 47 RSTN
SPISN

FXSD1
ADDIO

P2LED0
P2LED1
P1LED0
P1LED1
VDDCO
SDA_MDIO

© 2019 Microchip Technology Inc.

RX1_N 1 36 SCL_MDC
RXM1 SCL_MDC SDA_MDIO
RX1_N SDA_MDIO
RX1_N
RX1_P 2 35 INTRN
RXP1 INTRN SCL_MDC
SCL_MDC
RX1_P TX1_N 3 34 SCRS3
RX1_P TXM1 SCRS3
SPIQ
SPIQ
TX1_P 4 TXP1 SCOL3
SCOL3 33
TX1_N SPISN
TX1_N SPISN
VDDA_3P3 5 32 VDD_1P8
VDDA_3.3 VDDC
R15
TX1_P ISET 6 31
TX1_P GND ISET GND GND
KSZ8863RLL
P1LED0
11.7k P1LED0
VDDA_1P8 7 VDDA_1.8 30 SMRXC3
SMRXC3
P1LED1
P1LED1
RX2_N 8 29 SMRXD30
RXM2 SMRXD30
P2LED0
P2LED0
RX2_N RX2_P 9 28 SMRXD31
RX2_N RXP2 SMRXD31
P2LED1
P2LED1
SMRXD32
GND 10 AGND
SMRXD32 27
RX2_P
RX2_P
TX2_N 11 26 SMRXD33
TXM2 REFCLKO_3/SMRXD33
SMRXD30
SMRXD30
TX2_N TX2_P 12 25 SMRXDV3
TX2_N TXP2 SMRXDV3
SMRXD31
SMRXD31
TX2_P SMRXD32
TX2_P SMRXD32
SMRXD33
SMRXD33

N/C
X2
SMTXEN3
SMTXD33/EN_REFCLKO_3
SMTXD32
SMTXD31
SMTXD30
GND
VDDIO
REFCLKI_3/SMTXC3
MII_LINK_3/SMTXER3
SMRXDV3

13
14 X1
15
16
17
18
19
20
21
22
23
SMRXDV3
P1LED0
P1LED0

X1
X2
P1LED1 SMTXD30
P1LED1 SMTXD30

SMTXEN3
SMTXD32
SMTXD31
SMTXD30
VCC_3P3
P2LED0 SMTXD31
P2LED0 SMTXD31
P2LED1 50MHz Clock Select Options SMTXEN3
P2LED1 SMTXEN3

REFCLKI_3/SMTXC3
MII_LINK_3/SMTXER3 24
GND
REFCLKI_3/SMTXC3
_ R20 CLK_IN MII_LINK_3/SMTXER3
MII_LINK_3/SMTXER3

SMTXD33/EN_REFCLKO_3
33R

X1 R21
33R
POWER-ON RESET Crystal Characteristics INTRN
Frequency - 25MHz +/- 50 ppm INTRN
Load Capacitance - 20pF CLK_IN
CLK_IN
K _3

VCC_3P3
_ Series Resistance - 40 Ohms VCC_3P3
_ RSTN
RSTN
E CLKO

X1
R18

X1
X2
25MHz
E _REF

D1 R14 1k
10k DNP DNP
1N4148
R
X 33/EN
X 32

RSTN
C13 C14
REFCLKI_3/SMTXC3
SMTXD33/EN_REFCLKO_3
SMTXD
SMTXD32
SMTXD

M XER3

DNP 18pF 18pF DNP

R19 R22 R23
C11 1k
DNP 1k 1k
10uF
MII_LINK_3/SMTXER3
MII_LINK_3/SMT

GND
G
GND
GND
GND
G GND GND
G
GND GND
G
GND

DS50002767B-page 4
Schematics
KSZ8863
 VCC_3P3 SPI Communication Option
Port Configuration Options
DNP
SPISN R44 = Placed
R34 R35 R44
1k 1k 1k
VCC_3P3
_ SPIQ R24 = Placed
SPIQ R24 DNP SMRXD30 R30 DNP
1k 1k
SMRXD31 R31 DNP
I2C Communication
SMRXDV3 R25 DNP
1k
1k SCL_MDC
SMRXD32 R32 DNP SDA_MDIO
DNP R34 & R35 Replace with 4.7k
P1LED1 R26 SPISN
1k
1k
SMRXD33 R33 DNP
P1LED0 1k
P1LED0 GND
G
GND
P1LED1
P1LED1 VCC_3P3
_
P2LED0 DNP
P2LED0 P1LED0 R27 GND
G
GND

© 2019 Microchip Technology Inc.

P2LED1 4.7k
P2LED1 NOTE !!
Signals INTRN and RSTN, Pins 35 and 47 have
PORT 1 - OPTIONS PORT 2 - OPTIONS internal pull-up resistors integrated into the pad structure
SPIQ
SPIQ
Force Flow Control Force Flow Control
SPISN SPIQ DNP = ENABLE SMRXD30 DNP = ENABLE
SPISN
Placed = DISABLE Placed = DISABLE
SDA_MDIO
SDA_MDIO Force Full/Half Duplex Force Full/Half Duplex 3 3
SCL_MDC SMRXDV3 DNP = FULL DUPLEX SMRXD31 DNP = FULL DUPLEX 2 2
SCL_MDC Placed= HALF DUPLEX Placed= HALF DUPLEX 1 1
Force Speed Force Speed J3 J4
DNP = 100BaseTX DNP = 100BaseTX SMTXEN3 49.9R R36
P1LED1 SMRXD32 EGND EGND
SMRXD30 Placed = 10BaseT Placed = 10BaseT
SMRXD30
SMTXD30 49.9R R37
SMRXD31 Auto-Negotiation Auto-Negotiation
SMRXD31
P1LED0 DNP = ENABLE SMRXD33 DNP = ENABLE SMTXD31 49.9R R38 TX_EN RXD1 49.9R R45 SMRXD31
1 1
SMRXD32 Placed = DISABLE Placed = DISABLE TXD0
SMRXD32 2 2 RXD0 49.9R R46 SMRXD30
SDA_MDIO 33R R39 TXD1
3 3
SMRXD33 SPI_MOSI 4 4
RXER 49.9R R47 MII_LINK_3/SMTXER3
SMRXD33
SPIQ 33R R40 SPI_MISO
5 5 CRS_DV49.9R R48 SMRXDV3
SMRXDV3 6 6
SMRXDV3
XTAL1
7 7 MDC 33R R49 SCL_MDC
GND
G
GND CLK_IN 8 8
MDIO 33R R50 SDA_MDIO
9 9
SMTXD30
SMTXD30 VCC_3P3 10 10 nINT 33R DNP R51 INTRN
SPI_SS 11 11
SMTXD31 SPI_CLK nRST 33R R52 RSTN
SMTXD31 12 12

SMTXEN3 SPISN 33R R41 J2 J5

SMTXEN3
MII_LINK_3/SMTXER3 SCL_MDC 33R R42
MII_LINK_3/SMTXER3
Bus Communication Configuration EGND

INTRN
INTRN
RSTN
RSTN DNP
P2LED1 R28
CLK_IN
CLK_IN 1k
DNP Clock Source Configuration
P2LED0 R29
1k
Pin 17 SMTXT D33
SMTXD33 Pin 18 SMTXD32
SMTX
T D32
Reg198 bit [3] /EN_REFCLK0_3 Internal Pull-Up Clock Source Note
Internal Pull-Up (For Rev A3)
A
External 50MHz OSC input EN_REFCLK0_3 = 0
GND
G
GND 0 0 0 to SMTXC3/REFCLKI_3
SMTX
T C3/REFCLKI_3 to Disable REFCLK0_3
(use 1k Pull-Down) (use 1k Pull-Down) and X1 pin directly for better EMI

50MHz on X1 pin is clock EN_REFCLK0_3 = 1

source. REFCLK0_3
[ P2LED1, P2LED0 ] Serial Bus Configuration 0 1 0 Output is Feedback to Ensable REFCLK0_3
(use 1k Pull-Down) to REFCLKI_3 externally
[ Placed,Placed] I2C (master mode) EEPROM 25MHz on X1 pin is clock
EN_REFCLK0_3 = 1
source. REFCLK0_3
0 1 1 Output is connected to Ensable REFCLK0_3
[ Placed,DNP ] I2C Slave Mode
to REFCLKI_3 externally
[ DNP,Placed ] SPI Slave Mode 25MHz on X1 pin, 50MHz RMII EN_REFCLK0_3 = 0
0 or 1 SMTX
T C3/
Clock goes to SMTXC3/
1 to Disable REFCLK0_3
0
[ DNP,DNP ] SMI Mode REFCLKI_3 internally
REFCLKI_3 is unconnected for
f better EMI

DS50002767B-page 5
Schematics
KSZ8863
 KSZ8863
Revision History

2. Revision History
Revision B - March 2019
The following changes were implemented for this release:
• Updated the schematics:
– Added the property and notation DNP to the resistor R51
• Updated document format

Revision A - June 2018

Initial release of this document.

© 2019 Microchip Technology Inc. DS50002767B-page 6

 KSZ8863

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© 2019 Microchip Technology Inc. DS50002767B-page 7

 KSZ8863

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their
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All other trademarks mentioned herein are property of their respective companies.

© 2019 Microchip Technology Inc. DS50002767B-page 8

 KSZ8863

© 2019, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.
ISBN: 978-1-5224-4249-3

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© 2019 Microchip Technology Inc. DS50002767B-page 9


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DS50002767B-page 10
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