1 2 3 4 5 6 7 8

RX2
TX2

RX4
TX4
LED BL R22
MUSIC SPEAKER
100K

R7
R6
R5
R4
R3
R2
R1
R0

G7
G6
G5
G4
G3
G2
G1
G0
<=1.5W 5V 33uH SD_CLK
<=2.5W 5V 22uH Speaker Output

129

128
127
126
125
124
123

122
121
120
119

118
117

116
115
114
113
112
111
110
109

108
107

106
105
104
103
102
101
100
+5V C37 IC6

99

98
97
>2.5W 5V 10uH 104 NS4150B
1 8
EN OUT+

33uH
C5 C23

VIO

VIO

VIO
TX2/04
CRX/03

R7/67
R6/66
R5/65
R4/64
R3/63
R2/62
R1/61
R0/60
RX5

RX4
GND

RX2/05

CTX/02
TR5/01
TR4/00

VDD

VDD

G7/57
G6/56
G5/55
G4/54
G3/53
G2/52
G1/51
G0/50

VDD
TX5

TX4
R9

L1
470P 105 2 7
10R BP GND
M2 C20
R23 47K
96 B7 3404 3 6 470p//106
B7/47 IN+ VCC
D 1 95 B6 LED+ +5V D
TX3/06 B6/46 R24 47K
2 94 B5 C33 4 5
RX3/07 B5/45 IN- OUT-
93 B4 PWMI D1 223

8R 3W
B4/44 R21 10R

SPK1
3 92 B3 SS14 Z1
VDD B3/43 C35 R25

470P//106C
4 91 B2 13V
VIO B2/42 223 2.2K
90 B1 SPK C21
B1/41
5
P10
T5L B0/40
89 B0
C36
470p

C3
6
P11 R7 104//470p
7 88
P12 VIO 100R
8 87 IF_0.4 LED-
P13 VDD

ILED=400/R8 mA
9 Max HVGA difference of Chip Apps
P14
10 86 VS
P15 IC Bit color TA Mode DGUS II Mode VS/37
11 85 HS LCD data interface
P16 HS/36 R8 R4 10K
12 T5L0 18bit 1024*768 854*480 84 DE C4
P17 CPU_OS DE/35 RGB LCD INTERFACE 10R
83 PCLK 103 C11
T5L1 24bit 1366*768 720*720 PCK/34 R12
13 82 470p//106
VDD 33 22K
14 T5L2 24bit 1920*1080 1366*768 81 CS_C
VIO 32
80 CS_B
31
15 PS:DGUS II T5L1 MB not exceed 512*1024 79 DW3 DW2

VGL
P20 CKO/30
16 6.8V 16V
P21
17 78
P22 VIO
18 PACKAGE:ELQFP128 77 IC2
P23 VDD
19 74HC138 Multi SPI Flash C13

VGH
P24 R3 10K R10
20 VDD=1.25V T5L1 76 TPX0 +3.3 CS_A 1 16 +3.3 470p//475
P25 X0/27 A VCC 470R
21 VDD=1.20V T5L2/T5L0 75 TPY0 CS_B 2 15 CS0 16MB
P26 Y0/26 B Y0
22 74 TPX1 CS_C 3 14 CS1 32MB
P27 VDDPLL=VDD X1/25 C Y1
73 TPY1 4 13
Y1/24 R19 10K E1 Y2 D2
JTAG Debug Select: 23 VIO=3.3V 72 SPI_CK 5 12 R15
C VDD SCK/23 R13 10K E2 Y3 4148 C
24 AVDD=3.3V 71 CS_A +3.3 6 11 1K
0=GUI 1=OS VIO SCS/22 E3 Y4
VREF=3.3V CPU_GUI 70 SD_CMD +3.3 7 10 D6
CMD/21 Y7 Y5
25 69 SD_CLK 8 9 CS6 4148
P30/X0 CLK/20 R2 4.7K GND Y6 D7
JP1 26
P31/X1 4148
JUMPER 27 68 112MB
P32 VIO Used in add Flash !
28 67 C14
P33 VDD C12
29 103
GND 103
ON:JTAG GUI
OFF:JTAG OS

30 66 DATA3 +3.3 +3.3

GND SD3/17
31 65 DATA2 5V IO to 3.3V IO 3.3V T5L TXD to 3.3V TXD
1

GND SD2/16 D4
32 470p
OS/UI R11 R40 470p//106C 4148
4.7K 22K
VDDPLL

D3 C16
TMS/00

TDO/03

PW0/10
PW1/11
PW2/12
PW3/13
TCK/01

SD0/14
SD1/15
C19
JTAGS

TDI/02

AGND
AVDD

XOUT
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7

VREF

SS14 AVDD
VDD
/RST

FRX
FTX
RX1
TX1

XIN

VIO

DIN RXD? DOUT TXD?

R28 AVDD=10.3V R30
10R 12K
C24 470p
33
34
35
36
37
38
39
40
41
42

43
44
45
46
47
48
49
50

51
52
53
54

55
56

57
58

59
60
61
62
63
64
R26
10K R35 R29

4
XT1
TCONSCL
TCONSDA

DATA0
DATA1

+5V
T5L1:2.2K//2.2K
TCONCS
/RST

PWMI
JTAGS

SPK

T5L2/L0=1.0K 1K
IF_0.4

+3.3 +1.2 +1.2

TDO

VOUT

FB
SW
R1
ADX0
ADY0
ADX1
ADY1

C41 C40 11.0592MHz C25 106 L3

4.7K

4
C1 C2
R5 4.7K

R6 4.7K

+3.3
470P//105

470P//105

22pJ 22pJ
1.2V Core 10uH IC4

R34

VIN
FB0.6
1K
TLV61046A

GND
VIN

EN
B IC5 B
TLV62568
JTAG PRG

+3.3

+5V
TCONCS C9 C28

GND

3
CS_A @ only 1 FLASH

SW
470P//105

EN
TCONSCL T5L0 Min60uF /RST
TCONSDA 3 CS0 1 8 +3.3 C18 LCD Bias
Power On Reset /CS VCC T5L1,T5L2 Min 40uF
TDO SGM809S +5V
R32
1 2 DATA1 2 7 DATA3

3
IO1 IO3 10K L2
JTAGS +5V 470p//106
R14 2.2uH
DATA2 3 6 SPI_CK +1.2
4.7K IO2 SCK
JTAG Interface
IC7
4 5 DATA0 C26 C31
GND IO0 SGM2019-33

226*3
C10 470p 103

C27

C28
470p
/RST

470p SPI Nor Flash 4 3

IC3 BP EN
GD/FM/BY/XTX25Q32/64/128 R33
10R
R39 2
3.3K GND
SD/SDHC C6 103
R38
CTP
220K 100K
R41 +3.3 5 1 +5V
DET VOUT VIN
TPX0
/RST
DATA1 Z6 C29

104
DAT1 Z2 5.1V

330K
5RTP 5.1V 4RTP 470p//226//226
R20
DATA0 C7 103 TPY0
DAT0 Z7 SCL 10R
TPY1 TPX0 ADX0 +5V
RD 5.1V X

C34
R42 220K

470p//106

R37
GND 3.3V IO
TPX1 C38 470P TPX1
RU /INT
SD_CLK TPY0 ADY0 D5

C32
CLK R27 100K Y
A ADX0 Z3 5.1V 4148 A
C39
22p

TP BUZZ
+3.3 TPY1
VCC SDA
TPY0 Z8 TPX1 ADX1 C8 103 M4
LU X
SD_CMD 5.1V 3404
CMD
TPX0 Title
LD Z9 R27*
DATA3 TPY1 ADY1 T5L UI TA&DGUS2
DAT3 5.1V Y Z4 5.1V 4.7K
+3.3 SPK
DATA2 Z6 C15 103 BUZZ Size Number Revision
DAT2 CTP Interface
5.1V
4RTP Interface Buzzer A3
SD/SDHC 5RTP Interface
Date: 6-Jan-2022 Sheet of
Z5 5.1V
File: F:\硬件研 发组管理\钉钉群 文件\PCB标准化 相关文件
Drawn By: \T5L原理图 \DEMO.ddb
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