CMOS Digital Integrated Circuits

Analysis and Design 4th Edition Kang

Solutions Manual
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CHAPTER 7

COMBINATIONAL MOS LOGIC CIRCUITS

Exercise Problems

7.1 A CMOS circuit was designed based on company XYZ’s 3-  m design rules, as
shown in Fig. P7.1 with WN = 1.2  m and WP = 2.4  m.

(a) Determine the circuit configuration and draw the circuit diagram.
(b) For simple hand analysis, make the following assumptions:
i) Wiring parasitic capacitances and resistances are negligible.
ii) Device parameters are

nMOS pMOS
VT0 0.53 V –0.51 V
tox 16 Å 18 Å
k' 98.2  A/V2 46  A/V2
Xj 32nm 32nm
LD 10nm 10nm
ECL 0.4V 1.8V

iii) The total capacitance at node I is 0.1 pF.

iv) An ideal step-pulse signal is applied to the CK terminal such that

VCK = 1.2 V, t<0

VCK = 0 V, 0 ≤ t < Tw
VCK = 1.2 V, t ≥ Tw
VDD = 1.2 V

v) At t = 0, the node voltage at I is zero.

vi) The input voltages at A1, B1, and B2 are zero for 0 ≤ t ≤ TW.

Find the minimum TW that allows VI to reach 0.6 V.

Figure P7.1

SOLUTION :
(a)
 VDD

CK

I Z

B1

B2

(b)
In PMOS
VGS  VT , p  1.2  0.51  0.69
VDS  VDD  VI
 for VI  0.51 , PMOS is in saturation region.

VI 0.51 dVI VI 0.6 dVI

Tw  CI [  ( ) ( )]
VI 0 I D, sat VI 0.51 I
D ,linear

(VDD  VT , p )2 98.2 106 1.8  (2400 / 40) (1.2  0.51) 2

I D ,sat  W  vsat  Cox     1.014mA
(VDD  VT , p )  EC Lp 2 (1.2  0.51)  1.8
VI 0.51 dVI 0.51CI
CI    50.3 ps
VI 0 I D ,sat I D ,sat

kp 1
I D ,linear   2  (VDD  VT , p ) VI  VI 2 
2  V 
1  I 
 EC Lp 
VI 0.6 dVI
CI  ( )  18.66 ps
VI 0.51 I
D ,linear

Tw  50.3  18.66  68.96 ps

7.2

Calculate the equivalent W/L of the two nMOSTs with W1/L and W2/L connected in series. For
simplicity, neglect the body effect, i.e., the threshold voltages of individual transistors are constant
and do not depend on the source voltages. Although this is not true in reality, such an assumption
is necessary for simple analysis with a reasonably good approximation.
SOLUTION:
VDS VDS
W1/L
VG IDS1
Weq/L
VDS2 VG IDS

IDS2
W2/L

We know that IDS=IDS1=IDS2, assuming all transistors are operating in linear region, neglecting body
effect,

nCox  W1  1  2  (VG  VDS 2  VT 0 ) VDS  VDS 2   VDS  VDS 2 2 

I DS  I DS 1   
2  L   VDS  VDS 2   
 1  
 EC ,n Ln 
W 
 k1  1   2  (VG  VDS 2  VT 0 ) VDS  VDS 2   VDS  VDS 2  
2

 L  
 C W  1
I DS  I DS 2  n ox  2   2  (VG  VT 0 )VDS 2  VDS 2 2 
2  L  VDS 2 
1  
 EC ,n Ln 
W 
 k2  2   2  (VG  VT 0 )VDS 2  VDS 2 2 
 L 
Rewriting the first equation, we obtain,
W 
I DS  k1  1   2  (VG  VDS 2  VT 0 )VDS  2  (VG  VDS 2  VT 0 )VDS 2  VDS2
 2VDSVDS 2  VDS2

2
 L
W  W 
 k1  1   2 VG  VT 0  VDS  VDS2
  k1  1   2 VG  VT 0 VDS 2  VDS
2

2
 L  L
W  kW W  kW
 k1  1   2 VG  VT 0  VDS  VDS2
  1 1 I DS 2  k1  1   2 VG  VT 0 VDS  VDS
2
  1 1 I DS
 L k2W2  L k2W2

rearranging the above equation,

 k1W1   W1 
1   I DS  k1    2 VG  VT 0 VDS  VDS 
2

 k 2 2 
W  
L
k k WW  1 
I DS  1 2 1 2    2 VG  VT 0  VDS  VDS 2

k1W1  k2W2  L 
nCox Weq 1
    2  (VG  VT 0 )VDS  VDS 
2

2  VDS   L 
1  
 EC ,n Ln 
W1 W2
 VDS  VDS 2   VDS 2 
1   1  
 EC ,n Ln   EC ,n Ln  Weq

W1

W2  VDS 

VDS 2   EC ,n Ln 

 VDS  VDS 2   1
 1    1    
 EC , n Ln   E C , n Ln 
rearranging the above equation,
WW
Weq  1 2

 EC ,n Ln  VDS 2   EC ,n Ln  VDS  VDS 2 

W1    W2  
 EC ,n Ln  VDS   EC ,n Ln  VDS 
WW
 1 2
W1  W2 
where, α, β < 1.
If we compare this result with long channel transistor case, assuming W 1=W 2=2μm, α=β=0.9.
WW WW 4
Weq  1 2
 1 2  1
Long-channel:
W1  W2  W1  W2 2  2
WW 4
Weq  1 2
  1.11
Short-channel:
W1  W2  1.8  1.8
Therefore, stacked transistor logic with short channel device does not need to be increased as
much as in the long-channel case.

7.3 Analytical expressions for Vth(logic) have been derived in Chapter 7 for the CMOS
NOR2 gate. Now consider the CMOS NAND2 gate for the following cases and use
kp = kn = 100 uA/V2:

• two inputs switching simultaneously

• top nMOS switching while the bottom nMOS’s gate is tied to VDD
• top nMOS gate is tied to VDD and the gate input of the bottom nMOS is changing
 (a) Derive an analytical expression for Vth corresponding to the first case. Also find

the Vth value for the first case for VDD = 1.2 V when the magnitudes of the threshold

voltages are VTn = 0.53 V, VTp = –0.51 V with  = 0.

(b) Determine Vth for all three cases by using SPICE.

(c) For Cload = 0.2 pF, calculate 50% delays (low-to-high and high-to-low
propagation delays) for an ideal pulse input signal for each of the three cases by
assuming that Cload includes all of the internal parasitic capacitances. Verify the results
using SPICE.

SOLUTION :

(a) Considering Figure 7.15. When both transistors are switching simultaneously, transistor
M1 is in saturation and M2 is in linear region. Let VD2 be the internal node voltage.
(Vth  VT ,n  VD 2 ) 2
I M 1  W  vsat  Cox 
(Vth  VT ,n  VD 2 )  EC Ln
kn  EC Ln (Vth  VT ,n  VD 2 ) 2
 
2 (Vth  VT ,n  VD 2 )  EC Ln
1
 kn (Vth  VT ,n  VD 2 ) 2 (if Vth  VT ,n  VD 2 EC Ln )
2

kn 1
IM 2   2  (Vth  VT ,n ) VD 2  VD 2 2 
2  VD 2 
1  
 EC Ln 
1
 kn  2  (Vth  VT ,n ) VD 2  VD 2 2  (if VD 2 EC Ln )
2
From the first equation, we have
2I D
VD 2  Vth  VT ,n 
kn
Plug into the second equation, the following can be found:
ID
Vth  VT ,n  2
kn

Both PMOS transistor are in saturation.

VGS 3  VGS 4  Vth  VDD
 (VDD  Vth  VT , p ) 2
I D  I M 3  I M 4  k p  EC Lp 
(VDD  Vth  VT , p )  EC Lp
 k p  (VDD  Vth  VT , p ) 2 (if VDD  Vth  VT , p EC L p )
kp
VT ,n  2 (VDD  VT , p )
kn
Vth   0.637V
kp
1 2
kn
VD 2  0.031
(b) SPICE simulation results

Case 1: two inputs switching simultaneously

VTH = 625mV

Case 2: top nMOS switching while the bottom nMOS’s gate is tied to VDD
VTH.TOP = 595mV

Case 3: top nMOS gate is tied to VDD and the gate input of the bottom nMOS is changing

VTH = 594mV
The figure below shows the three simulation plotted on one graph.

(c) Calculate output from high to low

Case 1:
In this case, an equivalent nMOS transistor can be used with half the size. Thus,
100  0.4  3 (1.2  0.53)2
I D (Vin  1.2, Vout  1.2)    25.2uA
2 (1.2  0.53)  0.4
100 3
I D (Vin  1.2, Vout  0.6)     2 1.2  0.53 0.6  0.62   26.645uA
2 1  0.6 
0.4
1
I avg , HL  (25.2  26.645)  25.92uA
2
C V
tPHL  load  4.63ns
I avg , HL
SPICE simulation result: 1.8ns

Case 2:
At Vin=1.2V, Vout=1.2V, M1 in saturation M2 in linear,
(VDD  VT ,n  VD 2 ) 2
I M 1  W  vsat  Cox 
(VDD  VT ,n  VD 2 )  EC Ln
kn  EC Ln (VDD  VT ,n  VD 2 ) 2
 
2 (VDD  VT ,n  VD 2 )  EC Ln

kn 1
IM 2   2  (VDD  VT ,n ) VD 2  VD 2 2 
2  VD 2 
1  
 EC Ln 
 Solve for VD2,
VD 2  0.031V
100u  0.4  6 (1.2  0.53  0.031)2
I D (Vin  1.2, Vout  1.2)    47.16uA
2 (1.2  0.53  0.031)  0.4

At Vin=1.2V, Vout=0.6V, M1 and M2 in linear,

VD 2  0.22V
100u  6 1
I D (Vin  1.2, Vout  0.6)  2  (1.2  0.53)  0.22  0.22 2   47.7uA
2  0.22  
1  
 0.4 

1
I avg , HL  (47.16  47.7)  47.43uA
2
C V 0.2 1012  0.6
tPHL  load   2.53ns
I avg , HL 47.43 106

SPICE simulation result: 1.78ns

Case 3: top transistor is tied to VDD, bottom transistor is switching.

In this case, transistor M1 is in saturation at the edge of turn-on and the internal node voltage is
0.67V. Thus,
100 106  6 1
I D (Vin  1.2, Vout  1.2)  2  (1.2  0.53)  0.67  0.67 2   50.34uA
2  0.67 
1  
 0.4 
100 106  6 1
I D (Vin  1.2, Vout  0.6)  2  (1.2  0.53)  0.6  0.6 2   53.28uA
2  0.6 
1  
 0.4 
1
I avg , HL  (50.34  53.28)  51.81uA
2
C V 0.2 1012  0.6
tPHL  load   2.32ns
I avg , HL 51.81106

SPICE simulation result: 1.78ns

7.4 Write down the SPICE input description for transistor connections, source
and drain parasitics in terms of areas, and perimeters for the layout shown in Example 7.2.
Neglect the wiring capacitances in the polysilicon and metal runners. Default model names to
be used for pMOS and nMOS are MODP and MODN. Assume L = 60nm and Y = 0.175  m
for all transistors.

SOLUTION :
The circuit diagram is redrawn here with the node numbers

The SPICE input description is

Vdd 99 0 dc 1.2
mn1 4 1 0 0 nmod w=176n l=60n AS=31.7f AD=15.8f PS=704n PD=352n
mn2 4 2 0 0 nmod w=176n l=60n AS=15.8f AD=15.8f PS=352n PD=352n
mn3 4 3 0 0 nmod w=176n l=60n AS=15.8f AD=15.8f PS=352n PD=352n
mn4 7 5 4 0 nmod w=176n l=60n AS=15.8f AD=15.8f PS=352n PD=352n
mn5 7 6 4 0 nmod w=176n l=60n AS=31.7f AD=15.8f PS=704n PD=352n
mp1 10 1 99 99 pmod w=176n l=60n AS=31.7f AD=15.8f PS=704n PD=352n
mp2 9 2 10 99 pmod w=176n l=60n AS=15.8f AD=15.8f PS=352n PD=352n
mp3 7 3 9 99 pmod w=176n l=60n AS=15.8f AD=15.8f PS=352n PD=352n
mp4 7 5 8 99 pmod w=176n l=60n AS=15.8f AD=15.8f PS=352n PD=352n
mp5 8 6 99 99 pmod w=176n l=60n AS=31.7f AD=15.8f PS=704n PD=352n

7.5 For the gate shown in Fig. P7.5,

■ Pull-up transistor ratio is 5/5
■ Pull-down transistor ratios are 100/5
■ VTn= 0.53 V
■ VTp=0.51 V
1/2
■ γ=0.574 V
■ |2Φ|=1.020 V
■ EC,nLn=0.4 V
■ EC,pLp=1.8 V
a. Identify the worst-case input combination(s) for VOL.
b. Calculate the worst-case value of VOL. (Assume that all pull-down transistors have the same
body bias and initially, that VOL≈ 5% VDD.)
 Figure P7.5

SOLUTION:
(a) The worst case input combinations are those that cause only one current path from output to
ground. The combinations are listed in the following table.
A=1 C=1 B=0
A=1 C=1 C=0 E=0
B=1 D=1 A=0 E=0
B=1 D=1 C=0 E=0
B=1 E=1 A=0 D=0
B=1 E=1 C=0 D=0

(b) The worst case equivalent circuit can be represented by a simple inverter. Both transistors are
operating in linear region.
VT ,up  VT 0    
| 2 F  VSB |  | 2 F |  0.53  0.574  
0.06  1.02  1.02  0.5468
VT ,down  0.53
From P7.2, when W=W 1=W 2, W eq can be expressed as
W W
Weq  
1 EC ,n Ln
1 1
1
VDS E L
C ,n n  VOL
EC ,n Ln
nCox  5  1  2  (2  VOL  0.5468)  2  VOL    2  VOL 2 
 
2  5   1.2  VOL   
1  
 0.4 
100
0.4
1
nCox 0.4  VOL 1
  2  (1.2  0.53)VOL  VOL 2 
2 5  VOL 
1  
 0.4 
Solve for VOL, since VOL is small, no iteration of VT,up is needed in this case.
VOL=0.035V
7.6 A store has one express register and three regular ones. It is the store policy that the express
register be open only when two or more of the other registers are busy. Assume that the Boolean
variables A, B, and C reflect the status of each of the regular registers (1 one busy, zero0 idle).
Design the logic circuit, with A, B, and C as inputs and F as output, to automatically notify the
manager (by setting F = 1) to open the express register. Present two solutions, the first using only
NAND gates, the second using only NOR gates.

SOLUTION:
For NAND gate implementation

   
F  AB  AC  BC  AB  AC  BC
For NOR gate implementation

  
F  ( A  B)( A  C )( B  C )  A  B  A  C  B  C   
7.7 Calculate VOL, VOH, VIL, VIH, NML, and NMH for a two-input NOR gate fabricated
with CMOS technology.

(W/L)p = 4
(W/L)n = 1
VTn = 0.53 V
VTp = –0.51 V
 n Cox = 98.2  A/V2
 p Cox = 46  A/V2
VDD = 1.2 V

Compare your answers with SPICE simulation results.

SOLUTION :
The equivalent inverter for the NOR gate.
(W / L)eq ,n  2(W / L)n  2
1
(W / L)eq , p  (W / L) p  2
2
therefore
kn,eq  kn '(W / L)eq ,n  196.4 A / V 2
k p,eq  k p '(W / L)eq , p  92 A / V 2
VOL  0V
VOH  VDD  1.2V

Calculate VIL
1
 kn  kn 

Vout  
  1  V  V  V  V 
2  IL T 0, n T 0, p DD
 k p  kp 

Vout  1.567VIL  0.289
 kn  V  VDD 
(VIL  VT 0,n )2  k p VIL  VDD  VT 0, p  out  (Vout  VDD )
2  2 
VIL  0.207V

Calculate VIH
1 k p  kp 

Vout  1  VIH  VT 0,n  (VDD  VT 0, p ) 
2 kn  kn 

Vout  0.734VIH  0.427
 V  kp
kn  VIH  VT 0,n  out Vout  (VIH  VDD  VT 0, p )2
 2  2
VIH  0.61V

NM L  0.207  0  0.207V
NM H  1.2  0.61  0.59V

7.8 Use a layout editor (e.g., Magic) to design a two-input CMOS NAND gate.
All devices have W = 0.6 m. The n-channel transistors have Leff = 60 nm and the p-
channel transistors have Leff = 120 nm. Calculate the drawn channel lengths by assuming that
LD = 15 nm. Use the design rule checker to avoid rule violations. Finally, have the layout editor
perform parasitic capacitance extraction.

SOLUTION :
1. Layout
2. Parasitic extraction result

.subckt PM_06319PRO7_8%VDD 3 5 7 10 12 14 17 19 21 25 28 45
c19 30 0 0.00437298f
c20 29 0 0.00437298f
c21 25 0 0.0417278f
c22 21 0 0.0348879f
c23 19 0 0.0601717f
c24 17 0 0.00703762f
c25 14 0 0.0315598f
c26 12 0 0.0601717f
c27 10 0 0.00823824f
c28 7 0 0.0210509f
c29 5 0 0.120343f
c30 3 0 0.044639f
c31 2 0 0.0154647f
r32 23 25 0.39619
r33 22 30 0.0529971
r34 21 23 0.0983284
r35 21 22 0.386667
r36 17 19 8.66667
r37 16 30 0.0314258
r38 16 17 0.924444
r39 15 29 0.0529971
r40 14 30 0.0529971
r41 14 15 0.733333
r42 12 45 4.06829
r43 10 12 8.66667
r44 9 29 0.0314258
r45 9 10 0.924444
r46 8 28 0.0549107
r47 7 29 0.0529971
r48 7 8 0.386667
r49 25 5 8.66667
r50 3 5 8.66667
r51 2 28 0.0434177
r52 2 3 0.39619
.ends

.subckt PM_06319PRO7_8%GND 3 5 7 10 12 14 18 21
c18 22 0 0.00437298f
c19 18 0 0.0417278f
c20 14 0 0.0348488f
c21 12 0 0.0601886f
c22 10 0 0.00751075f
c23 7 0 0.0509513f
c24 5 0 0.120343f
c25 3 0 0.0467866f
c26 2 0 0.0154257f
r27 16 18 0.39619
r28 15 22 0.0529971
r29 14 16 0.0983284
r30 14 15 0.386667
r31 10 12 8.66667
r32 9 22 0.0314258
r33 9 10 0.924444
r34 8 21 0.0581944
r35 7 22 0.0529971
r36 7 8 1.08
r37 18 5 8.66667
r38 3 5 8.66667
r39 2 21 0.0401341
r40 2 3 0.39619
.ends

.subckt PM_06319PRO7_8%OUT 2 4 6 7 9 15 17 22 24 25
c30 24 0 0.0601717f
c31 17 0 0.00322683f
c32 15 0 0.0414075f
c33 9 0 0.00538588f
c34 7 0 0.00580636f
c35 6 0 0.00501621f
c36 4 0 0.0601886f
c37 2 0 0.00737792f
r38 17 19 0.24
r39 13 19 0.04
r40 13 15 1.36
r41 24 11 2.69678
r42 25 11 2.69678
r43 9 11 8.66667
r44 8 19 0.08
r45 8 9 1.05778
r46 6 17 0.04
r47 6 7 0.302222
r48 4 22 4.24411
r49 2 4 8.66667
r50 1 7 0.0893966
r51 1 2 0.817778
.ends

.subckt PM_06319PRO7_8%NET14 6 7 8
c8 8 0 0.00207785f
c9 6 0 0.0601717f
r10 7 8 2.81333
r11 6 8 2.81333
.ends

.subckt PM_06319PRO7_8%A 15 16 20 24
c17 20 0 0.0319113f
c18 16 0 0.0121695f
c19 15 0 0.00527354f
r20 20 24 171.35
r21 19 24 37.25
r22 15 19 11.1725
r23 15 16 47.1833
.ends

.subckt PM_06319PRO7_8%B 16 20 21 22
c16 22 0 0.0121695f
c17 21 0 0.00495424f
c18 16 0 0.0345129f
r19 21 22 47.1833
r20 16 20 119.2
r21 21 15 11.1725
r22 15 20 89.4
.ends

.subckt Pro7_8 GND OUT A B

MM0 N_OUT_MM0_d N_A_MM0_g N_NET14_MM0_s N_GND_MM0_b nmos L=6e-08
W=6e-07
MM1 N_NET14_MM1_d N_B_MM1_g N_GND_MM1_s N_GND_MM0_b nmos L=6e-08
W=6e-07
MM2 N_OUT_MM2_d N_A_MM2_g N_VDD_MM2_s N_VDD_MM2_b pmos L=1.2e-07
W=6e-07
MM3 N_OUT_MM3_d N_B_MM3_g N_VDD_MM3_s N_VDD_MM2_b pmos L=1.2e-07
W=6e-07

C0 OUT GND 0.01pF

x_PM_06319PRO7_8%VDD N_VDD_c_1_p N_VDD_MM2_b N_VDD_c_2_p

+ N_VDD_c_4_p N_VDD_c_15_p N_VDD_c_6_p N_VDD_c_9_p
+ N_VDD_MM3_s N_VDD_c_12_p N_VDD_c_13_p VDD N_VDD_MM2_s
+ PM_06319PRO7_8%VDD
x_PM_06319PRO7_8%GND N_GND_c_20_n N_GND_MM0_b N_GND_c_22_n
+ N_GND_c_28_p N_GND_MM1_s N_GND_c_29_p N_GND_c_30_p GND
+ PM_06319PRO7_8%GND
x_PM_06319PRO7_8%OUT N_OUT_c_47_n N_OUT_c_60_p N_OUT_c_49_n
N_OUT_c_38_n
+ N_OUT_c_40_n OUT N_OUT_c_55_p N_OUT_MM0_d N_OUT_MM3_d
N_OUT_MM2_d
+ PM_06319PRO7_8%OUT
x_PM_06319PRO7_8%NET14 N_NET14_MM1_d N_NET14_MM0_s N_NET14_c_68_n
+ PM_06319PRO7_8%NET14
x_PM_06319PRO7_8%A N_A_c_81_n N_A_MM2_g N_A_MM0_g A
PM_06319PRO7_8%A
x_PM_06319PRO7_8%B N_B_MM1_g B N_B_c_102_n N_B_MM3_g
PM_06319PRO7_8%B
cc_1 N_VDD_c_1_p N_GND_c_20_n 0.00414563f
cc_2 N_VDD_c_2_p N_GND_c_20_n 5.26201e-19
cc_3 N_VDD_c_2_p N_GND_c_22_n 8.72394e-19
cc_4 N_VDD_c_4_p N_GND_c_22_n 5.30151e-19
cc_5 N_VDD_c_4_p N_OUT_c_38_n 0.00123627f
cc_6 N_VDD_c_6_p N_OUT_c_38_n 0.00187535f
cc_7 N_VDD_c_4_p N_OUT_c_40_n 0.0271501f
cc_8 N_VDD_c_6_p N_OUT_c_40_n 0.00574835f
cc_9 N_VDD_c_9_p N_OUT_c_40_n 0.0271501f
cc_10 N_VDD_c_6_p OUT 0.00210897f
cc_11 N_VDD_c_9_p OUT 0.00448928f
cc_12 N_VDD_c_12_p OUT 0.00343695f
cc_13 N_VDD_c_13_p OUT 0.010475f
cc_14 N_VDD_c_4_p N_A_MM2_g 0.025849f
cc_15 N_VDD_c_15_p N_A_MM2_g 0.0382172f
cc_16 N_VDD_c_6_p N_A_MM2_g 0.00757613f
cc_17 N_VDD_c_6_p N_B_MM3_g 0.00746294f
cc_18 N_VDD_c_9_p N_B_MM3_g 0.025849f
cc_19 N_VDD_MM3_s N_B_MM3_g 0.0382172f
cc_20 N_GND_c_20_n N_OUT_c_47_n 0.0239526f
cc_21 N_GND_c_22_n N_OUT_c_47_n 0.00565974f
cc_22 N_GND_c_22_n N_OUT_c_49_n 0.0020246f
cc_23 N_GND_c_22_n OUT 0.00169095f
cc_24 N_GND_c_28_p OUT 0.00448925f
cc_25 N_GND_c_29_p OUT 0.00343695f
cc_26 N_GND_c_30_p OUT 0.010475f
cc_27 N_GND_c_22_n N_NET14_c_68_n 0.00555677f
cc_28 N_GND_c_28_p N_NET14_c_68_n 0.0355706f
cc_29 N_GND_c_20_n N_A_MM0_g 0.00412609f
cc_30 N_GND_c_22_n N_A_MM0_g 0.00391027f
cc_31 N_GND_c_22_n N_B_MM1_g 0.00397792f
cc_32 N_GND_c_28_p N_B_MM1_g 0.0225815f
cc_33 N_GND_MM1_s N_B_MM1_g 0.0382172f
cc_34 N_OUT_c_47_n N_NET14_c_68_n 0.0355706f
cc_35 N_OUT_c_55_p N_NET14_c_68_n 0.00793608f
cc_36 N_OUT_c_38_n N_A_c_81_n 0.00219171f
cc_37 N_OUT_c_40_n N_A_c_81_n 0.0167093f
cc_38 N_OUT_MM3_d N_A_MM2_g 0.0382172f
cc_39 N_OUT_c_47_n N_A_MM0_g 0.024573f
cc_40 N_OUT_c_60_p N_A_MM0_g 0.0382172f
cc_41 N_OUT_c_49_n N_A_MM0_g 0.00824367f
cc_42 N_OUT_c_55_p N_A_MM0_g 0.0167093f
cc_43 N_OUT_c_40_n N_B_MM1_g 0.0278251f
cc_44 OUT N_B_MM1_g 0.0115107f
cc_45 N_OUT_c_55_p N_B_MM1_g 0.00487497f
cc_46 OUT N_B_c_102_n 0.00287578f
cc_47 N_OUT_MM3_d N_B_MM3_g 0.0382172f
cc_48 N_NET14_MM1_d N_A_MM0_g 0.0382172f
cc_49 N_NET14_c_68_n N_A_MM0_g 0.0160343f
cc_50 N_NET14_MM1_d N_B_MM1_g 0.0382172f
cc_51 N_NET14_c_68_n N_B_MM1_g 0.0160343f
cc_52 N_A_MM0_g N_B_MM1_g 0.0120028f
cc_53 N_A_c_81_n N_B_c_102_n 0.0120028f
cc_54 N_A_MM2_g N_B_MM3_g 0.0120028f
7.9 Assume that the 2-input NAND gate in Problem 7.8 is driving a 0.01 pF load. Use hand
calculations to estimate tPLH and tPHL. Do not forget to add in the parasitic capacitances extracted
from your layout! Check your answer with SPICE. Use:

kn' = 98.2 A/V2

kp' = 46.0 A/V2
VTn = 0.53 V
VTp = -0.51 V
EC,nLn = 0.4V
EC,pLp = 1.8V

SOLUTION :
1. The delay can be calculated using an equivalent inverter of 2-input NAND gate. From
equations (6.22b) and (6.23b), we can obtain,


Cload  1  4 VDD  VT ,n   2   VDD  VT ,n VDD  VT ,n   EC L  
 PHL  ln   1   ln  2   
kn  VDD  VT ,n   VDD  EC L
 
 2 V  V  
  
2

   DD T , n  VDD VT ,n

0.011012  1  4(1.2  0.53)  2   1.2  0.53 (1.2  0.53)  0.4 

 6  ln   1  ln  2   
98.2 10  (5 /1)  (1.2  0.53)  1.2  0.4   2(1.2  0.53)  (1.2  0.53) 2 
 145.41ps

 PLH 

Cload  1 

 4 VDD  VT , p 

1 

2   VDD 
 VT , p VDD  VT , p  EC L

 
ln ln 2  

k p VDD  VT , p 
 
VDD  EC L  
  
2 VDD  VT , p   
 VDD  VT , p 
2


0.011012  1  4 1.2  0.51  2   1.2  0.511.2  0.51  1.8  
  ln   1  ln  2   
6
46.0 10  (10 /1) 1.2  0.51  1.2  1.8   2 1.2  0.51  1.2  0.51
2


 75.65ps

2. SPICE simulation netlist and results.

** Problem 7.9 : 2-input NAND gate delay measurement **

** Vriables **
.param supply=1.0
.temp=50

** Options **
.option post accurate nomod brief
*.option scale=60n

** Source **
VDD VDD gnd supply
VA A GND DC PULSE(0V 1V 0.1NS 0NS 0NS 0.5NS 1NS)
VB B GND DC PULSE(0V 1V 0.1NS 0NS 0NS 0.5NS 1NS)

** Netlist(including parasitic extraction result) **

.global vdd gnd

.subckt PM_06319PRO7_8%VDD 3 5 7 10 12 14 17 19 21 25 28 45
c19 30 0 0.00437298f
c20 29 0 0.00437298f
c21 25 0 0.0417278f
c22 21 0 0.0348879f
c23 19 0 0.0601717f
c24 17 0 0.00703762f
c25 14 0 0.0315598f
c26 12 0 0.0601717f
c27 10 0 0.00823824f
c28 7 0 0.0210509f
c29 5 0 0.120343f
c30 3 0 0.044639f
c31 2 0 0.0154647f
r32 23 25 0.39619
r33 22 30 0.0529971
r34 21 23 0.0983284
r35 21 22 0.386667
r36 17 19 8.66667
r37 16 30 0.0314258
r38 16 17 0.924444
r39 15 29 0.0529971
r40 14 30 0.0529971
r41 14 15 0.733333
r42 12 45 4.06829
r43 10 12 8.66667
r44 9 29 0.0314258
r45 9 10 0.924444
r46 8 28 0.0549107
r47 7 29 0.0529971
r48 7 8 0.386667
r49 25 5 8.66667
r50 3 5 8.66667
r51 2 28 0.0434177
r52 2 3 0.39619
.ends

.subckt PM_06319PRO7_8%GND 3 5 7 10 12 14 18 21
c18 22 0 0.00437298f
c19 18 0 0.0417278f
c20 14 0 0.0348488f
c21 12 0 0.0601886f
c22 10 0 0.00751075f
c23 7 0 0.0509513f
c24 5 0 0.120343f
c25 3 0 0.0467866f
c26 2 0 0.0154257f
r27 16 18 0.39619
r28 15 22 0.0529971
r29 14 16 0.0983284
r30 14 15 0.386667
r31 10 12 8.66667
r32 9 22 0.0314258
r33 9 10 0.924444
r34 8 21 0.0581944
r35 7 22 0.0529971
r36 7 8 1.08
r37 18 5 8.66667
r38 3 5 8.66667
r39 2 21 0.0401341
r40 2 3 0.39619
.ends

.subckt PM_06319PRO7_8%OUT 2 4 6 7 9 15 17 22 24 25
c30 24 0 0.0601717f
c31 17 0 0.00322683f
c32 15 0 0.0414075f
c33 9 0 0.00538588f
c34 7 0 0.00580636f
c35 6 0 0.00501621f
c36 4 0 0.0601886f
c37 2 0 0.00737792f
r38 17 19 0.24
r39 13 19 0.04
r40 13 15 1.36
r41 24 11 2.69678
r42 25 11 2.69678
r43 9 11 8.66667
r44 8 19 0.08
r45 8 9 1.05778
r46 6 17 0.04
r47 6 7 0.302222
r48 4 22 4.24411
r49 2 4 8.66667
r50 1 7 0.0893966
r51 1 2 0.817778
.ends

.subckt PM_06319PRO7_8%NET14 6 7 8
c8 8 0 0.00207785f
c9 6 0 0.0601717f
r10 7 8 2.81333
r11 6 8 2.81333
.ends

.subckt PM_06319PRO7_8%A 15 16 20 24
c17 20 0 0.0319113f
c18 16 0 0.0121695f
c19 15 0 0.00527354f
r20 20 24 171.35
r21 19 24 37.25
r22 15 19 11.1725
r23 15 16 47.1833
.ends

.subckt PM_06319PRO7_8%B 16 20 21 22
c16 22 0 0.0121695f
c17 21 0 0.00495424f
c18 16 0 0.0345129f
r19 21 22 47.1833
r20 16 20 119.2
r21 21 15 11.1725
r22 15 20 89.4
.ends

.subckt Pro7_8 GND OUT A B

MM0 N_OUT_MM0_d N_A_MM0_g N_NET14_MM0_s N_GND_MM0_b nmos L=6e-08
W=6e-07
MM1 N_NET14_MM1_d N_B_MM1_g N_GND_MM1_s N_GND_MM0_b nmos L=6e-08
W=6e-07
MM2 N_OUT_MM2_d N_A_MM2_g N_VDD_MM2_s N_VDD_MM2_b pmos L=1.2e-07
W=6e-07
MM3 N_OUT_MM3_d N_B_MM3_g N_VDD_MM3_s N_VDD_MM2_b pmos L=1.2e-07
W=6e-07

C0 OUT GND 0.01pF

x_PM_06319PRO7_8%VDD N_VDD_c_1_p N_VDD_MM2_b N_VDD_c_2_p

+ N_VDD_c_4_p N_VDD_c_15_p N_VDD_c_6_p N_VDD_c_9_p
+ N_VDD_MM3_s N_VDD_c_12_p N_VDD_c_13_p VDD N_VDD_MM2_s
+ PM_06319PRO7_8%VDD
x_PM_06319PRO7_8%GND N_GND_c_20_n N_GND_MM0_b N_GND_c_22_n
+ N_GND_c_28_p N_GND_MM1_s N_GND_c_29_p N_GND_c_30_p GND
+ PM_06319PRO7_8%GND
x_PM_06319PRO7_8%OUT N_OUT_c_47_n N_OUT_c_60_p N_OUT_c_49_n
N_OUT_c_38_n
+ N_OUT_c_40_n OUT N_OUT_c_55_p N_OUT_MM0_d N_OUT_MM3_d
N_OUT_MM2_d
+ PM_06319PRO7_8%OUT
x_PM_06319PRO7_8%NET14 N_NET14_MM1_d N_NET14_MM0_s N_NET14_c_68_n
+ PM_06319PRO7_8%NET14
x_PM_06319PRO7_8%A N_A_c_81_n N_A_MM2_g N_A_MM0_g A
PM_06319PRO7_8%A
x_PM_06319PRO7_8%B N_B_MM1_g B N_B_c_102_n N_B_MM3_g
PM_06319PRO7_8%B
cc_1 N_VDD_c_1_p N_GND_c_20_n 0.00414563f
cc_2 N_VDD_c_2_p N_GND_c_20_n 5.26201e-19
cc_3 N_VDD_c_2_p N_GND_c_22_n 8.72394e-19
cc_4 N_VDD_c_4_p N_GND_c_22_n 5.30151e-19
cc_5 N_VDD_c_4_p N_OUT_c_38_n 0.00123627f
cc_6 N_VDD_c_6_p N_OUT_c_38_n 0.00187535f
cc_7 N_VDD_c_4_p N_OUT_c_40_n 0.0271501f
cc_8 N_VDD_c_6_p N_OUT_c_40_n 0.00574835f
cc_9 N_VDD_c_9_p N_OUT_c_40_n 0.0271501f
cc_10 N_VDD_c_6_p OUT 0.00210897f
cc_11 N_VDD_c_9_p OUT 0.00448928f
cc_12 N_VDD_c_12_p OUT 0.00343695f
cc_13 N_VDD_c_13_p OUT 0.010475f
cc_14 N_VDD_c_4_p N_A_MM2_g 0.025849f
cc_15 N_VDD_c_15_p N_A_MM2_g 0.0382172f
cc_16 N_VDD_c_6_p N_A_MM2_g 0.00757613f
cc_17 N_VDD_c_6_p N_B_MM3_g 0.00746294f
cc_18 N_VDD_c_9_p N_B_MM3_g 0.025849f
cc_19 N_VDD_MM3_s N_B_MM3_g 0.0382172f
cc_20 N_GND_c_20_n N_OUT_c_47_n 0.0239526f
cc_21 N_GND_c_22_n N_OUT_c_47_n 0.00565974f
cc_22 N_GND_c_22_n N_OUT_c_49_n 0.0020246f
cc_23 N_GND_c_22_n OUT 0.00169095f
cc_24 N_GND_c_28_p OUT 0.00448925f
cc_25 N_GND_c_29_p OUT 0.00343695f
cc_26 N_GND_c_30_p OUT 0.010475f
cc_27 N_GND_c_22_n N_NET14_c_68_n 0.00555677f
cc_28 N_GND_c_28_p N_NET14_c_68_n 0.0355706f
cc_29 N_GND_c_20_n N_A_MM0_g 0.00412609f
cc_30 N_GND_c_22_n N_A_MM0_g 0.00391027f
cc_31 N_GND_c_22_n N_B_MM1_g 0.00397792f
cc_32 N_GND_c_28_p N_B_MM1_g 0.0225815f
cc_33 N_GND_MM1_s N_B_MM1_g 0.0382172f
cc_34 N_OUT_c_47_n N_NET14_c_68_n 0.0355706f
cc_35 N_OUT_c_55_p N_NET14_c_68_n 0.00793608f
cc_36 N_OUT_c_38_n N_A_c_81_n 0.00219171f
cc_37 N_OUT_c_40_n N_A_c_81_n 0.0167093f
cc_38 N_OUT_MM3_d N_A_MM2_g 0.0382172f
cc_39 N_OUT_c_47_n N_A_MM0_g 0.024573f
cc_40 N_OUT_c_60_p N_A_MM0_g 0.0382172f
cc_41 N_OUT_c_49_n N_A_MM0_g 0.00824367f
cc_42 N_OUT_c_55_p N_A_MM0_g 0.0167093f
cc_43 N_OUT_c_40_n N_B_MM1_g 0.0278251f
cc_44 OUT N_B_MM1_g 0.0115107f
cc_45 N_OUT_c_55_p N_B_MM1_g 0.00487497f
cc_46 OUT N_B_c_102_n 0.00287578f
cc_47 N_OUT_MM3_d N_B_MM3_g 0.0382172f
cc_48 N_NET14_MM1_d N_A_MM0_g 0.0382172f
cc_49 N_NET14_c_68_n N_A_MM0_g 0.0160343f
cc_50 N_NET14_MM1_d N_B_MM1_g 0.0382172f
cc_51 N_NET14_c_68_n N_B_MM1_g 0.0160343f
cc_52 N_A_MM0_g N_B_MM1_g 0.0120028f
cc_53 N_A_c_81_n N_B_c_102_n 0.0120028f
cc_54 N_A_MM2_g N_B_MM3_g 0.0120028f

xPro7_8 GND OUT A B Pro7_8

** Analysis **
.tran 1ps 5ns

.model nmos NMOS(VTO=0.48 KP=168E-6)

.model pmos PMOS(VT0=-0.42 KP=60.3E-6)
.print tran V(a) V(out)

.end

The simulation result is shown in the plot.

1.2

1.0

0.8

0.6
V

0.4

0.2

0
0 0.2 0.4 0.6 0.8 1
Time(ns)
The delays are found out from the output which is very close to hand calculation.

 PLH  654.24 1012  601.5 1012  52.74ps

 PHL  154.56 1012  100.5 1012  54.06ps
7.10 Consider the logic circuit shown in Fig. P7.10, with μnCox = 98.2 μA/V2, μpCox = 46.0 μA/V2,
VT0,n = 0.53 V, VT0,p = –0.51 V, EC,nLn = 0.4V, and EC,pLp = 1.7V, and  = 0. The power supply
voltage is VDD = 1.2V.

(a) Determine the logic function F.

(sol) F  A (B  C)  D

(b) Calculate WL/LL such that VOL does not exceed 80mV.

(sol) First, find the worst case inputs. (A=1, B=1 or C=1, D=0)
Using (eq.7.27) we can find effective (W/L) of driver,
1
W   1 1   1 1 
1
2
         
 L effective  W / L  A W / L  B or C 
 8/ 4 4/ 4 3
And VOL have to satisfy below condition (eq.7.4),

 
2
k  EC , p  Lp  VDD  VT 0, p
V  VT 0,n 
2
VOH  VT 0,n    load   80mV
OH
 kdriver  
 VDD  VT 0, p  EC , p  Lp
where  kload / kdriver   WL / LL  / W / L effective .
Then, WL / LL  can be express as,

 
 
 W / L effective 
 WL    V  V 2   80 mV  V  V 2 
 
 
    OH 
2 T 0, n OH T 0, n
 LL  E  L  V  V
 C , p p DD T 0, p 

 V V
 DD 
T 0, p  EC , p  L p


 0.2
Therefore, WL / LL   0.2
(c) Qualitatively, would WL/LL increase or decrease if the same conditions in (b)
are to be achieved but  = 0.524 V1/2?

(sol) Threshold voltage of depletion nMOS is changed due to the body effect. So, drain
current of load is reduced. Then VOL will be increased. In order to make its drain
current larger, WL/LL should be increased.

Figure P7.10

7.11 Consider the circuit shown in Fig. P7.11.

(a) Determine the logic function F.

 (b) Design a circuit to implement the same logic function, but using NOR gates.

Draw a transistor-level schematic and use pseudo nMOS technology.

(c) Design a circuit to implement the same logic function, but use an

AOI (AND-OR-INVERT) gate. Draw a transistor-level schematic and use

CMOS technology.

Figure P7.11

SOLUTION :

(a) F  AB  AB  A  B
(b) Using NOR gates,

AB  AB  ( A  B)( A  B)  ( A  B)  ( A  B)
 VDD

VDD
A B

F
VDD

A B

(c) Using AOI gates,

F  AB  AB
F  F  AB  AB

7.12 The enhancement-type MOS transistors have the following parameters:

VDD = 1.2 V
 VT0,n = 0.53 V
VT0,p = -0.51 V
 = 0.0 V-1
pCox = 46.0 A/V2
nCox = 98.2 A/V2
EC,nLn = 0.4V
EC,pLp = 1.7V

For a CMOS complex gate OAI432 with (W/L)p = 30 and (W/L)n = 40,

(a) Calculate the W/L sizes of an equivalent inverter with the weakest
pull-down and pull-up. Such an inverter can be used to calculate worst-case pull-up and
pull-down delays, with proper incorporation of parasitic capacitances at internal nodes into
the total load capacitance. In this problem, you are asked to calculate only (W/L)worse-case
for both p-channel and n-channel MOSFETs by neglecting the parasitic capacitances.

SOLUTION :
The OAI432 circuit is drawn along with an Euler path in the following figure.

1. The weakest pull-up case : Only A-B-C-D(pMOS) branch is turned on.

W  1 W  30
       7.5
 L eq , p 4  L  p 4

2. The weakest pull-down case : Only one nMOS transistor is turned on each cascode
level.
W  1W  40
       13.3
 L eq ,n 3  L n 3

(b) Do the layout of OAI432 with minimal diffusion breaks to reduce the number of polysilicon
column pitches. With proper ordering of polysilicon gate columns, the number of diffusion
breaks can be minimized. One way of achieving such a goal is to find a Euler path
 common to both p-channel and n-channel nets using graph models. Symbolic layout that
shows source and drain connections is sufficient to answer this problem.

SOLUTION :

7.13 Consider a fully complementary CMOS transmission gate with its input terminal tied to
ground (0 V) while the other non-gate terminal is tied to a 1 pF load capacitor initially
charged to 1.2 V. Use the values in Problem 7.12. At t = 0, both transistors are fully turned
on by clock signals to start the discharge of the capacitor.

(a) Plot the effective resistance of this transmission gate as a function of capacitor voltage
when (W/L)p = 50 and (W/L)n = 40. From the plot find the average value of the resistance.
Then calculate the RC delay for the capacitor voltage to change from 1.2 V to 0.6 V. This
can be found by solving the RC-circuit differential equation.

SOLUTION :
There are three operating regions of the transmission gate.

a. Region 1

When 0 < Vout < |Vt0,p|, pMOS is turned off and nMOS is in the linear region.

 Vout 
2Vout  1  
 Ec ,n  Ln 
Req ,n 
  
kn   2 VDD  VT 0,n Vout  Vout 2 

 Vout 
2  1  
 Ec ,n  Ln 

kn   2 VDD  VT 0,n   Vout 
Req , p   (Cut off)

b. Region 2
 When |Vt0,p| < Vout < VDD-VT0,n, nMOS is in the linear region and pMOS is in the
saturation region.

 Vout 
2  1  
 Ec ,n  Ln 
Req ,n 
kn   2 VDD  VT 0,n   Vout 

Req , p    
2Vout   Vout  VT 0, p  Ec , p  Lp 

 
2
k p  Ec , p  Lp  Vout  VT , p

c. Region 3

When Vout > VDD-VT0,n, nMOS and PMOS are in the saturation region.

2Vout  VDD  VT 0,n   Ec ,n  Ln 

Req ,n 
kn  Ec ,n  Ln  VDD  VT 0,n 
2

Req , p    
2Vout   Vout  VT 0, p  Ec , p  Lp 

 
2
k p  Ec , p  Lp  Vout  VT , p

Using above equations, equivalent resistance of CMOS transmission gate is shown in the
plot.

And average value of the effective resistance is 1.38k

 d. Calculate the RC delay.

Differential equation :
 dV 
Vout  Req  i  Req   C out 
 dt 
1 1
dt  dVout
Req C Vout
t
 ln Vout    ln AVout
ReqC
 t 
exp   AVout
 R C 
 eq 
When t=0, Vout is equal to VDD(=1.2V).
 t   t 
Vout  V0 exp    1.2exp 
R C  R C 
 eq   eq 
If we set Vout = 0.6, than we can find the answer.
t   ReqC ln 0.5  ReqC ln 2  0.95ns

(b) Verify your answer to part (a) by using SPICE simulation. The source/drain parasitic
capacitances can be neglected.

SPICE input list

SPICE simulation result

The delay time is 810ps
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