IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO.

5, MAY 2022 4687

MIMO Control of a High-Step-Up Isolated

Bidirectional DC–DC Converter
Yuchen Zhang , Student Member, IEEE, Giorgio Spiazzi , Member, IEEE,
Simone Buso , Member, IEEE, and Tommaso Caldognetto , Member, IEEE

Abstract—This article proposes a multi-input multi-

output digital control strategy for a bidirectional interleaved
boost converter with coupled inductors, designed to oper-
ate as an interface between an ultracapacitor and a high-
voltage dc-bus in a hybrid nanogrid. The control strategy
keeps the high-voltage side dc-bus of the nanogrid stable
when the voltage at the low-voltage side, connected to
the ultracapacitor, changes in a wide range. Bidirectional
energy flow control with current protection is allowed too.
The high-voltage regulation loop is closed around an inner,
low-voltage side current control loop. In parallel to these,
a third, clamp voltage regulator is set to keep tight con-
trol over switch voltage stress. This article discusses the Fig. 1. Application of bidirectional dc–dc converters in a hybrid
controller organization, the design criteria, and shows the nanogrid to bridge different dc-buses.
subsequent implementation on a general purpose digital
control platform. The achievable performance is experimen-
tally verified on a 1.5-kW converter prototype.
The BIBCI topology has numerous merits, including con-
Index Terms—Digital control, high-step-up isolated dc–
dc converter, multi-input multi-output (MIMO) control.
tinuous low-voltage side current with reduced ripple at twice
the switching frequency, flexible step-up ratio, galvanic isola-
tion, and zero-voltage-switching (ZVS) capability for all the
I. INTRODUCTION switches [1]–[6], which ensures high efficiency in a wide power
IGH-STEP-UP dc–dc converters with bidirectional power range. On the other hand, being somewhat more complex than
H flow capability are nowadays extremely important for
electrical energy storage applications. These topologies are the
the DAB, the BIBCI topology presents slightly higher cost,
higher current stress at the primary side, and higher order
only option to interconnect dc-buses at significantly different dynamics [7].
voltage levels (e.g., a low-voltage 48-V device with a high- Starting from a unidirectional version of the BIBCI, intro-
voltage 400-V dc-bus) as is the case in a typical nanogrid, as duced and analyzed in [8] and [9], considerable research efforts
shown in Fig. 1. While the most frequently adopted solution have been devoted to the definition of optimal design criteria
is represented by the dual active bridge (DAB) topology, the and the characterization of the static converter performance,
bidirectional interleaved boost with coupled inductors (BIBCIs), especially in terms of efficiency. As far as converter control
whose basic scheme is shown in Fig. 2(a), has been recently is concerned, several papers addressed the modulation strategy,
proposed as an effective alternative [1], [2]. proposing different techniques. In a recent survey paper [10],
the class of L–L type current-fed-isolated-bidirectional dc–dc
Manuscript received December 3, 2020; revised March 9, 2021 and converters, which includes the BIBCI topology, has been identi-
April 9, 2021; accepted April 19, 2021. Date of publication May 13, 2021; fied. On the basis of the literature analysis reported therein (see,
date of current version January 7, 2022. The work of Y. Zhang was sup- e.g., [11]–[15]), the typical modulation strategy for this class
ported by the Chinese Scholarship Council under Grant 201906290155.
(Corresponding author: Yuchen Zhang.) of converters aims at minimizing the circulating current of the
Yuchen Zhang is with the School of Automation, Northwestern Poly- transformer [16]–[18] and expanding the soft switching region,
technical University, Xi’an 710072, China, and also with the Department especially at light load [19]–[22], by exploiting the multiple
of Information Engineering, University of Padova, 35122 Padova, Italy
(e-mail: zhangyuchen@dei.unipd.it). degrees of freedom of the topology. A few different modula-
Giorgio Spiazzi and Simone Buso are with the Department of Infor- tion techniques have been more clearly defined and repeatedly
mation Engineering, University of Padova, 35122 Padova, Italy (e-mail: used, namely, the single phase shift [23], the plus phase shift
spiazzi@dei.unipd.it; simone.buso@dei.unipd.it).
Tommaso Caldognetto is with the Department of Management (PPS) [21], [24], the dual phase shift [25], and the triple phase
and Engineering, University of Padova, 36100 Vicenza, Italy (e-mail: shift [26], which often rely on converter loss models [27], [28].
tommaso.caldognetto@unipd.it). Due to the relatively high computational burden implied, the
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIE.2021.3078393. development of external, high speed, digital controllers is often
Digital Object Identifier 10.1109/TIE.2021.3078393 made more difficult than with more conventional modulators.
0278-0046 © 2021 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 4688 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 5, MAY 2022

(a) (b)

Fig. 2. BIBCIs. (a) Basic topology. (b) Equivalent circuit for energy transfer analysis.

For this reason, in [3], just a slow current controller is imple- keeping the latter a pure square wave. Three different operating
mented, with limited dynamic performance capabilities. Overall, regions can be defined, depending on the relation between D
while promising results have been presented for steady-state and ϕ, namely
operation, large-bandwidth closed-loop regulation has not been
R1 :0 < ϕ < π |D − 1/2|
documented yet.
This article moves a step forward in this direction presenting R2 :π |D − 1/2| < ϕ < π (1 − |D − 1/2|)
the design methodology and the implementation of a novel,
R3 :π (1 − |D − 1/2|) < ϕ < π (1)
high performance, multi-input, multi-output (MIMO) digital
controller for the BIBCI converter. In the proposed solution, where R1 , R2 , and R3 indicate region 1, region 2, and region 3,
on top of a PPS modulator, a multiloop controller is designed to respectively. It is important to notice, however, that the boundary
automatically adjust the modulator inputs and achieve state vari- between R2 and R3 is ≥ π/2 ∀ D ∈ [0, 1]. Therefore, limiting
ables’ regulation. Differently from open-loop or low-bandwidth the applicable phase shift in the range [−π/2, +π/2], R3 is
solutions, the proposed controller guarantees a satisfactory dy- actually never entered. From now on, electrical variables will
namic performance and inherent circuit protection in the con- be expressed in normalized form according to the following
sidered target application. After a brief recapitulation of the notation and base quantities:
converter principle of operation in Section II and a summary Instantaneous quantities : v X , iX
of the applied circuit design procedure in Section III, the pro- Average quantities in TN : v̄X , īX
posed digital controller organization is presented in Section IV. Switching frequency: fsw
Modeling, design, and implementation details are given in this Base time interval: TN = 1/fsw
section. The outcomes of the controller dynamic performance Base voltage: VN = VB = VH
tests are presented in Section V. Finally, Section VI concludes Base impedance: XL = 2πfsw L
this article. Base current: IN = VN /XL
Base power: PN = VN2 /XL
II. BIBCI PRINCIPLE OF OPERATION Normalized current : jX = iX /IN
Normalized voltage : νX = vX /VN
Although the two topologies present visible differences, the Normalized power : ΠX = PX /PN
energy transfer mechanism of the BIBCI is by all means identical
to that of the DAB [29]. Indeed, the converter operation is The relevant equations for the converter’s dynamic model
such that the power transferred from one side to the opposite derivation are recalled in the following. The complete converter
depends on the voltage applied to an energy transfer inductor analysis can be found in [1] and [2].
L, as shown in Fig. 2(b). Notably, inductor L results from the
series connection of the secondary side leakage inductances of A. Clamp Capacitor Voltage
the two coupled inductors. Voltage sources vA and vB result Applying volt-second balance across each coupled inductor
from the two full bridge circuits, with a remarkable property: magnetizing inductance and neglecting the ripple on the clamp
the amplitude VA of the three-level voltage vA is not constant capacitor voltage, the amplitude VA of the three-level voltage
(as it would be in a DAB), but, rather, is proportional to the clamp vA is simply related to the low-voltage side dc voltage VL as
capacitor voltage vCL and, as such, depends on the duty cycle
VCL VL νL
D of the interleaved boost-type cells that form the low-voltage VA = = ⇒ νA = (2)
n n(1 − D) n(1 − D)
bridge.
n
This feature is usually exploited to compensate for the input where n = nps is the turns ratio of each coupled inductor. No-
voltage variations and keep the amplitudes VA and VB of the tably, in the steady state, VA does not depend on ϕ. The definition
two voltages vA and vB balanced, implementing the PPS mod- of VB , the square wave amplitude, is much simpler, as that is
ulation. The power flow between input and output ports can be equal to VH . Of course, according to the normalization factors,
regulated by adjusting the phase shift ϕ between vA and vB while νB = 1.

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 ZHANG et al.: MIMO CONTROL OF A HIGH-STEP-UP ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4689

Fig. 4. Control characteristics of the BIBCI converter.

TABLE I
CONVERTER SPECIFICATIONS

Fig. 3. Modulation characteristics. (a) Normalized output power Π

versus phase shift ϕ and boost duty cycle D. (b) Constant power curves.

B. Power Transfer Equation

The amount of transferred power is determined from the
instantaneous current iL (θ), where θ = 2π TtN , as
 2π
1
P = iL (θ) · vB (θ) dθ. (3)
2π 0
This low-level control strategy is known as PPS modulation.
The integral calculation is simplified by vB (θ) being piecewise Fig. 4 shows the PPS control characteristics of the converter
constant, but the result shows a different dependence from D (i.e., normalized power versus ϕ) for different values of D.
and ϕ in each operation region. After a few calculations [1], the First of all, the good linearity of the dependence of Π from
following normalized expressions can be found: ϕ, at least in the range [−π/4, +π/4], can be appreciated. As
R1 :Π1 = νA ϕ (1 − |2D − 1|) can be easily determined assuming νA = 1, for D in the range
[0.4, 0.6], ΠMAX varies only from 0.754 to 0.785, that is, by less
  ϕ π 
R2 :Π2 = νA ϕ 1 − − (2D − 1)2 than 5%, indicating that, in the steady state, the sensitivity of
π 4 ΠMAX to D is limited.
 ϕ 
R3 :Π3 = νA π 1 − (1 − |2D − 1|) . (4) III. CONVERTER DESIGN CRITERIA
π
Combining the three expressions, according to the boundaries The converter considered in this article has been designed
defined in (1), the plot shown in Fig. 3(a) is obtained. around the main parameters listed in Table I that address the
Using (4), it is also possible to calculate the constant power typical application of the BIBCI as a bridge converter linking
characteristics of the converter, as shown in Fig. 3(b). As can two dc-buses: a low-voltage one, herein assumed connected
be seen, the peak power transfer takes place at ϕ = π/2. As a to an ultracapacitor-type BMOD0130P056B03 from Maxwell,
result, operation in region 3 of (1) is not required and should and a high-voltage one, to be regulated at VH = 400 V. This
be altogether avoided in order to prevent system’s instability. functionality is almost always required in dc or hybrid nanogrids,
Furthermore, using (2), the maximum power flow expression is whenever a low-voltage energy storage device has to be in-
found tegrated in the system. The design procedure for the BIBCI
converter has been presented in detail in past papers [1], [2]
ΠMAX = νA πD (1 − D) (5)
and is pretty much straightforward.
which shows minimum sensitivity at D = 0.5. In conclusion, (2) The design has been validated by testing the controller per-
and the static transfer characteristics analysis suggest to use duty formance in open-loop conditions. Voltage and current stresses
cycle D to control VA so as to achieve VA = VB for D ∼ = 0.5 have been verified to stay within the design boundaries. The
while using ϕ to regulate the power flow. typical converter waveforms are visible in Fig. 5. As can be seen,

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 4690 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 5, MAY 2022

Fig. 7. Nonlinear, average, dynamic model of the BIBCI converter.

(a) (b)

Fig. 5. Measured BIBCI waveforms at VL = 50 V, VH = 400 V, and is therefore nontrivial, because the input inductors Lm and
IDCL = 16 A. (b) Detail of the commutations in (a). the clamp capacitors CCLa,b operate at different, but relatively
close, time scales, whereas the output capacitor CDC presents
significantly slower dynamics.

A. Converter Dynamic Model

For the design of the digital controller, a linear, dynamic model
of the power converter is derived from its average, nonlinear
model shown in Fig. 7. Not surprisingly, the typical structure of
a boost converter model can be recognized in the middle block,
describing the clamp voltage dynamics. The model is given just
for one phase, since the interleaved operation of the two input
boost cells is equivalent, in average terms, to a current doubling
effect, therefore, the average low-voltage side current is just
given by
īDCL = īma + īmb = 2 · īm (6)
Δ
since, for symmetry, īma = īmb = īm . For this reason, the left-
hand side block of the model shows a gain equal to 2 in the
current generator.
Observing the boost switching cell, the following constraint
Fig. 6. BIBCI performance. (a) Region where ZVS is achieved for
all switches with PPS modulation. (b) Measured efficiency for different
for the average current flowing into the clamp capacitor can be
transferred power, at VL = 48 V: power flow from low- to high-voltage set:
sides in blue, from high to low voltage in purple.  
iL
īCL = im − = īm (1 − D) − īr (7)
n
SaH =on
smooth transitions are achieved for both the high-voltage and the
where the bar operator indicates the time average over interval
low-voltage sides. A detailed view of the switch SaL drain to
TN of any variable. While the first term of (7) is easily de-
source voltage (yellow trace) and of the secondary side square
termined, the calculation of īr is a little involved, because the
wave voltage (purple trace) during the commutation is visible
averaging integral
in Fig. 5(b). It is possible to appreciate the well-behaved drain 
to source voltage, which is due to soft-switching taking place 1 iL
īr = (θ) dθ (8)
at both sides of the converter. Conversion efficiency has been 2π SaH =on n
measured as well and is shown in Fig. 6, together with the ZVS
depends on the converter operating region.
operating region. As can be seen, the design achieves ZVS for all
If we now consider the high-voltage side dynamics, the aver-
switches in a wide range of operating points of interest. Notably,
age current īf , feeding the output capacitor and the equivalent
the efficiency is above 95 % in a wide power range and for both
load resistance RLoad , is given by
directions. Such good efficiency figures are maintained also at
higher power levels. In particular, at the nominal transferred P 2īr v̄L 2īr v̄CL
īf = īDCH = = = (9)
power of 1.5 kW, the measured efficiency is 96%. v̄H 1 − D v̄H v̄H
which again depends on īr . Therefore, to get a computable
IV. DIGITAL CONTROLLER ORGANIZATION AND DESIGN model, the explicit expressions of īr , and īf , need to be de-
As mentioned in Section II, the PPS modulation strategy offers termined for the two operating regions of interest. This is im-
2 DOF. On the other hand, even neglecting the energy transfer mediately done considering (4), which yields the results shown
inductor, which does not play a significant role in the converter in Table II.
dynamics, as will be shown in the following, the BIBCI converter As can be seen, in each region, īr is a different nonlinear
presents three reactive components, Lm , CCL , and CDC , whose function of ϕ, D, and v̄H , but, interestingly, does not depend on
state cannot be independently regulated. The control problem state variable vCL . The opposite holds for īf , that, thanks to (9),

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 ZHANG et al.: MIMO CONTROL OF A HIGH-STEP-UP ISOLATED BIDIRECTIONAL DC–DC CONVERTER 4691

TABLE II
EXPRESSIONS OF īr
⎧ V
⎪ H
⎨ 2nXL (1 − |2D − 1|)
⎪ R1
hr =   (14)
⎪
⎪ |Φ|
⎩ VH 1−2 R2
2nXL π

VCL VCL
gf = 2gr , hf = 2 hr , kf = 2 kr (15)
VH VH
where Φ = ϕ|OP . Considering the operating point OP =
[400 V, 100 V, +30 A], gr = 0.018 Ω−1 , gf = 0.035 Ω−1 ,
hr = 7.2 A, hf = 3.8 A, kr = 9.3 A, and kf = 4.9 A.
Based on the aforementioned model and with the specified
parameter values, the system state-space linear model and, by
adopting any suitable MIMO design approach, a system con-
troller can be derived. However, as explained earlier, we have
considered a different approach, where an advantageous struc-
Fig. 8. Linearized, small-signal model of the BIBCI converter. ture is attributed a priori to the controller. By doing so, we are
actually able to achieve a sufficiently decoupled control of state
variables (vCL , iDCL , vH ), even if the converter is actuated just
does not depend on v̄H , but rather on v̄CL . This is the origin of by the two variables (D, ϕ). In particular, the couple (vCL , iDCL )
the intrinsic dynamic coupling among the system state variables, is the most problematic, as the natural modes of the system
which will have to be managed by the controller. corresponding to these state variables have similar magnitude.
At this stage, the model in Fig. 7 is completely determined. Variable vH , instead, is the expression of an intrinsically slow
To be used in controller design, the model needs to be linearized system mode, which suggests that a natural decoupling exists
in a small-signal sense yielding the small-signal, linear circuit from the former couple. Considering the couple (vCL , iDCL ),
shown in Fig. 8. and referring to Fig. 4, the different sensitivity of the power
In order to determine the small-signal gains of the model, flow (i.e., of current iDCL ) to the two control variables (D, ϕ)
the functions īr and īf with the expressions in Table II need is clearly visible. This suggests to use the latter, ϕ, to regulate
to be linearly approximated around a selected operating point the low-voltage side current, because this intrinsically minimizes
OP = [VH , VCL , Im ], which yields the interference coming from D. Of course, duty cycle variations
will still have some impact on the transferred power, as well as
∂ īr ∂ īr ∂ īr the variation of ϕ will have an impact of the clamp voltage. The
ĩr = ϕ̃ · + d˜ · + ṽh ·
∂ϕ OP ∂d OP ∂v̄H OP (10) two control actions, however, can be also actively decoupled
by setting different bandwidths on the respective regulators, as
= ϕ̃ · hr + d˜ · kr + ṽdch · gr explained in the following section.
∂ īf ∂ īf ∂ īf
ĩf = ϕ̃ · + d˜ · + ṽcl ·
∂ϕ OP ∂d OP ∂v̄CL OP (11) B. Design Controller Structure
= ϕ̃ · hf + d˜ · kf + ṽcl · gf . Considered the target application, we chose to make the
high-voltage dc-bus vH a directly controlled state variable,
The calculation of the gain parameters in (10) and (11) is again as, in a dc or hybrid nanogrid, that would be hosting loads
a little involved. The expressions turn out to be the following: requiring a controlled supply voltage. Now, because the steady
⎧ 1 state can be achieved only when the power flowing through the
⎪
⎪ |Φ| (1 − |2D − 1|) R1 converter low-voltage port matches the high-voltage port one, an
⎪
⎨ 2nXL
  inner, closed-loop regulation of the low-voltage dc current iDCL
gr =   2 
⎪
⎪ 1 |Φ| 1 can certainly improve the high-voltage bus regulator dynamic
⎪
⎩ |Φ| 1 − −π D− R2
2nXL π 2 performance. Furthermore, the current controller can be used
to operate the BIBCI as a controlled power source/sink when
(12)
needed (e.g., when the high-voltage bus is regulated by another
converter), in which case the dc voltage loop will have to be
⎧  
⎪
⎪ VH 1 disabled. In addition to the two port loops, we chose to directly
⎪
⎨ nXL |Φ| sign − D R1
2 control the clamp voltage vCL , so as to keep the switch stress
kr =   (13) at the low-voltage side under tight regulation at all times. As a
⎪
⎪ VH 1
⎪
⎩ π −D R2 result, the digital controller proposed herein is organized as in
nXL 2 Fig. 9.

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 4692 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 5, MAY 2022

TABLE III
COMPARATIVE ANALYSIS OF CONTROL STRATEGIES

Fig. 9. Block diagram of the adopted digital control architecture. thanks to the aforementioned spectral decoupling, control signal
ϕ̃ will be null over the time span where the PI regulator for vCL
is not in steady state. It yields
As can be seen, three proportional-integral (PI) regulators 1 + b11 s + b21 s2
have been arranged in two parallel loops: the clamp voltage loop Gvcl d (s) = GV D0 · (16)
1 + a11 s + a21 s2 + a31 s3
and the high dc voltage loop. The latter is actually a multiloop
regulator itself, where the inner current controller is driven by the with
 
outer voltage controller. Based on the discussion in Section II, VCL gr gf Lm + Rd CCL
GV D0 = , a11 = RH CDC
the clamp voltage loop indirectly drives the D input of the 1−D (1 − D)2
modulator, whereas the dc-bus loop drives the ϕ input. Overall,
Lm CCL + RH Rd CCL CDC RH CDC Lm CCL
the controller presents three input and two output signals. The a21 = 2
, a31 =
two control action effects, however, can be actively decoupled (1 − D) (1 − D)2
by setting different bandwidths on the respective regulators, (kr + Im )Lm + gr kf RH Lm + RH CDC Rd
based on the converter’s dynamic model. Specifically, the clamp b11 = RH CDC −
VCL (1 − D)
voltage (vCL ) loop, controlled by duty cycle D, is made the
fastest loop, with the largest bandwidth. In order to design its PI (kr + Im )Lm RH CDC
b21 = − .
regulator, we just need to compute the transfer function between VCL (1 − D)
D and vCL . The input current iDCL loop is designed around the (17)
transfer function between ϕ and iDCL , so as to get a much lower Based on (16), it is possible to design a PI controller to get
bandwidth than the vCL loop. By doing so, the effects of the predefined crossover frequency and phase margin. In our case,
PI regulator of iDCL over vCL will be strongly attenuated, as its that was set to 1.5 kHz with a 70° phase margin.
much faster control loop prevails over the current loop. On the Once the loop around vCL is closed, the dynamics of the
contrary, the current loop will appear to be open to the (vCL ) loop, system within the loop bandwidth simplify. Indeed, if we limit
but this will not have a significant impact on current regulation the bandwidth of the iDCL regulator at around 250 Hz, vCL will
due to its lower sensitivity to D. In summary, the decoupling appear to be practically constant, as its much faster control loop
between the state variables vCL and iDCL is enforced in the will be able to keep it on its set-point no matter what the current
frequency domain, limiting the regulation bandwidth of the latter loop does. Under this assumption, the current dynamics can be
well below the former’s. Finally, voltage vH can be regulated by derived from the model in Fig. 7, where current iCL is set to zero.
the loop with the smallest bandwidth, this matching the physical In this case, (7) reduces to
system natural modes. īm (1 − D) − īr = 0. (18)
With respect to the only previously described closed-loop
controller for the BIBCI topology, namely, the one discussed After small-signal linearization, a simple first-order dynamic
in [3], the solution proposed herein allows a much higher per- model is found and the following transfer function is derived:
formance level. In particular, the proposed MIMO organization 1 + b12 s
GIm ϕ (s) = GIΦ0 · (19)
allows to: tightly regulate the most critical system state variables; 1 + a12 s
minimize undesired transients on the low-voltage side current; where the coefficients are
and implement rapid reversal of the ultracapacitor power flow,
with minimum impact on the energy source and the loads. On GIΦ0 = gr hf RH + hr , a12 = RH CDC
the other hand, it also presents a few disadvantages, mainly hr RH CDC (20)
due to the described more complex design of the controller. A b12 = .
GIΦ0
comparison among the two solutions is summarized in Table III.
The Bode diagrams of the aforementioned transfer functions,
in different regions, are shown in Fig. 10. Herein, duty cycle is fix
C. Regulator Design Criteria at 0.52, and ϕ is variable from 0 to 0.5π. When ϕ/π = 0.02, the
In order to design the PI regulator for state variable vCL , the black dashed curve is the boundary between R1 and R2 , which
transfer functions between d˜and ṽcl , namely Gvcl d , can be used. verifies the reliable continuity of the transfer function between
The model in Fig. 8 can be exploited to this end, assuming that, the two regions. The red curve refers to the nominal operating

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 ZHANG et al.: MIMO CONTROL OF A HIGH-STEP-UP ISOLATED BIDIRECTIONAL DC–DC CONVERTER
Fig. 10. Bode diagram in different region. (a) and (b) Magnitude and phase of Gvcl d . (c) and (d) Magnitude and phase of GIm ϕ . Here, D = 0.52,
the black dashed curve is the boundary between region 1 and region 2 (i.e., ϕ/π = 0.02), and the red curve is at operating point.
(a) (b)
Fig. 11. Bode diagram of transfer functions Gvcl d in (a) and GIm ϕ in
(b). Solid lines: analytical results; circles: experimental measurements.
point, which is further experimentally verified in the following
(see Fig. 11).
Finally, the PI controller for vH has to be designed. This is
a relatively simple task because, thanks to the closed loops for
vCL and iDCL , the converter behaves like a controlled current
source feeding the high-voltage dc-bus. As a result, the open-
loop dynamics of the high-voltage port correspond very closely
to a simple current-fed capacitor (i.e., a first-order system). Once
again, the loop bandwidth must be limited sufficiently below the
current loop’s one. In our case, the bandwidth has been set to
100 Hz, with a 50◦ phase margin. As shown next, this is sufficient
to ensure a satisfactory performance at the high-voltage side,
even in presence of load transients.
As a preliminary validation of the converter small-signal
model, the transfer functions involved in the most critical part
of the controller’s design have been experimentally measured
and compared to the analytically derived ones (16) and (19) at
nominal power. The measurement results are shown in Fig. 11.
A reasonable match is found between the model and the exper-
iment, validating the performed analysis and design.
D. Digital Controller Implementation
The digitalization of the aforementioned regulators is not
critical, as the ratio between the expected crossover frequencies
and the sampling frequency, here equal to fsw , is very low.
This implies that any common discretization approach is able to
offer an adequate accuracy in replicating the regulator frequency
response. In our case, standard Euler discretization was used for
all the controllers. Overall, the continuous time design presented
earlier can be turned into a digital equivalent.
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4693
Fig. 12. Experimental setup with BIBCI and ultracapacitor.
V. EXPERIMENTAL VERIFICATION
In order to verify the theoretical analysis and the controller de-
sign procedure, several experimental tests have been performed
on a BIBCI converter with parameters in Table I. The control
system is implemented in a NI sbRIO-9606 control board.
Specifically, the control algorithm is implemented on the built-in
field-programmable gate array unit, which is programmed and
managed by means of NI LabVIEW. Other platforms, such as
DSP-based ones, may be employed as well. The final experimen-
tal setup is shown in Fig. 12. In the following, the performance
of the proposed control system is discussed showing: the dy-
namic response of the inner closed-loop controllers and some
tests of the BIBCI operating with the proposed controller as a
bidirectional bridge between a low-voltage ultracapacitor and a
high-voltage dc-bus.
A. Dynamic Response Test of Closed-Loop Controller
To test the dynamic closed-loop response of the proposed
controller, at first, a Chroma dc power supply is used as the low-
voltage source of BIBCI. The PI controller of vCL is verified first,
as shown in Fig. 13. In this experiment, the control parameter
ϕ is given a constant value. The PI regulator parameters of vCL
loop are kpV CL = 0.01 V−1 and kiV CL = 3000 (V · s)−1 . In the
converter prototype, taking into account transducer gains and
numerical conversions, these values correspond to the desired
crossover frequency and phase margin.
∗
In Fig. 13, errvCL is the error between the reference value vCL
and the measured value of vCL , made visible by means of the
DAC of the NI sbRIO-9606. As can be seen, the steady state
 4694 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 5, MAY 2022

Fig. 13. Dynamic response test of single-loop controller of vCL , when

values of RLoad and vL are 300 Ω and 48 V, respectively. (a) Rising
∗ from 70 to 80 V. (b) Falling step
step of reference clamp voltage vCL
∗ from 80 to 70 V.
of reference clamp voltage vCL

Fig. 14. Dynamic response test based on double-loop controller of vCL

∗
and iDCL , when values of RLoad , vL , and vCL are 300 Ω, 48 V, and 80 V,
respectively. (a) Rising step of low-voltage side reference current i∗DC Fig. 15. Step response test of load based on triple-loop controller of
L ∗ and v ∗ are 100 and 400 V,
from 3 to 4 A. (b) Falling step of low-voltage side reference current i∗DC vCL , iDCL , and vH , when values of vCL H
L
from 4 to 3 A. respectively. (a) Falling step of RLoad from 360 to 180 Ω. (b) Rising step
of RLoad from 180 to 360 Ω.

is reached in about 0.7 ms, a value in good agreement with the

The current delivered by the power supply is periodically stepped
target bandwidth of 1.5 kHz.
from 0 to 3 A, so as to induce a power flow reversal on the
Subsequently, the iDCL PI controller is activated and operates
ultracapacitor. Indeed, when the current source is set to 0 A,
in parallel with the clamp voltage one. The response of the
the load power (around 450 W) comes entirely from the ultraca-
system to step changes of the low-voltage side current reference
pacitor (discharging phase). On the contrary, when the current
i∗DCL is shown in Fig. 14, where erriDCL is the error between
source is set to deliver 3 A to the high-voltage dc-bus, the control
the reference value i∗DCL and the measurement value iDCL .
system needs to use the ultracapacitor as a power sink, draining
The second PI regulator parameters are kpIm = 0.001 A−1 and
the surplus power (around 800 W, charging phase). Fig. 16(a)
kiIm = 3000 (A · s)−1 . A 25% raising and falling step variation
shows the ultracapacitor current resulting from the power flow
of i∗DCL is performed, after which the system takes around
reversal, whereas Fig. 16(b) and (c) show the detail of each
1.61 ms to restore the steady state. Notably, the settling time is
transition. As can be seen, the high-voltage dc-bus and the
in good agreement with a target bandwidth in the few hundred
clamp voltage are kept stable both during the relatively fast
hertz range.
transitions and over the long-term charging and discharging
Finally, Fig. 15 demonstrates the converter’s response to
phases.
a high-voltage side 50% resistance step, again based on the
triple closed-loop controller. It further proves that the triple-loop
controller, designed according to the proposed model, operates C. High-Voltage Bus Fault Test
stably with good steady-state and dynamic characteristics. A further experiment is made to evaluate the bridging con-
verter and control system performance during fault conditions.
B. Ultracapacitor Bridging Test To this purpose, with the current limiter of i∗DCL set at 20 A in
the PI regulator, an overload fault condition is applied to the
As mentioned earlier, a possible target application for the
vH port, as shown in Fig. 17, producing a voltage sag of about
BIBCI converter equipped with the proposed controller is bridg-
50%. Thanks to the limiter, the converter goes though the fault
ing, with galvanic isolation, two dc-buses at significantly differ-
condition in a controlled manner and vH automatically recovers
ent voltages. Specifically, an ultracapacitor is considered as the
to its nominal value after fault removal.
low-voltage side dc-source/sink of the BIBCI, whose operating
voltage is in the range 0–56 V. The high-voltage side of the
BIBCI is instead set at 400 V and actively controlled by the D. Black Start Test
BIBCI converter. A purely resistive load RLoad is connected The successful operation of the BIBCI as an ultracapacitor
to the high-voltage dc-bus. The same bus is also fed by an interface converter in a nanogrid requires the ability to operate
external power supply, operated as a controlled current source. a system black start (i.e., start-up from de-energized condition).

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 ZHANG et al.: MIMO CONTROL OF A HIGH-STEP-UP ISOLATED BIDIRECTIONAL DC–DC CONVERTER
Fig. 16. Step response test of externally injected current into the dc-
bus by a power supply connected in parallel with the high-voltage side
of the BIBCI. Values of vCL ∗ and v ∗ set at 100 and 400 V, respectively.
H charging phase. Meanwhile, the BIBCI keeps control of vH ,
(a) Whole transient. (b) Injected current rise transient from 0 to 3 A. (c)
Injected current fall transient from 3 to 0 A.
This experiment is illustrated in Fig. 18, taken from a Keysight
PA2203 A IntegraVision power analyzer. In this test, the system
starts with zero voltage across the ultracapacitor and zero voltage
on the high-voltage dc-bus. Then, an external dc source with
voltage and maximum current of 410 V and 3 A, respectively,
is connected to the dc-bus. This configuration can model the
operation of a photovoltaic source feeding the dc-bus. In the
beginning, due to output voltage is lower than the reference
∗
voltage of vH (400 V), the BIBCI transfers zero current, being
the ultracapacitor discharged. As vH reaches the set-point at
400 V, the BIBCI voltage loop controller automatically diverts
power to the ultracapacitor. Thanks to the limiter in the con-
troller organization, the charging current (iDCL ) is automatically
saturated at 25 A, and the low-voltage vL starts rising linearly.
After around 150 s, the ultracapacitor input power reaches the
maximum output power of external dc source. As a result,
iDCL exits saturation and starts decreasing, in a constant power
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4695
Fig. 17. High-voltage port fault test. The bridging converter limits the
ultracapacitor current during the fault, and safely resumes control of vH
when the fault is removed.
Fig. 18. Black start test of the ultracapacitor interface converter. The
efficiency η is calculated as the ratio between the power delivered at the
low-voltage port and the power drawn from the high-voltage port.
making it regulated to the given reference value (i.e., 400 V).
As can be seen, the conversion efficiency is minimum at low
voltage, being around 70%, but grows above 90% as soon as the
ultracapacitor voltage reaches just about 15 V.
VI. CONCLUSION
This article discussed the implementation of a digital MIMO
controller for a BIBCI converter with PPS modulation. The
small-signal, linearized model of the converter was derived
and then used to design the three PI-type regulators required
by the proposed control architecture. To verify the functional-
ity of the controller, measurements were taken on a 1.5-kW
prototype, showing satisfactory results both in the steady state
and during different types of transient conditions. Notably, the
BIBCI converter, equipped with the proposed controller, was
proven adequate to implement a bridging function, with galvanic
isolation, between a low-voltage energy storage device, namely
an ultracapacitor, and a higher voltage dc-bus. This functionality
can be very useful for the operation of smart (hybrid) nanogrids.
 4696 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 69, NO. 5, MAY 2022
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Yuchen Zhang (Student Member, IEEE) re-
ceived the B.S. and M.S. degrees in electri-
cal engineering in 2015 and 2018, respectively,
from the School of Automation, Northwestern
Polytechnical University, Xi’an, China, where he
is currently working toward the Ph.D. degree in
on digital control of bidirectional dc-dc convert-
ers.
From 2019 to 2021, he was a Visiting Ph.D.
Student with the Department of Information En-
gineering, University of Padova, Padova, Italy.
His research interest includes digital control for bidirectional dc–dc con-
verters.
Giorgio Spiazzi (Member, IEEE) graduated
cum laude in electronic engineering from the
University of Padova, Padova, Italy, in 1988,
and received the Ph.D. degree in industrial elec-
tronics and informatics from the University of
Padova, in 1993.
He is currently an Associate Professor with
the Department of Information Engineering,
University of Padova. His current research in-
terests include dc–dc converters for renewable
energy sources, soft-switching techniques, and
electromagnetic compatibility in power electronics.
Simone Buso (Member, IEEE) received the
M.Sc. degree in electronic engineering and the
Ph.D. degree in industrial electronics from the
University of Padova, Padova, Italy, in 1992 and
1997, respectively.
He is currently an Associate Professor of
Electronics with the Department of Information
Engineering, University of Padova. His main re-
search interests include related specifically to
switching converter topologies, digital control of
power converters, and smart microgrids.
Tommaso Caldognetto (Member, IEEE) re-
ceived the M.S. (Hons.) degree in electronic
engineering and the Ph.D. degree in informa-
tion engineering from the University of Padova,
Padova, Italy, in 2012 and 2016, respectively.
He is currently a Researcher and Lecturer
with the Department of Technology and Man-
agement, University of Padova. His research
interests include the control of grid-tied convert-
ers, microgrid architectures, converters for dc
nanogrids, and real-time simulation for power
electronics applications.
Dr. Caldognetto has been an Associate Editor for the IEEE OPEN
JOURNAL OF POWER ELECTRONICS since 2019.