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reRas Caine SF Registers C 16 bit) ca ry Ee Alea eats ets ee Qx—> bse Cx —— —Comt DX ——> Dota @ Pointere & Index pa SUSikoS 6! —s Sounce Index eo ercre Meld Cl Oe eae a Se eae @ Seq ment pee inieks * 16 bit data bus * 20 bit address bus —can address up to 1MB memory — Intel has 2 peculiarities in accessing memory * memory must be divided in to 2 banks * instead of a flat memory, it uses segmented memory * 21 bit control bu: * most of the lines/pins are used for more than one purpos —hence they are multiplexed (aNOP NaS LCC Ad SUIS Cd RS 20 bt bet §& wer iii Xe TS aS eS Ray addeess in aoe ial dia So +o locate ‘he next insinuction jn aoa we need two nae SO, aint he a CECT Cery Ohta canal OT a So Fe ed an aan ee Balto Stont of Sail nes 14330) Cae l4 22367 Sars ce ers poToNea lg 4042.H , Orono] Note > Hex Csxil0, + IP Nene oar] Sense PENTEL T PaO D Te ) (40420 EOL) = ea nLrO nny SH con Re8 2 Fine eee ean ; id roar) ©5 30H = \408,, ee eed a Oe caro aT em Iob} eS BP are rence he alate ee Fa) aaa CCS tLe Ce a eo ee S6&: B640H Se acne BP. 49264 SSKioy+ BP =(36 40H KOH + 43264 Cees) ea Pay OCC eae cLS) as ee apenas Sad ano TS Ob so we hae @ lot locadiong and Mats ines Cad ala oni dota (_memember- C8 bit) byte “oe » . eas Felons MC Rig location Coming (oe Nour P ar Pacey aL | TT eta So OL A ia Vocati6% Contains 2 bit- To access 16 bits Pom two different (cating We hae oo ole eC OCS) Pt eo Col 80 The natal (ON SMe Kel —1e) eo into two Parts (_bongg) . One bank CN GC -) Ce a a oc ae Sn (ofl a eCL ae ao bom, —> lower bany Os oe alle rane &cheme allows to access tulo aUyo a? aa Se aa etc a gC dal APR inlaiaa: 5 Pee as ola Seu ea Se ee ee dar beg and ach memory location (Ie Cols te of data. ean alee eS 42) aly many Roe 43) Tot) amount Os 4 Clocs a) emo) reer NTU Vesti} Pe ee shes) as oe ae deoctivaked (Get PRC al) i) meses ere es) OT a ener SSS on Ee Sai ALE Signa) Remadas active ( |utehed [eX lo Cty stosle) externa] memory devices Access Crore Pree memes fe reli Ae9 UP Sete Aleck oat a LT When dealing with externd a Wied oN ee Lda rohan Oa COMI po >» Avanfization . aA Sant SF oe clock te Systemize mh Roe LS te ec SST) aN .o) ae 4 oscillation —> Physica ont aii L Squaqte Wove_ Microprocessor Operation Microprocessor Operation * The time a P requires to complete fetch-decode-execute operation of a single instruction is known as Instruction Cycle * An Instruction Cycle consists of one or more Machine Cycles * A basic uP operation such as reading or writing a byte from or to memory or I/O port is called a Machine Cycle or Bus cycle * A Machine (bus) cycle consists of at least four clock cycles, called T states. * One cycle of a clock is called a State Fetching an Instruction * Step 1 Instruction Pointer (IP) or a program counter is register, that holds the address of the next instruction to be fetched. Fetching an Instruction * Step 2 Fetching an Instruction 001 Fetching an Instruction * Step 4 The memory location ofthe next instruction islocated 001 Memory Access Register Fetching an Instruction * Step 5 Memory location contents i = [cp The contents of memory atthe 002 FAO given location are movedacrossthe data bus 0100 oct 0010 Fetching an Instruction = Step 6 ~ Memory location — 002 J Into the instruction register (IR) OFFF InstructionRegster

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