IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO.
1, JANUARY 2013
Digital Plug-In Repetitive Controller for
Single-Phase Bridgeless PFC Converters
Younghoon Cho, Student Member, IEEE, and Jih-Sheng (Jason) Lai, Fellow, IEEE
Abstract—This paper investigates a plug-in repetitive control
scheme for bridgeless power factor correction (PFC) converters
to mitigate input current distortions under continuous conduction
mode and discontinuous conduction mode operating conditions.
From the PFC converter model and the fact that a type-II compen-
sator is used, a design methodology to maximize the bandwidth of
the feedback controller is suggested. After that, the error transfer
function including the feedback controller is derived, and the sta-
bility of the repetitive control scheme is evaluated using the error
transfer function. The implementation of the digital repetitive con-
troller is also discussed. The simulation and experimental results
show that the input current THD is significantly improved by us-
ing the proposed control scheme for a 1-kW single-phase bridgeless
PFC converter prototype.
Index Terms—AC–DC converters, bridgeless power factor cor-
rection (PFC) converter, digital average current control, repetitive
control.
I. INTRODUCTION
RIDGELESS power factor correction (PFC) converters
B which do not have a diode bridge rectifier have been ex-
tensively used in many applications due to high efficiency and
simple control features [1]–[3]. For the control of a bridge-
less PFC converter, either an analog or a digital controller can
be employed, and most of the traditional control strategies for
boost PFC converters can be directly applied for controlling the
bridgeless PFC converter. Generally, a digital control scheme
can easily implement various control logics and sequences for
the converter operation as well as interfacing an upper level con-
troller in convenient. One problem of the digital control scheme
for the bridgeless PFC converter, however, is that the current
control bandwidth cannot be as high as an analog controller due
to the digital delay effects caused by the digital pulse-width mod-
ulation (DPWM) delay and the digital computation delay. Ac-
cordingly, the performance of the input current regulation with
a digital controller is relatively poorer than the case with an ana-
log controller implementation. To overcome this low bandwidth
of the digital current controller for boost or bridgeless PFC con-
verters, the input voltage duty feed-forward or the admittance
compensation methods have been proposed [4], [5]. Although
Manuscript received December 14, 2011; revised February 16, 2012 and
April 2, 2012; accepted April 13, 2012. Date of current version September 11,
2012. Recommended for publication by Associate Editor K. Ngo.
The authors are with the Virginia Polytechnic Institute and State University,
Blacksburg, VA 24060 USA (e-mail: yhcho98@vt.edu; laijs@vt.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2196288
0885-8993/$31.00 © 2012 IEEE
165
these methods improve overall current regulation performance,
they may not work perfectly for harmonic components or the
current distortion near a zero-crossing point (ZCP) where higher
control bandwidth is necessary [6]–[8]. Several previous stud-
ies have dealt with this problem. In [8], the method is proposed
using separate control parameters for continuous conduction
mode (CCM) and discontinuous conduction mode (DCM) to
improve the current control performance. In [9], the inductor
current sampling correction and the feed-forward gain schedul-
ing strategy for CCM and DCM have been proposed. In [10],
a correction factor is defined, and the inductor current sample
and the feed-forward gains are modified based on the correction
factor to enhance the current control characteristics in DCM.
In [11], the variable-frequency predictive digital current mode
control is proposed for CCM and DCM operation.
Since the current distortion is usually periodic, a repetitive
control scheme which compensates a periodic error in a con-
trol system can be a good solution to resolve this issue. There
are several research articles about repetitive control schemes in
power electronic converter and inverter applications [12]–[16].
Among those documents, the repetitive control scheme for a
traditional boost PFC converter had been studied in [15].
Traditionally, the early stage of the repetitive control scheme
aims to compensate the frequency components at the multiples
of the electrical fundamental frequency fr . If Ts is defined as
the sampling and iteration period of the repetitive controller, it
requires N memory blocks, where N = 1/(Ts · fr ) [17]–[19].
However, by considering only odd harmonic components to
be compensated rather than including even harmonics, the odd
harmonic repetitive control scheme can be applied, where only
N/2 memory blocks are necessary [15], [20], [21]. A similar
concept with the odd harmonic repetitive control scheme is
called the negative feedback repetitive controller in some studies
[15], [16], [22].
In this paper, a plug-in repetitive controller is designed for
the bridgeless PFC converter to compensate the current har-
monic components. Prior to designing the repetitive controller,
the modeling of the bridgeless PFC converter is performed,
and a type-II compensator-based feedback controller is sug-
gested. After that, the plug-in repetitive controller is designed to
compensate the frequency component which cannot be handled
with the feedback controller alone. By using the rectified con-
trol variables for the bridgeless PFC converter, the frequency
component to be compensated by the repetitive controller is not
the multiples of fr but the multiples of 2fr . Accordingly, only
N/2 memory blocks are necessary. For proving the repetitive
controller operation, the design procedure of the repetitive con-
troller is addressed, and the error transfer function to examine
166
Fig. 1. Single-phase bridgeless PFC converter control structure.
the tendency of the error attenuation with both the feedback
and the repetitive controllers is derived. After that, the stabil-
ity of the entire control system is analyzed by evaluating the
derived error transfer function. The proposed control strategy
shows satisfactory compensating results for current distortions
in steady state as well as stable operation even during transients.
Both simulations and experiments are performed to verify the
designed control strategy for a 1-kW bridgeless PFC converter.
II. MODELING AND CONTROL OF THE BRIDGELESS PFC
CONVERTER
A. Modeling of the Bridgeless PFC Converter
The bridgeless PFC converter demonstrated in this paper is
shown in Fig. 1. To reduce the common-mode noise effect,
diodes Dl and Dh are placed at the input stage [23], [24]. When
the switches Sp and Sn are left open, the input current ig free-
wheels through Lp , Dp , and Dl in a positive cycle of the input
voltage v g , whereas ig flows via Ln , Dn , and Dh in a negative
cycle of v g . The purpose of this converter control is to regulate
the output voltage Vo across the load Ro as well as shaping ig
to be sinusoidal. In order to do this, the external output voltage
controller Gcv (z) and the internal input current controller Gcc (z)
are employed. In this paper, these controllers are implemented
in a digital controller. By considering a general and popular
solution in industry, the digital controller performs sampling
of the control variables, computation of the control algorithm,
and updating of the pulse-width modulation (PWM) signal in a
single PWM switching cycle. These control actions in the dig-
ital controller induce digital delay effects. By considering the
digital delay effects, two modeling blocks are placed in Fig. 1.
One is the zero-order hold (ZOH) block in front of the com-
parator, and the other is the unit delay block z−1 between the
controller output d and the modulator. The roles of the ZOH
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
block and z−1 are to model the DPWM update and the compu-
tation delays, respectively [25]–[27]. For the current controller,
the feed-forward term with the gain Kff is applied to compensate
the admittance component of the input voltage variation [4]. If
Lp and Ln are the same as L, a high frequency approximated
control-to-inductor model of the converter Gid (s) is written as
follows [4]:
Vo
Gid (s) = . (1)
sL
If the ZOH and z−1 are incorporated with (1), the z-domain
control-to-inductor model Gid (z) is derived as [28]
Vo Ts
Gid (z) = . (2)
Lz (z − 1)
B. Feedback Controller for the Bridgeless PFC Converter
In Fig. 1, the loop gain of the open-loop system including
Gcc (z) and Gid (z) is defined as follows:
Ti (z) = Gcc (z)Gid (z). (3)
The performance of the current controller Gcc (z) is deter-
mined by the crossover frequency which corresponds the band-
width of the closed-loop system and the phase margin at the
crossover frequency of Ti (z). If the switching frequency is de-
fined as fs , the maximum bandwidth of a PFC converter may
be reasonably limited around fs /6 with a proper phase margin
using an analog controller [4], [29]. However, with the digital
controller, it may not be possible to achieve such a high band-
width due to the digital delays. Consequently, the performance
of the input current regulation will decline. To examine the max-
imum bandwidth with the digital controller, let us assume that
Gcc (z) is implemented in a type of proportional-integral (PI)
or type-II compensator. In this case, the phase boost of Gcc (z)
in the high-frequency region is at best 0◦ . From this fact, it is
intuitively supposed that the phase of Ti (z) near the crossover
frequency is mainly determined by the phase of Gid (z) since
almost no phase boost is arisen by Gcc (z) at that region. Ac-
cordingly, the phase of Ti (z) is obtained as (4) by substituting
z = ej 2π f c T s into (2)
 
−1 sin (4πfc Ts ) − sin (2πfc Ts ) 180
θid = − tan × . (4)
cos (4πfc Ts ) − cos (2πfc Ts ) π
If fc in (4) is defined as the desired crossover frequency, θid
is understood as the maximum phase margin at that crossover
frequency. On the other hand, if θid is decided, the maximum
achievable bandwidth of the closed-loop control system is sup-
posed as fc . Note that only Ts and θid are related to determine
the maximum bandwidth.
C. Feedback Current Controller Design
Table I shows the parameters of the bridgeless PFC converter.
From the table and (2), the numerical expression of Gid (z) is
written as follows:
12.5
Gid (z) = . (5)
z (z − 1)
CHO AND LAI: DIGITAL PLUG-IN REPETITIVE CONTROLLER FOR SINGLE-PHASE BRIDGELESS PFC CONVERTERS
TABLE I
BRIDGELESS PFC CONVERTER PARAMETERS
Input filter inductance (L)
Output capacitance (C)
Input root-mean-square (RMS) voltage (Vg)
Output voltage (Vo)
Switching frequency (fs)
Sampling frequency (Ts)
Fig. 2. Frequency response of Gi d (z), Gc c (z), and Ti (z).
If the target phase margin of the closed-loop system is 50◦ , the
maximum achievable bandwidth is obtained as nearly 2.9 kHz
from (4). By considering a little parameter mismatch, the target
bandwidth to be designed is selected as 2.7 kHz. If the sys-
tem model, the target bandwidth, and the target phase margin
are given, the well-known K-factor approach [30], [31] can be
applied to design the type-II compensator-based feedback con-
troller as follows:
(z + 1) (z − 0.9867)
Gcc (z) = 0.029635 . (6)
(z − 1) (z + 0.7483)
Fig. 2 compares the frequency responses of Gid (z), Gcc (z), and
Ti (z) up to the Nyquist frequency fnyq . As shown in the fig-
ure, the crossover frequency and the phase margin which are
the bandwidth and the phase margin of the closed-loop system
satisfy the design specification, 2.7 kHz and 50◦ . The phase of
Ti (z) is also following the phase of Gid (z) in the high-frequency
range as analyzed in the previous section.
III. PROPOSED PLUG-IN REPETITIVE CONTROLLER
A. Plug-In Repetitive Controller for a Bridgeless PFC
Converter
Fig. 3 shows the proposed control structure including the
plug-in repetitive controller Gr p (z) which is paralleled by the
feedback controller Gcc (z). For convenience of the analysis, the
feed-forward gain dff is purposely omitted. The repetitive con-
trol scheme based on the internal model principle [32] is to
167
400 µH
1120 µF
120 V
200 V
40 kHz
25 µs
Fig. 3. Plug-in repetitive control structure.
Fig. 4. Equivalent structure of the current controller.
obtain very accurate reference tracking for the closed-loop con-
trol system, where the tracking error is periodically repeated.
The repetitive controller Gr p (z) compensates the repetitive er-
ror which requires a bandwidth higher than Gcc (z) can handle.
As shown in Fig. 1, with the rectified control variables, the fun-
damental compensating frequency of Gr p (z) will be twice the
fundamental frequency fr . Hence, Gr p (z) requires N/2 memory
blocks rather than N blocks for one fundamental cycle unlike
the other applications. Note that the physical meaning of the
reduced sampling number in this case is different from the odd
harmonic repetitive controller described in [20] and [21]. Al-
though it is not discussed in this paper, it is supposed that only
N/4 memory blocks are necessary when the odd harmonic repet-
itive controller is employed for the bridgeless PFC converter. In
Fig. 3, L, q(z), and Kr p represent the number of samples for the
phase leading, the stabilization filter, and the gain of the repeti-
tive controller which will be explained in a later section. From
Fig. 3, Gr p (z) is written as follows:
dr p zL
Gr p (z) = = Kr p N /2 . (7)
ier r z − q(z)
In order to see how the loop gain of the control system is affected
by the plug-in repetitive controller, an equivalent model of the
control blocks in Fig. 3 can be drawn as in Fig. 4.
Here, it is assumed that the admittance component caused by
the ac input voltage is compensated by the feed-forward duty
dff . In Fig. 4, Tif b (z) is defined as follows:
Ti (z)
Tif b (z) = . (8)
1 + Ti (z)
The physical meaning of Tif b (z) is the closed-loop gain of the
bridgeless PFC converter where only the feedback controller
Gcc (z) is used. From Fig. 4, the relationship between the in-
put current reference i∗g and the current error ier r is written as
168 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

follows which is a similar form derived in [32]:

ier r (z) 1
Ge (z) = =
i∗g (z) 1 + Ti (z)
z N /2 − q(z)
× . (9)
z N /2 − (q(z) − Kr p z L (Gid (z)/(1 + Ti (z))))
If all of the magnitudes of the roots for Ge (z) are less than unity,
all the poles of Ge (z) are located in the unit circle in the z-domain
so that Ge (z) remains stable. At that situation, the roots of the
denominator (1 + Ti (z)) are identical to the roots of Tif b (z).
Hence, the roots for (1 + Ti (z)) are located within the unit circle
as long as Tif b (z) is stable. Accordingly, the stability of Ge (z) is
determined by the roots of the remaining term. Let the function
of the roots H(z) be defined as follows:
Gid (z)
H(z) ≡ q(z) − Kr p z L . (10)
1 + Ti (z)
If H(z) meets the condition below, the control system becomes
stable according to the small gain theorem [17], [18], [32]
|H(z)| < 1. (11)
Meanwhile, by setting Kr p = 0, Ge (z) can be rewritten as
ier r (z) 1
Ge (z) = ∗
= . (12)
ig (z) 1 + Ti (z)
In this case, Ge (z) represents the error transfer function of Gcc (z)
only. The entire closed-loop gain Ticl (z) which includes the
feedback and the plug-in repetitive controllers is represented as
follows from (9) or (12):
eg (z) i∗g (z) − ig (z)
Ge (z) = ∗
= ⇒ Ticl (z) = 1 − Ge (z).
ig (z) i∗g (z)
(13)

B. Practical Design Procedure

In order to design a stable repetitive controller, the design
parameters L, q(z), and Kr p should be selected to satisfy (11).
For selecting the number of the samples for the phase leading L,
the time delay effect between the controller and the actual plant
should be considered. Generally, the time delay effect disturbs
the convergence of the error and produces an unstable repetitive
control action. The role of L is to compensate this time delay
effect. By using L, the recursive error in the memory blocks is
leading the actual error. Accordingly, the stability of the repet-
itive control system can be improved. In this paper, the time
delay effect caused by the digital PWM update and the compu-
tation delay is supposed to be 1.5Ts . Hence, by considering a
little margin, L is chosen as 2. On the other hand, the control
action at the high-frequency region where the compensation is
not available due to the physical limitation should be restricted
for stable operation of the repetitive controlled system. Without
a proper compensation method, the stability of the control sys-
tem is not guaranteed because the magnitude of the repetitive
controller output is too high at that high-frequency range. The
factor to mitigate this situation is the stabilization filter q(z). In
 
Fig. 5. Trajectories for the roots of H(z): (a) q(z) = z + 2 + z −1 /4 and
(b) q(z) = 0.95.
this paper, two traditional methods for q(z) are introduced. One
method is to select q(z) as a low-pass filter which has zero phase
delay as follows [18], [33]:
 
z + 2 + z −1
q(z) = . (14)
4
In
 fact, some
 other expressions such as q(z) =
z + 6 + z −1 /8 can also be applied [18]. Another method is
just to select q(z) as a constant number less than unity, e.g.,
0.95 [17], [34]. One easy way to select Kr p is to evaluate
whether H(z) satisfies (11) according to the changes of Kr p .
As mentioned before, all the roots of H(z) should be in the
unit circle in the z-domain to meet the condition in (11).
Fig. 5 compares the trajectories of the roots up to the Nyquist
frequency fnyq 20 kHz at different Kr p . In Fig. 5(a), q(z) is
CHO AND LAI: DIGITAL PLUG-IN REPETITIVE CONTROLLER FOR SINGLE-PHASE BRIDGELESS PFC CONVERTERS
 
Fig. 6. Frequency responses of Ge (z): (a) q(z) = z + 2 + z −1 /4 and (b) q(z) = 0.95.
implemented as (14), whereas q(z) is just selected to be 0.95 in
Fig. 5(b).
In Fig. 5, if Kr p is less than 0.03, the trajectories of the roots
converge into the unit circle for both cases. Accordingly, it is
supposed that the repetitive control system is stable because
condition in (11) is satisfied. However, when Kr p is 0.05, it is
observed that the trajectories of the roots go outside of the unit
circle. In this case, (11) cannot be satisfied, and the closed-loop
system becomes unstable.
Fig. 6(a) and (b) compares the frequency response of Ge (z) for
different q(z) implementation. For the purpose of comparison,
the frequency response of Ge (z) without the repetitive controller
is also plotted in both of the figures.
Regardless of the q(z) implementation methods, at the mul-
tiples of 120 Hz, the frequency responses of Ge (z) with the
repetitive controller have notches which are not found in the
case without the repetitive controller. This means that the error
at those frequency regions is effectively cut off with the repeti-
tive controller. On the other hand, by considering different q(z)
implementation cases, the depths of each notch at the multiples
of 120 Hz are more in Fig. 6(a) than in Fig. 6(b). Accordingly,
although the difference is trivial, it is expected that q(z) with
(14) may show better performance than q(z) with the constant
value of 0.95 for blocking the repetitive error component. It is
also monitored that the magnitude of Ge (z) in Fig. 6(a) is better
damped than in Fig. 6(b) over several kilohertz ranges. This is
caused by the low-pass filtering effect of q(z). However, this
may not be a significant difference because the frequency range
is greater than the bandwidth of the closed-loop system.
C. Analysis for DCM Operation
Since the converter operates in DCM near ZCPs or light-
load conditions, the designed repetitive controller should be
evaluated for DCM operation as well. In DCM, the control-to-
inductor current model is written as follows [8]:
vg T s 1
Gid (z) = · .
2L z
169
By considering the computation delay of the digital controller,
Gid (z) is modified as follows:
vg T s 1
Gid (z) = · . (16)
2L z 2
Fig. 7 reevaluates the trajectories of the roots of H(z) and
the frequency response of Ge (z) using (16). The repetitive
control gain Kr p is chosen as 0.03. In Fig. 7(a), for both
q(z) = z + 2 + z −1 /4 and q(z) = 0.95, the trajectories of
the roots of H(z) are within the unit circle and therefore the
operation of the proposed repetitive control scheme is stable
in DCM. Fig. 7(b) compares the frequency responses of Ge (z)
under DCM. As shown in the figure, the notches at the multi-
ples of 120 Hz occur with the repetitive controller. Hence, the
proposed scheme is also useful in eliminating the current error
at the multiples of 120 Hz under DCM operation.
D. Further Discussion on Stability
Basically, the proposed scheme can be directly applied to the
boost converter-based topology variations including traditional
boost PFC converters, bridgeless PFC converters, and so on.
One concern in applying the proposed scheme to those PFC
converters is the stability of the repetitive controller. In order
to improve the stability, the electromagnetic interference (EMI)
noise should be properly suppressed. Under severe EMI noise
environment, the possibility of a current misreading from the
digital controller is increased and the misread current error can
be amplified during the iteration of the repetitive control algo-
rithm. At the end, a small current misreading can drive the entire
system to be unstable. Unlike the converter used in this paper,
where two separated inductors and two freewheeling diodes are
employed, the bridgeless PFC converter consisting of one in-
ductor and no freewheeling diodes needs more careful design
for adapting the proposed scheme. This is because the latter may
suffer more from EMI noise than the former. In this case, one
good solution is to select a lower cut-off frequency or constant
value of q(z). By doing so, the stability of the converter would
(15)
170 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013

Fig. 7. Analysis of the repetitive control system under DCM operation. (a) Trajectories for the roots of H(z). (b) Frequency response of Ge (z).

be improved, but the ability of the harmonic elimination at the

steady state will be degraded.

IV. SIMULATION STUDY

In order to see the effectiveness of the designed controllers,
simulation studies have been performed using the simulation
software package PSIM. All parameters used in the simulation Fig. 8. Implemented block diagram of Gr p (z).
are identical to the values in Table I. Here, the grid impedance
which always exists in actual case is modeled as a 200-μH
inductance. For the feedback controller, the transfer function in
(6) is employed. The repetitive controller is realized by
 using
Kr p = 0.03, L = 2, N = 666, and q(z) = z + 2 + z −1 /4

0.03z 2
Gr p (z) = . (17)
z 333 − 0.25 (z + 2 + z −1 )

Fig. 8 showsthe implemented block diagram of the repetitive

controller. In addition to the feedback and the repetitive con-
trollers, the duty feed-forward term dff is implemented. Al-
though the duty feed-forward improves the current regulation
performance dramatically, it may not work perfectly as expected
in theory. One reason is that the measureable input voltage is not
the original source voltage but the voltage through the source
impedance. Unless the system has relatively much higher input
inductor compare to the grid impedance, the sensed voltage suf-
fers from the switching ripple. In this case, a low-pass filter at Fig. 9. Simulation result without and with the repetitive controller. (a) In-
put current at 1 kW operation (5 A/div). (b) Current error at 1 kW operation
the output of the voltage sensor is essential to filter out the high- (0.5 A/div). (c) Input current at 100 W operation (1 A/div). (d) Current error at
frequency switching ripple between the grid impedance and the 100 W operation (0.5 A/div).
PFC inductors, and this low-pass filter and the grid impedance
induce at least a few degrees’ phase shift between the original
source voltage and the measured voltage. Another issue with Fig. 9 compares the simulation result under the different load
the duty feed-forward scheme is that it may not work correctly conditions, 1 kW and 100 W. Before applying the repetitive con-
under the input voltage distortion or the DCM operation where troller, the peak-to-peak magnitude of the current error is almost
the desired shape of the duty cycle to regulate the phase current 3 A in each case. However, with the designed repetitive con-
sinusoidal is not exactly matched with the tendency of the input troller, both of the peak-to-peak current errors are limited to 1 A
voltage. in two electrical cycles.
CHO AND LAI: DIGITAL PLUG-IN REPETITIVE CONTROLLER FOR SINGLE-PHASE BRIDGELESS PFC CONVERTERS
Fig. 10. Input current THD comparison.
Fig. 11. Zoom-in waveforms near a ZCP.
Fig. 10 compares the input current total harmonic distortion
(THD) with traditional feedback and feed-forward scheme and
the proposed scheme. As can be seen in the figure, the proposed
method shows better THDs in entire operating range.
Fig. 11 shows the zoom-in current waveforms near a ZCP
when the output power is about 500 W. The reason of the current
increasing right after crossing the ZCP is because of DCM oper-
ation of the PFC converter with Gcc (z) that is designed for CCM
operation and the imperfect duty feed-forward compensation.
If Kr p = 0.0, so that the repetitive controller is not operating,
the current distortion is noticeable. However, with the operation
of the repetitive control action by selecting Kr p = 0.03, there
is almost no current distortion near the ZCP. Consequently, the
current error ier r is also limited within ±0.1 A.
The transient response of the control scheme is simulated as
shown in Fig. 12, where the load is changed from 500 W to
1 kW in step. To ignore the effect of the voltage controller, the
input current reference is intentionally changed in step while the
load resistance is altered from 80 to 40 Ω at the same time. As
can be seen in the figure, the step current error is recursive for
several cycles. This is definitely a disadvantage of the proposed
scheme. However, the recursive error totally disappears in few
cycles, and there is no stability issue after that point. In fact, the
unnecessary repetitive control action can be effectively removed
in the software by detecting the rapid change of the current
reference. In practice, the current reference is not changed in
step because of the external voltage controller. Therefore, the
recursive error in the simulation is not a problem in practical
converter operation.
171
Fig. 12. Transient response under the load step change condition.
V. EXPERIMENTAL RESULTS
The proposed control scheme has been tested with a 1-kW
bridgeless PFC converter prototype whose parameters are the
same with the values in Table I with the exception of switching
frequency fs which is chosen as 80 kHz to reduce the current
ripple. The sampling and the iteration period Ts is kept as in the
table. In order to suppress EMI noise, a 0.68-μF filter capacitor
is paralleled with each of the diodes Dl and Dh . As a digital
controller, Texas Instruments’ 32-bit floating-point digital sig-
nal processor (DSP) TMS320F28335 was used. The DSP board
includes a four-channel digital-to-analog converter (DAC) to
monitor the real-time variables in the DSP. The feedback con-
troller Gcc (z) in (6) and the duty feed-forward controller have
been implemented. The designed repetitive controller is added
to Gcc (z) in parallel. In practice, the grid impedance affects the
current control performance, but not too much.
Fig. 13 compares the measured input voltage v g , the input
current ig , and the input current THD without and with the pro-
posed repetitive control scheme. Here, the average input power
P is approximately 57 W which corresponds to 5.7% of the
rated power. As compared in Fig. 13(a) and (c), the proposed
method helps to shape ig to be sinusoidal. The harmonic spectra
of ig are compared in Fig. 13(b) and (d). Generally, the por-
tion of the DCM operation is increased in such a low power
operation, and the feedback and feed-forward controllers whose
design is based on CCM operation may not operate very well.
This causes low-frequency harmonics such as the third order,
fifth order, and so on as shown in Fig. 13(b), where the in-
put current THD was evaluated as 42.35%. With the proposed
repetitive control scheme, the THD is significantly improved
as in Fig. 13(d). In this case, the THD for the input current
was calculated as 29.38%. Although this improvement may not
be meaningful in such a low power operation, it is proven that
the proposed method improves the quality of the input current.
Similarly, the input voltage, the input current, and the input
current THDs are compared in Fig. 14 under approximately
P = 1 kW. Since the CCM operation is dominant under this
condition, the traditional controller works also pretty well as
shown in Fig. 14(a), and it shows the input current THD to be
6.04% as plotted in Fig. 14(b). Fig. 14(c) and (d) provides the
172
Fig. 13. Comparison of experimental results under P = 57 W and Vg =
110 V. (a) Input voltage and input current without the proposed repetitive control
scheme. (b) Input current THD without the proposed repetitive control scheme.
(c) Input voltage and input current with the proposed repetitive control scheme.
(d) Input current THD with the proposed repetitive control scheme.
test results with the proposed repetitive control scheme. Com-
pared to the previous figures, the shape of the input current is
more sinusoidal in Fig. 14(c). Accordingly, as can be seen in
Fig. 14(d), the harmonic contents are reduced, and the input
current THD was also improved from 6.04% to 3.01%.
Fig. 15 shows the performance of the proposed repetitive con-
trol scheme during transients. In Fig. 15(a), at the beginning,
only the feedback and the feed-forward controllers were oper-
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 1, JANUARY 2013
Fig. 14. Comparison of experimental results under P = 1 kW and Vg =
110 V. (a) Input voltage and input current without the proposed repetitive control
scheme. (b) Input current THD without the proposed repetitive control scheme.
(c) Input voltage and input current with the proposed repetitive control scheme.
(d) Input current THD with the proposed repetitive control scheme.
ating under P = 250 W. Under this condition, the peak-to-peak
value of the current error ier r was evaluated as approximately
1.3 A. At t = 0.1 s, the proposed repetitive controller was ap-
plied. Within several cycles, the error converges to within 0.5 A
without severe current distortion or unstable operation. This
amount of the error corresponds to 38% of the current error
under the previous condition.
CHO AND LAI: DIGITAL PLUG-IN REPETITIVE CONTROLLER FOR SINGLE-PHASE BRIDGELESS PFC CONVERTERS
Fig. 15. Transient responses of the PFC converter using the proposed repetitive
control scheme. (a) Performance of the current error convergence with the
startup of the proposed method. (b) Performance of the proposed repetitive
control scheme during the load transient.
Fig. 16. Comparison of experimental results under P = 220 W and Vg =
90 V. (a) Input voltage and input current without the proposed repetitive control
scheme. (b) Input voltage and input current with the proposed repetitive control
scheme.
173
Fig. 17. Comparison of experimental results under P = 230 W and Vg =
240 V. (a) Input voltage and input current without the proposed repetitive control
scheme. (b) Input voltage and input current with the proposed repetitive control
scheme.
In order to see the operation of the proposed repetitive con-
troller during the load transient, in Fig. 15(b), the output power
was changed from 500 to 250 W at t = 0.1 s while the repetitive
controller was working. During the transient, both the input cur-
rent and the current error slowly ramp down since the voltage
controller is working, and there are no severe current spikes or
unstable operations in ig as well as in the steady state. After
the load step down is completed, ier r was also reduced with the
small load as expected in the simulation result.
In Figs. 16 and 17, the converter is tested under universal
input line conditions. For the test, the output dc-link voltage is
set to 400 V, and all control parameters are kept the same.
Fig. 16 compares the input voltage and the input current
without and with the proposed method under Vg = 90 V and
P = 220 W. Without the proposed method, the input current THD
in Fig. 16(a) was about 14.43%. However, with the proposed
method, the input current THD in Fig. 16(b) was read as 5.41%.
In Fig. 17, the input RMS voltage and the average power
were chosen as 240 V and 230 W. The input current THD was
evaluated as 25.92% in Fig. 17(a) without the proposed method,
and 13.05% in Fig. 17(b) with the proposed method. Even if the
converter and the controller are not optimized for the universal
line operation, the experimental results in Figs. 16 and 17 clearly
show that the proposed repetitive control scheme improves the
input current quality in any case.
In Fig. 18, the proposed method was used under different dc-
link capacitance conditions, C = 1120 μF in Fig. 18(a) and C =
150 μF in Fig. 18(b). As can be seen in Fig. 18(b), although the
150 μF capacitor induces much higher double-frequency voltage
ripple—120 Hz in this case—than the 1120 μF capacitor, the
174
Fig. 18. Comparison of experimental results under P = 50 W and Vg = 110 V.
(a) Input voltage, input current, and output voltage with C = 1120 μF. (b) Input
voltage, input current, and output voltage with C = 150 μF.
performance of the input current regulation is not affected. It is
obvious that the double-frequency ripple is periodic so that the
proposed method compensates the effect of the voltage ripple
on the input current regulation.
VI. CONCLUSION
This paper discussed the plug-in repetitive control scheme
for the bridgeless PFC converter. To do this, the design pro-
cedure for the feedback and the feed-forward controllers was
discussed. After that, the proposed repetitive controller was de-
signed to handle the current distortion near the ZCP of the input
voltage and the input current as well as compensating the current
harmonic components. The stability analysis for the PFC con-
verter including the proposed control scheme was performed.
From this analysis, the control parameters for the repetitive con-
troller were selected. By using the designed repetitive controller,
the current distortion could be mitigated both in CCM and in
DCM operations. Both the simulation and experimental results
verified the effectiveness of the proposed control scheme under
various operating conditions including transient and steady-state
operations for the 1-kW bridgeless PFC converter prototype.
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Younghoon Cho (S’10) was born in Seoul, Korea, in
1980. He received the B.S. degree from Konkuk Uni-
versity, Seoul, Korea, and the M.S. degree from Seoul
National University, Seoul, in 2002 and 2004, respec-
tively, both in electrical engineering. He is currently
working toward the Ph.D. degree at Virginia Poly-
technic Institute and State University, Blacksburg.
From 2004 to 2009, he was an Assistant Research
Engineer at Hyundai MOBIS R&D Center, Yongin,
Korea. His current research interests include digital
control techniques for power electronic converters in
vehicle and grid applications, multilevel converters, and high-performance mo-
tor drives.
175
Jih-Sheng (Jason) Lai (S’85–M’89–SM’93–F’07)
received the M.S. and Ph.D. degrees in electrical engi-
neering from the University of Tennessee, Knoxville,
in 1985 and 1989, respectively.
From 1980 to 1983, he was the Head of the Electri-
cal Engineering Department of the Ming-Chi Institute
of Technology, Taipei, Taiwan, where he initiated a
power electronics program and received a grant from
his college and a fellowship from the National Sci-
ence Council to study abroad. In 1986, he became a
staff member at the University of Tennessee, where
he taught control systems and energy conversion courses. In 1989, he joined
the Electric Power Research Institute (EPRI) Power Electronics Applications
Center (PEAC), where he managed EPRI-sponsored power electronics research
projects. In 1993, he was with the Oak Ridge National Laboratory as the Power
Electronics Lead Scientist, where he initiated a high-power electronics program
and developed several novel high power converters including multilevel con-
verters and soft-switching inverters. In 1996, he joined Virginia Polytechnic
Institute and State University, where he is currently a Professor and Director of
the Future Energy Electronics Center. He has published more than 240 techni-
cal papers and 2 books and received 20 U.S. patents. His research interest in-
cludes high-efficiency power electronics conversions for high power and energy
applications.
Dr. Lai received several distinctive awards including a Technical Achieve-
ment Award in Lockheed Martin Award Night, three IEEE IAS Conference
Paper Awards, Best Paper Awards from IECON-97, IPEC-05, and PCC-07. His
student teams received three awards from future energy challenge competitions
and the first place award from TI Enginous Prize Analog Design Competi-
tion. He chaired the 2000 IEEE Workshop on Computers in Power Electronics
(COMPEL 2000), 2001 IEEE/DOE Future Energy Challenge, and 2005 IEEE
Applied Power Electronics Conference and Exposition (APEC 2005).