786
3, MARCH 2010
Digital Average Current Controlled Switching
DC–DC Converters With Single-Edge Modulation
Guohua Zhou and Jianping Xu
Abstract—Digital average current (DAC) control of switching
dc–dc converters with single-edge modulation (trailing-edge and
leading-edge modulations) is studied in this paper. To calculate the
average inductor current with minimum calculation time and ap-
propriate precision, a new algorithm, called the four-point-mean
(FPM) algorithm, is proposed. The DAC control laws with trailing-
edge and leading-edge modulations are derived by using FPM algo-
rithm, and their stabilities are studied. The subharmonic oscillation
of DAC controlled switching dc–dc converters is investigated and
analyzed. It is shown that both digital slope compensation and dig-
ital reposition compensation of the ac component of duty ratio for
digitally controlled switching dc–dc converters cannot eliminate
the subharmonic oscillation of DAC controlled switching dc–dc
converters. Instead, a new method, called digital triangle compen-
sation, for the elimination of the subharmonic oscillation of DAC
controlled switching dc–dc converters is proposed and studied. Ex-
perimental results are given to verify the analysis results.
Index Terms—Digital average current (DAC) control, digital
control, digital triangle compensation (DTC), subharmonic oscil-
lation, switching dc–dc converters.
I. INTRODUCTION
IGITAL control of power electronics has been widely in-
D vestigated recently [1]–[17]. It is well known that digital
control provides less component aging, programmable platform,
and robustness to noise. Moreover, it features short time-to-
market, easy implementation of multiloop control, ability to
interface with digital systems, immunity to components vari-
ations, flexibility to implement sophisticated control schemes,
and so on.
Digital current-mode control of switching dc–dc converters
is one of the most widely applied digital control techniques for
switching dc–dc converters [1], [2], [6], [9], [17]. Current-mode
control can be classified as peak-current or valley-current con-
trol, depending on whether the maximum or the minimum of
the sensed current is compared with a reference. Peak-current
control, which features instantaneous peak current protection,
is the most popular current-mode control method for switching
dc–dc converters. However, for power factor correction (PFC)
applications, the peak-current or valley-current control results
in some line current harmonic distortion. Although this line cur-
rent harmonic distortion can be reduced by biasing the current
Manuscript received March 17, 2009; revised May 30, 2009. Current version
published April 2, 2010. This work was supported by the National Natural Sci-
ence Foundation of China under Grant 50677056, the Cultivation Project of
Excellent Doctorate Dissertation of Southwest Jiaotong University (SWJTU) of
China, and the Doctoral Innovation Foundation of SWJTU of China. Recom-
mended for publication by Associate Editor F. L. Luo.
The authors are with the School of Electrical Engineering, Southwest
Jiaotong University, Chengdu 610031, China (e-mail: ghzhou-swjtu@163.com;
jpxu-swjtu@163.com).
Digital Object Identifier 10.1109/TPEL.2009.2033379
0885-8993/$26.00 © 2010 IEEE
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO.
reference waveform [18], [19], the average current control is still
preferred, compared with peak-current or valley-current control,
which results in very low current distortion without additional
compensation.
One of the key aspects of digital average current (DAC) con-
trol technique is how to calculate the average inductor current
efficiently and accurately. If the information for the calcula-
tion of the average inductor current is not enough, the average
inductor current cannot be accurately calculated, which will re-
sult in large error and degrade the control performance. If the
information for the calculation of the average inductor current
is too much, the calculation will become sophisticated and the
corresponding calculation time will increase, which will lead to
lower control performance due to the time delay to update the
anticipant duty ratio [20].
The control algorithms proposed in [1] are determined by sys-
tem information such as converter topology, inductance, input
voltage, and output voltage, where the average inductor cur-
rent is calculated via numerical integration algorithm or time-
averaged inductor current, which results in more computation
time and complex control laws. Based on a periodic compen-
sating ramp, digital current-mode control algorithms similar to
slope compensation technique in [24] was proposed in [9]. Thus,
control algorithms proposed in [9] are quite different from the
control algorithm proposed in [1]. However, the digital current-
mode controller proposed in [9] still needs system information
to choose appropriate slope of the compensating ramp, i.e., sys-
tem information is needed to derive the control algorithms both
in [1] and [9].
Based on the characteristics of single-edge modulation
(trailing-edge and leading-edge modulations), a new algorithm,
called four-point-mean (FPM) algorithm, to calculate the av-
erage inductor current with minimum calculation time and ap-
propriate precision is proposed and studied in this paper. Based
on this, the control laws of DAC controlled switching dc–dc
converters with single-edge modulation are obtained.
It is well known that subharmonic oscillation exists in ana-
log current-mode control and V2 control (peak-voltage control)
of switching dc–dc converters [21], [22]. It has also known
that subharmonic oscillation exists in its corresponding digital
control manner [1], [9], [23]. Subharmonic oscillation results
in instability issues and produces large ripple voltage and cur-
rent. To eliminate the subharmonic oscillation of digital peak
voltage (DPV) controlled switching dc–dc converters, digital
slope compensation (DSC), and digital reposition compensa-
tion (DRC) of the ac component of duty ratio were proposed
in [24]. However, the analysis results in this paper show that
DSC and DRC proposed in [24] cannot eliminate the subhar-
monic oscillation of DAC controlled switching dc–dc converters
ZHOU AND XU: DIGITAL AVERAGE CURRENT CONTROLLED SWITCHING DC–DC CONVERTERS WITH SINGLE-EDGE MODULATION
Fig. 1. Digitally controlled switching dc–dc converter.
with single-edge modulation. To eliminate this subharmonic os-
cillation, a new method, called digital triangle compensation
(DTC), is thus proposed and studied in this paper. The stabili-
ties of the proposed control laws are studied and the elimination
of subharmonic oscillation of DAC controlled switching dc–dc
converters by using DTC is investigated.
This paper is organized as follows. In Section II, FPM algo-
rithm for the calculation of average inductor current is proposed
and applied to the DAC control technique of switching dc–dc
converters with single-edge pulsewidth modulation, followed
by the analysis of the stabilities of the proposed control laws.
In Section III, it is demonstrated that DSC and DRC proposed
in [24] cannot eliminate subharmonic oscillation of DAC con-
trolled switching dc–dc converters. Thus, the DTC method is
proposed and studied to eliminate the subharmonic oscillation
of DAC controlled switching dc–dc converters in Section IV.
Experimental results are provided in Section V to verify the
analysis results.
II. DAC CONTROL TECHNIQUE WITH FPM ALGORITHM
Fig. 1 shows the configuration of digitally controlled switch-
ing dc–dc converter, in which a buck converter is taken as
an example, with the digital controller consists of analog-to-
digital converter (ADC), digital compensator (D-PID), and digi-
tal pulsewidth modulator, on which various digital control tech-
niques can be realized with corresponding digital pulsewidth
modulation (DPWM) algorithms.
In Fig. 1, Vdref , vg , and vo are the reference voltage, input
voltage, and output voltage, respectively; vs is the sampled out-
put voltage in the outer loop, is is the sampled inductor current
flowing through inductor L in the inner loop, ic is the control
signal generated by compensating the error signal between Vdref
and vs in D-PID block, Re is the equivalent series resistor (ESR)
of output filter capacitor C, and R is the load resistor.
A. DAC With Trailing-Edge Modulation
Fig. 2 shows the inductor current waveforms of DAC con-
trolled switching dc–dc converter with trailing-edge modula-
tion [1], with the transistor switch S1 turned on at the beginning
of each switching cycle Ts , i.e., turned on at t = (n − 1)Ts ,
and turned off after time interval dn −1 Ts , i.e., turned off at
787
Fig. 2. Inductor current waveforms of DAC with trailing-edge modulation.
t = (n − 1)Ts + dn −1 Ts , where dn −1 is the active duty ratio
(switch S1 in “ON” state) of the (n − 1)th switching cycle, with
dn −1 = 1 − d
n −1 . The switch S1 will remain off until the end
of the present switching cycle.
In Fig. 2, the solid line corresponds to the steady-state oper-
ation, while the dashed-dotted line shows the inductor current
with a perturbation îL (n − 1) injected at the beginning of the
(n − 1)th switching cycle. If a perturbated inductor current is
sensed at the beginning of each switching cycle and no other
perturbations are injected during the present switching cycle,
the perturbation îL (n − 1) will be kept the same in the entire
(n − 1)th switching cycle and it satisfies îL (n − 1) = îL (n).
The control objective of DAC control is to keep the average
inductor current to follow control signal ic , which can be re-
garded as constant in two consecutive switching cycles because
the natural frequency of low-pass filter is much lower than the
switching frequency [25]. d̂ is the ac small signal component
of duty ratio induced by îL (n − 1). Since the input voltage
and output voltage are slow-varying signals, they can also be
considered constant within a switching cycle.
For the basic switching dc–dc converters, i.e., buck converter,
boost converter, and buck-boost converter, the increasing and
decreasing slopes of inductor current in Fig. 2 are given as
follows:
m1 = (vg − vo )/L m2 = vo /L (1a)
m1 = vg /L m2 = (vo − vg )/L (1b)
m1 = vg /L m2 = −vo /L. (1c)
From Fig. 2, we have
is (n) = is (n − 1) + m1 dn −1 Ts − m2 d
n −1 Ts (2a)
ip eak (n) = is (n) + m1 dn Ts (2b)
is (n + 1) = is (n) + m1 dn Ts − m2 d
n Ts (2c)
where ip eak (n) and dn are the peak inductor current and the duty
ratio of the nth switching cycle, respectively, with d
n = 1 − dn .
For the trailing-edge modulation, the first valley current is (n),
the peak current ip eak (n), and the last valley current is (n + 1)
will be taken to calculate the average inductor current of the
nth switching cycle. From Fig. 2, the average inductor current
788 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 3, MARCH 2010

iavg (n) can be obtained as

is (n)dn + ip eak (n) + is (n + 1)d
n
iavg (n) = . (3)
2
From (2) and (3), it is known that iavg (n) in (3) has a quadratic
term of dn , and the corresponding duty ratio dn has a quadratic
root term, which results in inappropriate precision when they
are approximated by linear term. If the quadratic term in (3) is
considered to calculate the average inductor current accurately,
the calculation of (3) and predicted duty ratio dn are rather
complicated and need more computation time, which results in
more time delay and thus, degrades the control performance.
To have a more insight into the algorithm of the calculation
of average inductor current, let us define ∆d = 0.5 − dn , then, Fig. 3. Inductor current waveforms of DAC with leading-edge modulation.
we have |∆d| ≤ 0.5. From (2c) and (3), we further have
is (n) + 2ip eak (n) + is (n + 1) where Ic , Is , and D are the control objective current, the valley
iavg (n) =
4 current, and the duty ratio in steady state, respectively.
m1 dn − m2 d
n When the current perturbation îL (n − 1) is injected, to make
+ ∆dTs . (4) the average inductor current of the nth switching cycle equal
2
to Ic by using FPM algorithm, the following equation can be
During steady state, we have m1 dn = m2 d
n ; thus, the second
obtained:
term of the right-hand side of (4) equals to zero. While during
transient, as the second term of the right-hand side of (4) is at is (n) + 2[is (n) + m1 dn Ts] + [is (n) + m1 dn Ts − m2 d
n Ts]
Ic = .
least an order of magnitude smaller than ipp = max (m1 dn Ts , 4
m2 d
n Ts ), which is in proportional to inductor current ripple (8)
of the converter, therefore, if inductor current ripple is much From (6) and (8), the predicted duty cycle can be obtained as
smaller than the average inductor current, the second term of 4îL (n)
the right-hand side of (4) can thus be neglected, especially, dn = D − . (9)
(3m1 + m2 )Ts
when dn is closed to 0.5. This is not difficult to meet for high-
frequency switching dc–dc converter in practice. Thus, (4) can From (2c), (7), (9), and the relation of inductor current–volt-
be simplified as second balance in steady state m1 D = m2 (1 − D), the relation
between îL (n + 1) and îL (n) can be deduced as
is (n) + 2ip eak (n) + is (n + 1)
iavg (n) = . (5) îL (n + 1) m1 + 3m2 1 + 2D
4 =− =− . (10)
Compared with (3), (5) is a simple linear equation. Because îL (n) 3m1 + m2 3 − 2D
inductor current is (n), ip eak (n), ip eak (n), and is (n + 1) at four
It is obvious that when D > 0.5, we have |−(1 + 2D)/(3 −
points in one switching cycle are used to calculate the aver-
2D)| > 1, which means that DAC with trailing-edge modulation
age inductor current, the algorithm in (5) is called the FPM
will lead to subharmonic oscillation when duty ratio is greater
algorithm.
than 0.5.
From (2) and by substituting the control objective iavg (n) =
ic into (5), the predicted duty ratio can be given as
B. DAC With Leading-Edge Modulation
4[ic − is (n − 1)] 4(m1 + m2 ) 5m2
dn = − dn −1 + . The key inductor current waveforms of DAC controlled
(3m1 + m2 )Ts 3m1 + m2 3m1 + m2 switching dc–dc converter with leading-edge modulation is
(6)
Equation (6) gives the unified control law of DAC controlled shown in Fig. 3, where the transistor switch S1 is turned off
switching dc–dc converter with trailing-edge modulation, which at the beginning of each switching cycle, i.e., turned on at t =
is expressed as the function of the slopes m1 and m2 . By using (n − 1)Ts , and turned on after time interval d
n −1 Ts , i.e., turned
the expressions for m1 and m2 from (1), the corresponding on at t = (n − 1)Ts + d
n −1 Ts . The switch S1 will remain on
control law for the buck, boost, and buck–boost converters, until the end of the present switching cycle.
respectively, can be obtained. For the leading-edge modulation, the first peak current is (n),
In steady state, when a perturbation îL (n − 1) is injected at the valley current ivalley (n), and the last peak current is (n + 1)
the beginning of the (n − 1)th switching cycle by referring to will be taken to calculate the average inductor current of the nth
Fig. 2, we have switching cycle. From Fig. 3, we have

Ic = Is + m1 DTs /2 (7a) is (n) = is (n − 1) − m2 d
n −1 Ts + m1 dn −1 Ts (11a)

is (n) = Is + îL (n) (7b) ivalley (n) = is (n) − m2 d
n Ts (11b)

is (n + 1) = Is + îL (n + 1) (7c) is (n + 1) = is (n) − m2 d
n Ts + m1 d n T s . (11c)

ZHOU AND XU: DIGITAL AVERAGE CURRENT CONTROLLED SWITCHING DC–DC CONVERTERS WITH SINGLE-EDGE MODULATION 789

Similarly, by using FPM algorithm, the average inductor cur-

rent of the nth switching cycle can be obtained as
is (n) + 2ivalley (n) + is (n + 1)
iavg (n) = = ic . (12)
4
From (11) and (12), the predicted duty cycle can be obtained
as
4[ic − is (n − 1)] 4(m1 + m2 ) 7m2
dn = − dn −1 + .
(m1 + 3m2 )Ts m1 + 3m2 m1 + 3m2
(13)
Equation (13) gives the unified control law of DAC controlled
switching dc–dc converter with leading-edge modulation.
By referring to Fig. 3 in steady state, we have Fig. 4. Inductor current waveforms of DAC with trailing-edge modulation by
using DSC.
Ic = Is − m2 (1 − D)Ts /2 (14)

where Is is the peak current in steady state.

When the current perturbation îL (n − 1) is injected at the
beginning of the (n − 1)th switching cycle in the same way, we
have
is (n) + 2[is (n) − m2 d
n Ts] + [is (n) − m2 d
n Ts + m1 dn Ts]
Ic = .
4
(15)
From (7b), (7c), (14), and (15), the predicted duty cycle can
be obtained as
4îL (n)
dn = D − . (16)
(m1 + 3m2 )Ts
From (7b), (7c), (11c), and (16), the relation between Fig. 5. Inductor current waveforms of DAC with trailing-edge modulation by
îL (n + 1) and îL (n) can be further deduced as using DRC.

îL (n + 1) 3m1 + m2 3 − 2D
=− =− . (17)
îL (n) m1 + 3m2 1 + 2D
It is obvious that when D < 0.5, we have |−(3 − 2D)/(1 +
2D)| > 1, which means that DAC with leading-edge modulation
will lead to subharmonic oscillation when duty ratio is lower
than 0.5.
III. INAPPROPRIATE OF DSC AND DRC FOR THE ELIMINATION
OF SUBHARMONIC OSCILLATION OF DAC
DSC and DRC of the ac component of duty ratio were pro-
posed to eliminate the subharmonic oscillation of DPV con-
trolled buck converter with different modulations in [24]. Based
on a periodic compensating ramp in [9], digital current-mode
control algorithms similar to slope compensation technique
in [24] was proposed and DAC control with dual-edge modula-
tion method is investigated. The DAC control with single-edge
modulation proposed in this paper is based on system informa-
tion, such as converter topology, the input and output voltages.
Therefore, the control laws proposed in [9] are quite different
from control laws proposed in this paper. In the following, the
investigation on whether DSC and DRC can be used to elimi-
nate the subharmonic oscillation of DAC controlled switching
dc–dc converters with single-edge modulation or not will be
performed.
A. DSC Method
Fig. 4 shows the inductor current waveforms of DAC con-
trolled switching dc–dc converter with trailing-edge modulation
by using DSC. By comparing Fig. 4 with Fig. 2, it is known that
the slope −mc is added on ic 1 , where ic 1 is the new control ob-
jective after a slope is added and it satisfies ic 1 = ic + mc Ts /2,
where ic is the same as that of Fig. 2.
The perturbation îL (n + 1) at the beginning of the (n + 1)th
switching cycle (or at the end of the nth switching cycle) remains
as constant and is the same as that of Fig. 2 because the value
of ic 1 does not affect the duty ratio dn of the nth switching
cycle. Therefore, it is easy to know that DSC cannot eliminate
the subharmonic oscillation of DAC controlled buck converter
with trailing-edge modulation.
B. DRC Method
The key points of DRC of DPV control are to make the peak
output voltage equal to control objective and make the converter
recover back to steady state rapidly after perturbation [24]. In
this way, the perturbation will not be magnified and subharmonic
oscillation will not exist.
Fig. 5 shows the inductor current waveforms of DAC con-
trolled switching dc–dc converter with trailing-edge modula-
tion by using DRC, where the solid line corresponds to the
790 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 3, MARCH 2010

In Figs. 6 and 7, the slope −mc is constant and the slope mx

is variable. By referring to Fig. 7, we have
hn = mc dn Ts = mx (1 − dn )Ts (18a)
S∆ ,n = Ts hn /2 (18b)
i∆ ,avg(n ) = S∆ ,n /Ts (18c)
where hn , S∆ ,n , and i∆ ,avg(n ) are the height, the area, and the
average inductor current, respectively, of the DTC waveform
used in the nth switching cycle.
From (18), we can further have
i∆ ,avg(n ) = mc dn Ts /2. (19)
Fig. 6. DAC with trailing-edge modulation by using DTC.
By referring to Fig. 6, in steady state, we have
Ic − mc DTs /2 = Is + m1 DTs /2 (20)
where Is is the valley current in steady state.
When the perturbation is injected at the beginning of the
(n − 1)th switching cycle, to make the average inductor current
of the nth switching cycle equal to Ic − i∆ ,avg(n ) by using FPM
Fig. 7. Triangle of trailing-edge modulation with DTC. algorithm, the following equation can be obtained:
is (n) + 2[is (n) + m1 dn Ts ]
Ic − i∆ ,avg(n ) =
steady-state operation, while the dashed-dotted line shows the 4
inductor current with a perturbation îL (n − 1) injected at the is (n) + m1 dn Ts − m2 d
n Ts
beginning of the (n − 1)th switching cycle. + . (21)
4
After using DRC, it is shown that the converter can rapidly
recover back to steady state after perturbation. However, in this From (19)–(21), the ac small signal component of the duty
case, the average inductor current does not equal control ob- ratio can be given as
jective ic because there exists a triangle, whose area S∆ will 4îL (n)
make the average inductor current of the nth switching cycle d̂ = dn − D = − . (22)
(3m1 + m2 + 2mc )Ts
larger than ic . It is thus known that DRC also cannot eliminate
the subharmonic oscillation of DAC controlled switching dc–dc From (2c), (7b), (7c), and (22), the relation between îL (n + 1)
converter with trailing-edge modulation. and îL (n) can be deduced as
In the same way as the discussion given earlier, it is also con-
cluded that both DSC and DRC cannot eliminate the subhar- îL (n + 1) 2mc − m1 − 3m2
= . (23)
monic oscillation of DAC controlled switching dc–dc converter îL (n) 3m1 + m2 + 2mc
with leading-edge modulation. As both DSC and DRC cannot To eliminate the subharmonic oscillation, the following rela-
eliminate the subharmonic oscillation of DAC controlled switch- tion must be satisfied:
ing dc–dc converter with single-edge modulation (trailing-edge
m2 − m 1
and leading-edge modulations), thus, another way to eliminate mc > . (24)
2
the subharmonic oscillation of DAC controlled switching dc–dc
converter with single-edge modulation is needed. Therefore, subharmonic oscillation of DAC controlled
switching dc–dc converter with trailing-edge modulation when
IV. DTC FOR THE ELIMINATION OF duty ratio is greater than 0.5 can be eliminated if mc satisfies
SUBHARMONIC OSCILLATION (24).
From (2a), (21), and (22), by substituting ic for Ic in (21), the
To eliminate the subharmonic oscillation of DAC controlled corresponding control law can be given as
switching dc–dc converters with single-edge modulation, a new
method called DTC is proposed and studied in this section. 4[ic − is (n − 1)] 4(m1 + m2 )dn −1
dn = −
(3m1 + m2 + 2mc )Ts 3m1 + m2 + 2mc
A. Trailing-Edge Modulation With DTC 5m2
+ . (25)
Fig. 6 shows the inductor current waveforms of DAC con- 3m1 + m2 + 2mc
trolled switching dc–dc converter with trailing-edge modulation
B. Leading-Edge Modulation With DTC
by using DTC. The DTC waveform for trailing-edge modula-
tion is shown in Fig. 7. By comparing Fig. 6 with Fig. 2, it is Fig. 8 shows the inductor current waveforms of DAC con-
known that the slope −mc and mx are added on ic . trolled switching dc–dc converter with leading-edge modulation
ZHOU AND XU: DIGITAL AVERAGE CURRENT CONTROLLED SWITCHING DC–DC CONVERTERS WITH SINGLE-EDGE MODULATION
Fig. 8. Leading-edge modulation with DTC.
Fig. 9. Triangle of leading-edge modulation with DTC.
by using DTC. The DTC waveform for leading-edge modula-
tion is shown in Fig. 9. In Fig. 8, it is known that the slope mc
and −mx are added on ic , where the slope mc is constant and
the slope −mx is variable.
By referring to Fig. 8, we have
hn = mc (1 − dn )Ts = mx dn Ts .
From (18b), (18c), and (26), we can further have
i∆ ,avg(n ) = mc (1 − dn )Ts /2.
By referring to Fig. 9, in steady state, we have
Ic + mc D
Ts /2 = Is − m2 D
Ts /2
where Is is the peak current in steady state.
When the perturbation is injected at the beginning of the
(n − 1)th switching cycle, to make the average inductor current
of the nth switching cycle equal to Ic + i∆ ,avg(n ) by using FPM
algorithm, we have
is (n) + 2[is (n) − m2 d
n Ts ]
Ic + i∆ ,avg(n ) =
4 been realized by using a single field programmable gate array
is (n) − m2 d
n Ts + m1 dn Ts
+ .
4
In the same way, the relation between îL (n + 1) and îL (n)
can be deduced as
îL (n + 1) 2mc − 3m1 − m2
= .
îL (n) m1 + 3m2 + 2mc
To eliminate the subharmonic oscillation, the following rela-
tion must be satisfied:
m1 − m 2
mc > . (31)
2
791
Fig. 10. Experiment measured steady-state waveforms when D < 0.5.
(a) DAC control with trailing-edge modulation. (b) DPC control with trailing-
edge modulation.
Therefore, subharmonic oscillation of DAC controlled
switching dc–dc converter with leading-edge modulation when
duty ratio is smaller than 0.5 can be eliminated if mc satisfies
(31).
In the same way, the corresponding control law can be given
as
4[ic − is (n − 1)] 4(m1 + m2 )dn −1
dn = −
(m1 + 3m2 + 2mc )Ts m1 + 3m2 + 2mc
7m2
+ . (32)
m1 + 3m2 + 2mc
Based upon earlier discussion, it is known that by applying
DTC, the subharmonic oscillation of DAC controlled switching
dc–dc converter with trailing-edge and leading-edge modula-
tions can be eliminated if (24) and (31) are satisfied. Equations
(26) (25) and (32) are the corresponding control algorithm of DAC
with trailing-edge and leading-edge modulations by using DTC,
respectively. DTC method needs only to update the control law
(27) after DTC is adopted. It is easy to realize and does not need
extra compensation circuit.
(28) V. EXPERIMENTAL RESULTS
To verify the analysis results given earlier and to illustrate the
effect of DTC on the elimination of subharmonic oscillation, the
experimental studies of the buck converter are performed in the
following two cases. Case I: D < 0.5: vo = 1.5 V, R = 1.5 Ω,
and case II: D > 0.5: vo = 3 V, R = 3 Ω, with the same circuit
parameters vg = 5 V, L = 20 µH, C = 1420 µF, Re = 0.03 Ω,
and Ts = 20 µs. All the control laws proposed in this paper have
(FPGA) XC2S100 from Xilinx, Inc. A 9-bit ADC and 10-bit
(29) DPWM are used in the FPGA-based experimental system.
For the buck converter, the slopes of inductor current can be
obtained as m1 = 1.75 × 105 , m2 = 7.5 × 104 in case I and
m1 = 1 × 105 , m2 = 1.5 × 105 in case II, respectively. To verify
the precision of the average inductor current obtained by using
(30) FPM algorithm, the inductor current waveforms of digital peak
current (DPC) in [1] and DAC controlled buck converter with
trailing-edge modulation proposed in this paper are compared.
Fig. 10 shows experiment measured steady-state waveforms
of DPC and DAC controlled buck converter with trailing-edge
modulation when D < 0.5. In Fig. 10, the inductor current
792
Fig. 11. Experiment measured steady-state waveforms of DAC controlled
buck converter with leading-edge modulation when D < 0.5. (a) Without DTC.
(b) With DTC.
Fig. 12. Experiment measured steady-state waveforms of DAC controlled
buck converter with trailing-edge modulation when D > 0.5. (a) Without DTC.
(b) With DTC.
waveforms of DAC and DPC control are almost the same, which
means that the precision of the average inductor current obtained
by using FPM algorithm is appropriate.
To satisfy (24) for the elimination of subharmonic oscillation
of DAC with trailing-edge modulation, we select mc = 1 × 105
in case II, and to satisfy (31) for the elimination of subharmonic
oscillation of DAC with leading-edge modulation, we select
mc = 1.5 × 105 in case I. Figs. 11 and 12 show experiment mea-
sured steady-state waveforms of DAC controlled buck converter
with leading-edge modulation when D < 0.5 and trailing-edge
modulation when D > 0.5, respectively.
From Figs. 11(a) and 12(a), it is shown that subharmonic
oscillations exist in DAC controlled buck converter with both
leading-edge and trailing-edge modulations. However, by using
DTC, the subharmonic oscillations can be eliminated as shown
in Figs. 11(b) and 12(b), respectively. After using DTC, it is
shown that the inductor current waveforms of DAC with leading-
edge modulation when D < 0.5 and DAC with trailing-edge
modulation when D > 0.5 are stable.
Fig. 13 shows experiment measured transient waveforms of
DAC controlled buck converter with leading-edge modulation
by using DTC when D < 0.5. From Fig. 13, it is shown that the
inductor current and output voltage waveforms are stable under
startup and load variation, which further verifies the appropriate
precision of the proposed FPM algorithm and the validity of the
proposed DTC method to keep the DAC controlled converter
stable.
IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 25, NO. 3, MARCH 2010
Fig. 13. Experiment measured transient waveforms of DAC controlled buck
converter with leading-edge modulation by using DTC when D < 0.5:
(a) startup and (b) load variation.
VI. CONCLUSION
In this paper, DAC control of switching dc–dc converters with
single-edge modulation (trailing-edge and leading-edge modu-
lation) has been studied. Based on the characteristics of these
two single-edge modulations, a new algorithm, called the FPM
algorithm, was proposed to calculate the average inductor cur-
rent with minimum calculation time and appropriate precision.
The control algorithms of DAC with trailing-edge and leading-
edge modulations were derived by using FPM algorithm, and
their stabilities were also studied.
In this paper, it was shown that DAC with leading-edge mod-
ulation when D < 0.5 and DAC with trailing-edge modulation
when D > 0.5 have instability problem (subharmonic oscilla-
tion). It has also illustrated that both DSC and DRC cannot elim-
inate the subharmonic oscillations in DAC controlled switching
dc–dc converters with single-edge modulation. A new method
called DTC was proposed and studied to eliminate its subhar-
monic oscillation. It has been demonstrated that DTC can effi-
ciently eliminate the subharmonic oscillation of DAC controlled
switching dc–dc converters with single-edge modulation, which
is also verified by the experimental results.
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Guohua Zhou received the B.S. degree in electronic
and information engineering and the M.S. degree in
electrical engineering from Southwest Jiaotong Uni-
versity, Chengdu, China, in 2005 and 2008, respec-
tively, where he is currently working toward the Ph.D.
degree in the School of Electrical Engineering.
His current research interests include analog and
digital control techniques, modulation methods of
switching-mode power supplies, modeling, simula-
tion, and analysis of dynamical behavior of switching
dc–dc converters.
Jianping Xu received the B.S. and Ph.D. degrees in
electronic engineering from the University of Elec-
tronics Science and Technology of China, Chengdu,
China, in 1984 and 1989, respectively.
Since 1989, he has been with the School of
Electrical Engineering, Southwest Jiaotong Univer-
sity, Chengdu, where he has been a Professor, since
1995. From Nov. 1991 to Feb. 1993, he was en-
gaged as a Visiting Research Fellow with the Depart-
ment of Electrical Engineering, University of Federal
Defense Munich, Munich, Germany. From February
1993 to July 1994, he was engaged as a Visiting Scholar with the Department of
Electrical Engineering and Computer Science, University of Illinois, Chicago.
His current research interests include modeling, analysis, and control of power
electronic systems.