Data Converters

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 A/D and D/A conversions in sensor systems

Learning Objectives:
Here, you should develop an understanding of:

➢ Sampling concepts, criteria on the sampling rate, and limitations

➢ Principles of D/A and A/D converters, limitations, and need of signal
conditioning to overcome those limitations

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 Data Acquisition System

Analog Digital
Transducer
Post
Processing

Signal
Conditioning

Gain Decimation
and and
Filtering Digital filtering
A/D
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A. Sampling Concepts
Analog and discrete representations of a dynamic signal: Fig. 7.1

Fig. 7.1

The two signals look quite different, BUT the important info.: amplitude and
frequency can be conveyed by the discrete series providing certain
conditioning on the sampling process.
Need to sample → store less data → save memory and processing time.
The Discrete Fourier Transform (DFT) allows to reconstruct the dynamic
signal from its discrete series via the Inverse Fourier Transform (out of scope).
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Sampling Concepts

Fig. 7.2

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Sampling Concepts

Sample Rate: frequency ambiguity

The Sampling Theorem: To reconstruct the frequency content of
a measured signal accurately, the sample rate must be more
than twice the highest frequency contained in the measured
signal.
δt: sampling rate
1
fs  2 fm That is, t  fm: maximum frequency in
2 fm
the measured signal
Then, the frequencies defined by the DFT provide an accurate
representation of the original signal frequencies
What if the Sampling Theorem is Not met like in Fig 7.2 (d)??

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Sampling Concepts

Alias Frequencies
If fs < 2fm , the higher frequency content of the analog signal will
appear in the place of a lower frequency in the resulting discrete
series. This is shown in Fig. 7. 2. (d): the 10-Hz signal is observed to
take on the false identity of a 2-Hz signal, called an alias frequency

→ A misinterpretation of the frequency content of the original signal

results.

The alias phenomenon is an inherent result of the discrete sampling

process.

→ To avoid aliasing, simply stick to the sampling theorem.

→ In general, what alias frequencies Im getting NOT meeting the

sampling Theorem??? → next slide: Nyquist Frequency
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Sampling Concepts

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 Sampling Concepts
Alias Frequencies…
fs 1
For a given sampling frequency fs, the Nyquist frequency f N = =
2 2t
represents a folding point for the aliasing phenomenon as shown in Fig. 7.3
The Nyquist frequency: the maximum frequency that can be represented in
a resulting discrete series, i.e. sampled correctly.
Assume fm > fN → aliases →

EXAMPLE 7.1
A 10-Hz sine wave is sampled at 12 Hz. Compute the maximum
frequency that can be represented in the resulting discrete signal.
Compute the alias frequency.
KNOWN: f = fm = 10 Hz, fs = 12 Hz

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Sampling Concepts
EXAMPLE 7.2
A complex periodic signal has the form
y (t ) = A1 sin 2 (25)t + A2 sin 2 (75)t + A3 sin 2 (125)t

If the signal is sampled at 100 Hz, find the frequency content of

the resulting discrete signals.

SOLUTION
fa1 = fa2 = 25 Hz → the 75- and 125-Hz components:
completely indistinguishable from the 25-Hz signal.
Example 7.2 → the potential of signal misinterpretation via
improper sampling.
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Sampling Concepts

To sample unknown signals and avoid the alias phenomenon:

1) Unknown signal
• Sample the input at increasing sample rates by fixing the total
sample time, and examine the discrete values for each signal.
Look for changes in the waveform shape (e.g Fig. 7.2)
• Compute the amplitude spectrum for each signal and compare
the resulting frequency content.
• Retain that frequency fs above which the computed spectrum is
invariable.

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Sampling Concepts

2) Known frequency of interest: If the frequency range of

interest is limited to a maximum frequency fm, the signal
should be filtered at and above this frequency prior to
sampling. Then select fs >2fm (Sampling Theorem).

Of course, that filter (i.e. antialias analog filter) has to be

set at the Nyquist frequency (filter cut-off
frequency=fN=fs/2).

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Sampling Concepts

Amplitude Ambiguity

The construction of a measured waveform from a discrete signal is controlled by

the sampling rate and the DFT resolution, δf.
1 f , N: data number in DFT equation
f = = s
N t N
δf is the minimum frequency that can be reconstructed faithfully.
The freq. Resolution → plays a crucial role in the reconstruction of signal
amplitudes
When Nδt is not an integer of the period of the input signal ------- the DFT
cannot represent exactly the spectral amplitude of the sampled continuous signal.
In summary:
By adherence to the sampling theorem, one controls the frequency content of both
the measured discrete signal and the resulting DFT spectrum. 13
Sampling Concepts

Selecting Sample Rate and Data Number

For an exact discrete representation in both frequency and

amplitude of any periodic, analog waveform, both the number
(N) of data points and the sampling rate should meet:
fs 1 1 fs
fN = = f = =
2 2t N t N

The first eq. sets the minimum sampling rate fs and the second
eq. sets the total sampling time, Nδt from which the data
number, N is estimated.

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 Sampling Concepts

Practical Selection of Sample Rate and Data Number

In practice set:
• fs = 5fm
• Nδt → large
• Use an antialias filter → no freq. above a maximum desired
freq. is encountered.
Still:
The maximum sample rate → limited by the data acquisition system
The maximum data number → limited by the memory size available

EXAMPLE
We want to sample a signal whose frequency is in the range 2 – 200 Hz. Determine
appropriate sampling frequency and the number of samples to be taken in order to
reconstruct the signal faithfully using the DFT-IFT.
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B. Transmitting Digital Numbers: High & Low Signals
Binary numbers: formed
via a combination of HIGH
and LOW voltages through
a parallel grouping of
switches → Fig. 7.5

Communication Fig. 7.5

internal to a digital
device → parallel
Communication
between digital
devices → parallel or
serial
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C. Voltage Measurements
Digital-to-Analog Converter (D/A)

Digital measurement devices → need interfaces to connect them

to the physical world, which is analog → D/A, A/D → major
components of a digital voltmeter and a data acquisition system

A D/A → converts a digital binary word (in a register) into an

analog voltage → Fig. 7.6 (next page)

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 Digital-to-Analog Converter (D/A)

2
cm
I = E ref m −1
cm=1
m =1 R or 0
E0 = IRr
Fig. 7.6
X It’s like the D/A
E0 = M compares the magnitude
2 of the actual binary nbre
X in the register to the
largest possible nbre 2M

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Digital-to-Analog Converter (D/A)

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Digital-to-Analog Converter (D/A)

The D/A has digital & analog specifications:

1. Analog specifications:
• EFSR: Full-scale analog voltage range.
Typical values: 0-10 V, ±5 V
2. Digital specifications:
• M: Number of bits in the D/A register.
Typical values: 8 (DAC830), 12, 16, 18 bits

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 Analog-to-Digital Converter (A/D)
An A/D → converts an analog voltage into a binary number →
through: quantization

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Analog-to-Digital Converter (A/D)
An A/D has specifications
• EFSR: = 10V → unipolar: 0-10V, bipolar: ±5 V
• M: it can output a 2M different binary numbers
M=8 → 256 binary numbers.
A/D selection criteria:
• Resolution
• Voltage range
• Conversion speed

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Analog-to-Digital Converter (A/D)

Primary sources of errors:

1. Resolution and associated quantization error
2. Saturation error
3. Conversion error

Resolution
Is the smallest voltage increment that causes a bit change
at the output:
EFSR EFSR
Q= M or Q= M
2 2 −1
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Analog-to-Digital Converter (A/D)

Quantization Error
Fig. 7.7: 0-4V, 2-bit A/D
Resolution = 1 V → limited → errors:
0.0 & 0.9 V → 00
Fig. 7.7
→ Yet: 1.1 V → 01
→ These errors, eQ: like a
noise on the digital signal
Two schemes of eQ :
1. eQ = Q, above input voltage Ei

2. eQ = ±0.5Q, around Ei
In both cases: error span = 1 LSB = Q
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Analog-to-Digital Converter (A/D)

Sometimes: A/D resolution is specified in terms of SNR:

Signal power E2 R
SNR = = 2
Power resolvable by quantization E R 2 M

SNR (dB) = 20 log 2 M

Table 7.2 gives the effect of Table 7.2

bit number on the resolution
and SNR

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Analog-to-Digital Converter (A/D)

Saturation Error

If the input exceeds the A/D limits (out of range) →

The output will no longer increase ➔ saturation
Saturation error = limit – value equiv to the digital output assigner

Example: See Fig. 7.7; input 5V → 11

→ saturation error = 5 – 4 V = 1 V
Avoid saturation error ➔ input signals within the A/D range
➔ may require analog signal conditioning
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Analog-to-Digital Converter (A/D)

Conversion Error
As for any device, the A/D conversion error can be delineated into
errors such as:
➢ Hysteresis
➢ Linearity
➢ Sensitivity
➢ Zero
➢ Repeatability
➢ Thermal drift

A/D settling time, signal noise during analog sampling, temperature

effects, excitation power fluctuations ➔ contribute to the conversion
error 27
Analog-to-Digital Converter (A/D)

Sample Rate
Each A/D converter has a maximum sample rate typically from
1kHz – 100 MHz → Effect of sampling rate on the accuracy of
recorded signal has been discussed…

Remember ……. Stick to the sampling Theorem… -☺

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Signal Conditioning for A/D Conversion

Conditioning is often required

Most importantly:
• Prevent aliasing: use of LP or anti-aliasing filter (fc = fs/2=fN)
• Minimize quantization errors: amplify the signal to span the FSR
watch out saturation!!!
• Prevent saturation errors: care is required.

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 Analog-to-Digital Converter (A/D)

EXAMPLE 7.4

Compute the relative quantization error eQ/Ei in the quantization

of a 100-mV and a 1-V analog signal by using an 8-bit and 12-bit
A/D converter, both having a full-scale range 0-10 V.

KNOWN: Ei = 100 mV and 1 V, M = 8 and 12, EFSR = 0 – 10 V

FIND: eQ/Ei, where eQ is the quantization error.

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 Analog-to-Digital Converter (A/D)

SOLUTION
E 10 E FSR 10
Q8 = FSR = = 39mV Q12 = 12 = = 2.4mV
2 8
256 2 4096

Assume that the A/D is designed so that the absolute

quantization error is: ±0.5Q ➔ eQ/Ei is tabulated as follows
Ei M eQ 100x eQ/Ei
100 mV 8 ±19.5 mV 19.5 %
(high)
100 mV 12 ±1.2 mV 1.2 %
1V 8 ±19.5 mV 1.95 %
1V 12 ±1.2 mV 0.12 %
(low) 31
 Analog-to-Digital Converter (A/D)
EXAMPLE 7.5
The A/D converter with the following specifications is to be used
in an environment where its temperature may change by ± 10ºC.
Estimate the contribution of conversion and quantization errors to
the uncertainty in the digital representation of an analog voltage
by the converter.

KNOWN: EFSR = 0–10 V, M= 12 bits, Linearity ± 3 bits,

temperature drift = 1 bit/ 5C

FIND: (u c )E = eQ2 + eC2 eC: the conversion error

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 Analog-to-Digital Converter (A/D)

SOLUTION
The instrument (A/D) uncertainty, uC, → a combination of
uncertainty caused by quantization, eQ, and by conversion, eC:
(u c )E = eQ2 + eC2

For a 12 bit A/D → eQ = ±0.5Q = ±1.2 mV

eC is affected by two effects:

• linearity error e1 = ± 3 bits x Q = 3x2.4 mV = ± 7.2 mV
• temp. error = e2 = (1bit/5C) x 10C X 2.4 mV = ± 4.8 mV

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 Analog-to-Digital Converter (A/D)

An estimate of ec

ec =  e12 + e22 =  (7.2mV ) 2 + (4.8mV ) 2 = 8.6mV

The total error is:

(u c )E =  (1.2mV ) 2 + (8.6mV ) 2 = 8.7 mV

Note: the conversion errors dominate the uncertainty.

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Analog-to-Digital Converter (A/D)
A/D realization: Successive Approximation Converters

There are several

approaches for the A/D
conversion. The most
common: successive
approximation and Fig. 7.8
ramp converters.

The successive
approximation (most
common) → uses trial-
and-error approach →
Fig. 7.8
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Analog-to-Digital Converter (A/D)
A/D realization: Successive Approximation Converters
The conversion sequence is as depicted in Fig. 7.9 for Ei = 10.1V,
and using an 0-15 V, 4-bit successive approx. A/D

Fig. 7.9

The successive approximation method is used → when

conversion speed @ reasonable cost is important.
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 Analog-to-Digital Converter (A/D)
A/D realization: Successive Approximation Converters
The conversion → requires M steps = nbre of bits in the A/D register
Each step is triggered by one CLOCK pulse → in 1 us
For a 12-bit A/D operating with a typical 1 MHz clock → Requires a maximum
time of 12 us per conversion.

Tradeoff: increasing the nbre of bits to lower the quantization error and the
resulting increase in conversion time.

Sources of conversion error: D/A accuracy in Fig. 7.8

Noise → weakness of this type of converter
This type of converters ➔ requires the voltage remains constant during the
conversion process ➔ a Sample and Hold Circuit (SHC) seen before is used
ahead of the converter ➔ SHC also minimizes noise during conversion.
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 Analog-to-Digital Converter (A/D)
A/D realization: Ramp Converters
High accuracy–low level (< 1 mV)
The comparator compares the
reference ramp and input voltages
→ equal: the flip-flop stops the
output counter/register
The reference voltage is increased
in set time steps (= Q),
synchronized with the counter
which integrates time steps and
increases the register value at each
time step.
Improve accuracy ➔ Dual-ramp
A/D
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Analog-to-Digital Converter (A/D)

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Analog-to-Digital Converter (A/D)

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 Analog-to-Digital Converter (A/D)
A/D realization: Parallel Converters
The fastest → flash converter
Common in digital oscilloscopes and
spectral analyzers
M-bit A/D → uses 2M-1 comparators
Uses resistor ladder
There are 2M combinations→ table

A 2-bit A/D
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 Analog-to-Digital Converter (A/D)
Digital Voltmeters
EXAMPLE 7.6
A 0-10 V, 3-digit digital voltmeter is built around a 10-bit, single-ramp
A/D converter. A 100 kHz clock is used. An input voltage of 6.372 V is
applied. What should be the digital voltmeter output value? How long
will the conversion process take?

SOLUTION
E 10
Q10 = FSR
10
= = 9.77 mV ➔ 9.77 mV/step
2 1024
Nbre of steps required = Ei/ 9.77 mV/step=6.372/0.00977=653 steps ➔
Eo = 9.77mV/step x 653 steps = 6.3769 V = 6.38 V(3 digit A/D)

Conversion time = 653 steps x 10us/step = 6350 us.

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 D. Data-Acquisition Systems (DAS)

Measurement System

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E. Data-Acquisition System Components
Data Acquisition System

Analog Digital
Transducer
Post
Processing

Signal
Conditioning

Gain Decimation
and and
Filtering Digital filtering
A/D
44