KLS Vishwanathrao Deshpande Institute of Technology, Haliyal - 581 329

Doc. No.: VDIT/ACAD/AR/09 Rev.No.:01

Page 1 Rev. Dt: 25/03/2021
2nd Assignment
AY: 2023-24 (Odd)
Department: Electronics & Communication Engineering Semester / Division: 3rd / A & B
Subject with Sub. Code: Computer Organization and Architecture (BEC306C)
Faculty Name: Prof. Vijayalaxmi Kalal & Prof. Raghavendra N.

Last Date for submission: 14/02/2024

Q.
Question CO PO BTL
No.
1 Write a program to read a line from the keyboard and display it 3 1,2 L2
Explain in detail, the situations where a number of devices capable of
2 3 1,2 L2
initiating interrupts are connected to processor. How to resolve the problems
Define Interrupt. Explain Daisy chain and Priority Structure methods of
3 3 1,2 L2
handling interrupts from multiple devices
With a neat diagram, explain DMA Controller Operation with its Interface
4 3 1,2 L2
registers.
5 Write a note on classification of memory structure 4 1,2 L2

6 Define Cache Memory. Explain various types with neat diagrams 4 1,2 L2
Define the following terms: (a) Memory Latency (b) Memory Bandwidth (c)
7 4 1,2 L2
Memory Access Time (d) Memory Cycle Time
With a neat diagram, explain internal organization of 2M x 8 dynamic
8 4 1,2 L2
memory chip
9 Explain Hardwired Control Unit Organization 5 1,2 L2

10 What are the actions required to execute a Complete Instruction Add(R3), R1 5 1,2 L2