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Peak detector
Peak detector circuits are used to determine the peak (maximum) value of an input signal. It
stores the peak value of input voltages for infinite time duration until it comes to reset
condition. The peak detector circuit utilizes its property of following the highest value of an
input signal and storing it.

In positive half cycle, output of op-amp is positive so diode D is forward biased, capacitor
charges to peak value of input signal.
In negative half cycle, when input decreases diode D is reversed biased and capacitor is
isolated and holds the charge of previous half cycle.
 Sample and Hold Circuit

The Sample and Hold circuit is an electronic circuit which creates the samples of input voltage and after
that, it holds these samples for the definite time. The time during which sample and hold circuit generates
the sample of the input signal is called sampling time. Similarly, the time duration of the circuit during
which it holds the sampled value is called holding time.
Circuit diagram: A1 and A2 are op amp based unity gain amplifier .Transistor is used as
switch.vs is the control voltage applied at gate terminal that will make transistor on or off. When
the switch is closed sampling process will come into the picture and when the switch is opened holding
effect will be there.Capacitor is the heart of sample and hold circuit because the capacitor charges to peak
value when the switch is closed and hold the sampled value when the switch is opened.
When the Transistor is turned ON , the capacitor starts charging to the level of the input analog voltage
.When the Transistor is turned OFF , the capacitor is isolated from the input signal and hold voltage at
the value of the input voltage.

VS

Applications:

 It is used in analog to digital conversion by sampling the input voltage and holding it till the conversion is
complete.
 The S/H are used in multichannel ADC where the need of synchronization is necessary. The S/H circuit
samples all the signals from different channels at the same time.
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