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06 ControlUnitDesign
06 ControlUnitDesign
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Basic Concept
• Any digital circuit module consists of two components:
a) Data Path – performs data transfer and processing opera=ons.
(Adder, mul=plier, mul=plexer, register, bus, counter, decoder, etc.)
b) Control Unit – generates control signals for the data path for sequencing of
the opera=ons.
(Basically a finite-state machine)
Control signals
Control signals
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repeat forever
// till power off or Fetch
// system failure
{
Fetch instruction Memory
Decode
Decode instruction
Execute instruction
} Execute
Fetch-Decode-Execute Cycle
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PC
Instruc=on Decoding .. Control
MAR
and Control Unit . signals
MEMORY
MDR
IR
4
Y R0
General-purpose
Select MUX R1 Registers
..
Func=on
.
ALU Carry-in
select Rn-1
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Func3on
.
• The registers, the ALU and the interconnec=ng select
ALU Carry-in
Rn-1
Kinds of Opera2ons
• Transfer of data from one register to another.
MOVE R1, R2 // R1 = R2
• Perform arithme=c or logic opera=on on data loaded into registers.
ADD R1, R2 // R1 = R1 + R2
• Fetch the content of a memory loca=on and load it into a register.
LOAD R1, LOCA // R1 = Mem[LOCA]
• Store a word of data from a register into a given memory loca=on.
STORE LOCA, R1 // Mem[LOCA] = R1
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PC
Register File
4 M
U A
X
L
U
Instruc=on Decoder
IR
Data
MDR
Memory
MAR Address
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Organiza2on of a Register
Riin
• A register is used for temporary storage of data
(parallel-in, parallel-out, etc.).
• A register Ri typically has two control signals.
• Riin : used to load the register with data from the Register Ri
bus.
• Riout : used to place the data stored in the
register on the bus.
Riout
• Input and output lines of the register Ri are
connected to the bus via controlled switches.
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Riin
Riout
Riin
Riout
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R1in
Register-Register Transfer
MOVE R1, R2 // R1 = R2 Register R1
Riin
ALU Opera2on
Ri
ADD R1, R2 // R1 = R1 + R2 Riout
Yin
• Bring the two operands (R1 and R2) to the two
inputs of the ALU. Y
4
One through Y (R1) and another (R2) directly from
internal bus. S MUX
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Internal processor
bus
MFC Memory MDR
Internal processor
bus
MFC Memory MDR
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• When the processor sends a read request, it has to wait un=l the data is read from the memory and
wriken into MDR.
• To accommodate the variability in response =me, the processor has to wait un=l it receives an indica=on
from the memory that the read opera=on has been completed.
• A control signal called Memory Func1on Complete (MFC) is used for this purpose.
• When this signal is 1, indicates that the content of the specified loca=on is read and are available on the data
line of the memory bus.
Connec&ng
• Then the data can be madeMDR totoMemory
available MDR. Bus and Internal Bus
Memory bus MDRinE MDRin
Internal processor
bus
MFC Memory MDR
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PC
Register File
Instruc*on Decoder
T3: MDRoutB , R = B, IRin
IR
Data
T4: R2outA , R3outB , SelectA, SUB, R1in , End MDR
Memory
MAR Address
16
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