154 IEEE SOLID-STATE CIRCUITS LETTERS, VOL.

3, 2020

A Low-Power 1-V Supply Dynamic Comparator

Subhash Chevella , Student Member, IEEE, Daniel O’Hare , Member, IEEE,
and Ivan O’Connell , Senior Member, IEEE

Abstract—This letter presents a low-power dynamic comparator for

ultralow power applications. The prototype is designed in a 65-nm CMOS
process with a supply voltage of 1 V and is compared against the widely
used double tail latch comparator in terms of power consumption and
input referred rms noise. The addition of cross-coupled devices to the
input differential pair prevents the comparator internal nodes from fully
discharging to ground in contrast to the conventional architecture. This
reduces the power consumption while achieving similar noise levels.
Measurements demonstrate that the proposed comparator achieves an
input referred rms noise voltage of 220 µV against 210 µV for the con-
ventional comparator with a 30% reduction in power. The proposed
circuit consumes 0.19-pJ energy per comparison.
Index Terms—Analog-to-digital converter (ADC), comparator, double-
tail latch-type comparator, latch, low-noise, low-power, SAR, StrongArm.

I. I NTRODUCTION AND P RIOR A RT

Dynamic comparators are the essential building block in many
mixed signal conditioning circuits. The widespread use of battery
powered applications demands low-power signal processing circuits,
resulting in the widespread use of dynamic comparators. StrongArm
latch-type [1], [2] dynamic comparators and its variants are widely
used owing to their negligible static power consumption. However,
because of large voltage headroom [2], [3], kick-back noise and
common-mode dependent offset [2], StrongArm latch-type compara-
tors are often replaced by double-tail latch type [3] comparators by
separating the preamplification from the latch operation. This sepa-
Fig. 1. Conventional double tail latch type [4] comparator schematic.
ration allows us to optimize the offset, noise, speed, and power of
the circuits independently.
In SAR ADCs targeted for ultralow power applications, the com-
parators play a crucial role. Typically 40%–50% of the total SAR Conventional architectures fail to do this and allow Cp to discharge
ADC energy consumption is by the comparator alone [4]–[6]. A completely to ground as shown in Fig. 2(b). This means a fixed
widely used double tail latch [4] type comparator is shown in Fig. 1. charge of Cp ∗ VDD is required at each of the nodes, intP and intN.
The timing diagram associated with this comparator is shown in Thereby, consuming the energy 2 ∗ Cp ∗ VDD 2 for every comparison.
Fig. 2. For each comparison, the preamplifier output (intP and intN) As a result of this, the preamplifier consumes almost 70%–80% of
node capacitors (Cp ) discharge completely to ground and afterward the total comparator energy. This also holds true for architectures
they have to be recharged to the supply, VDD . The time to discharge shown in [3] and [4]. Ideally this preamplifier energy consumption
the capacitors, Cp from VDD to the voltage, Vlatch determines the would reduce to VDD ∗ Cp ∗ 2 ∗ (VDD − Vlatch ).
integration time, Tint . Vlatch is the voltage at which the regenerative Recent publications have proposed techniques like bi-directional
latch triggers, i.e., low enough to turn the transistors M11 and M12 comparator [5], data-driven noise reduction [6], and dynamic bias
on to provide the conduction path for the regenerative latch. Once the preamplifier [7] to reduce the energy per conversion of the compara-
latch triggers, further reduction of the node voltages intN and intP tors. In the bi-directional comparator presented in [5], the energy per
is not going to improve the noise or conversion time but it will cost comparison is reduced to Cp ∗ VDD 2 as compared to 2 ∗ C ∗ V 2
p DD
more energy to reset these nodes to VDD . In order to save the power, for the conventional circuit. However, to achieve this, extra logic
ideally we would stop the discharge of these nodes immediately after is required to switch from a pMOS differential pair to an nMOS
the latch triggers. drawback of double latch differential pair and reset/latch enable signals. The dynamic bias
preamplifier-based comparator in [7] uses the source degeneration
Manuscript received May 13, 2020; revised July 4, 2020; accepted July capacitor to reduce the energy consumption. However, this implemen-
10, 2020. Date of publication July 15, 2020; date of current version
July 31, 2020. This article was approved by Associate Editor Pieter Harpe. tation requires extra headroom and a degenerative capacitor increases
This work was supported by the Microelectronic Circuit Centre Ireland the comparison time. The floating inverter preamplifier-based com-
through the Enterprise Ireland Technology Centres Programme under Grant parator architecture [8] uses a reservoir capacitor to reduce the energy
TC-2015-0019. (Corresponding author: Subhash Chevella.) consumption. The cost of this is larger circuit area and the need for
The authors are with the Precision Circuits, Microelectronic Circuits
Centre Ireland, Tyndall National Institute, Cork, T12 R5CP Ireland (e-mail:
a higher supply voltage.
subhash.chevella@mcci.ie). This letter presents a comparator architecture to reduce the power
Digital Object Identifier 10.1109/LSSC.2020.3009437 consumption without the use of any extra capacitors or complex logic
2573-9603 
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 CHEVELLA et al.: LOW-POWER 1-V SUPPLY DYNAMIC COMPARATOR 155

Fig. 2. Simulated timing diagram of a conventional comparator with a 5-mV

input differential voltage; VCM = 0.5 V. (a) Applied clock, (b) preamplifier
output nodes, and (c) regenerative latch output nodes.

but with a simple cross-coupled mechanism around the input differen-

tial pair. This technique prevents the comparator internal nodes from
discharging fully for small differential inputs and thus reducing the
energy consumption per each comparison.

II. P ROPOSED C IRCUIT
The proposed comparator architecture is shown in Fig. 3. It consists
of a new modified preamplifier with the addition of the cross-coupled
devices (M21 and M22) and a regenerative latch. The operational
behavior of the proposed comparator circuit is explained as follows.
During the reset phase, when the applied clock is low, the transistors
M4, M5, M6, and M7 precharge the nodes intN, intP, N1, and P1 to
VDD and the transistors M17 and M18 reset the regenerative latch
output nodes (outP and outN). As the transistor M3 is turned off,
there is no direct flow of current from the supply to ground.
During the amplification phase, when the clock is high, the nodes
intP, intN, P1, and N1 are disconnected from VDD and M3 provides
a discharge path to ground. The amplification phase can be divided
into two subphases. The equivalent circuit in the first subphase is
shown in Fig. 4(a). At the instant that amplification starts, as the
gates of M3 and M21 are tied to VDD , the node N1 quickly gets
discharged to a low voltage which is the IR drop across the switches
(M3 and M21). The node P1 behaves in a similar manner. Once the
transistors M1 and M2 start conducting and M21 and M22 operate in
the linear region (i.e., as resistors). As the voltages at nodes intP and
intN decrease, at a rate controlled by the applied input voltages, the
internal node N1 and P1 voltages will increase slowly. This behav-
ior changes the effective Vgs of the input differential pair lowering
the transconductance (gm ). For small input differential voltages, this
behavior can increase the conversion time of the comparator. Based
on the applied input differential voltage (vinP>vinN), the rate of
decrease of the node intN is faster than the node intP. As the node
intN reaches to the threshold voltage of M22, the rate of decrease
of the node intP reduces and eventually intP will become static as
transistor M22 turns off completely.
With the node intP static, the operational behavior of the circuit
changes. The equivalent circuit in this mode is as shown in Fig. 4(b).
In this subphase, the transistor M22 is fully turned off and the tran-
sistors M1 and M21 behave as a cascode current source. As the
node intP is static, the gate potential of the transistor M21 is fixed.
Fig. 3. Proposed comparator schematic with the modified preamplifier and
the regenerative latch.
Fig. 4. Modified preamplifier equivalent circuit in (a) subphase-I and
(b) subphase-II.
This forces the node intN to discharge at a reduced rate. The timing
diagram associated with this circuit is shown in Fig. 5.
With the decrease of the node (intP and intN) voltages, we can
observe that the internal node (P1 and N1) voltages increase as shown
in Fig. 5(c). This is because the ON resistance of the devices M21
and M22 increase as their gate potential (which are connected to
the output nodes) decreases. The operational timing behavior of the
proposed comparator ensures intP and intN only discharge to VD1
and VD2 as shown in Fig. 5(b). This is in contrast with the conven-
tional architecture, in which both the preamplifier output nodes will
discharge fully to ground as shown in Fig. 2(b).
For a given comparison time, the nodes intP and intN approach
the voltages VD1 and VD2 below VDD , respectively. Thus, the energy
consumption is reduced to VDD ∗ Cp ∗ (VD1 + VD2 ). Thus, the
proposed comparator improves the power efficiency without the use
of any extra capacitors or more complex logic but with a simple
cross-coupled mechanism around the input differential pair. With the

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 156 IEEE SOLID-STATE CIRCUITS LETTERS, VOL. 3, 2020

Fig. 6. Die micrograph: the inset shows the size of (a) conventional dou-
ble tail latch type comparator 24 µm×40 µm and (b) proposed comparator
25 µm×41 µm.

Fig. 5. Simulated timing diagram of a proposed comparator with a 5-mV

input differential voltage; VCM = 0.5 V. (a) Applied clock, (b) modi-
fied preamplifier output nodes, (c) modified preamplifier internal nodes, and
(d) regenerative latch output nodes.

proposed solution, area saving is substantial but a small cost of this

low area active degeneration is a small increase in the noise com- Fig. 7. Measured probability of one’s fitted with CDF for (a) proposed
pared to [7] and [8] which use passive degeneration. However, the comparator and (b) standard double-tail latch type comparator; VCM = 0.5 V.
input referred rms noise is still dominated by the input pair. This
type of dynamic comparators does not have any hysteresis as the
preamplifier and the latch outputs are reset for every clock cycle and
do not have memory. But the added cross-coupled device (M21 and
M22) mismatch also contributes to the input referred offset along
with the main input differential pair. However, the impact from the
cross-coupled devices will be much less as compared to the impact
from the input pair.

III. M EASUREMENTS
The two comparators shown in Figs. 1 and 3 were designed and
fabricated on the same die in a standard 65-nm CMOS process. In
order to have similar regeneration times, the same regenerative latch
is used in both the designs. Similarly, the sizes of the input pair M1
and M2 are kept the same in both designs, with the only change
being around the addition of the new cross-coupled devices (M21
and M22), to ensure a fair comparison. The die micrograph for both
designs is shown in Fig. 6 with the inset showing the dimensions.
The proposed circuit occupies 6% higher area than the conventional
circuit.
The input differential voltage was swept in steps of 100 µV from
−1 mV to 1 mV and 3000+ output comparisons are taken at ten
different time instances for each input value.
Then, the measured probability of 1’s are fitted to the normal cumu-
lative distribution function (CDF) to obtain the input referred rms
noise as shown in Fig. 7. From the plots, the measured input referred
rms noise voltage 220 µV of the proposed circuit can be observed
against 210 µV of the conventional comparator for a single sample.
The “x” marks in Fig. 7 indicate the spread of the probability 1’s
measured at ten different time instances. For small input differential
Fig. 8. Simulated comparator delay as a function of differential input voltages
for the conventional and the proposed comparator; VCM = 0.5 V.
values, the wider spread of these measures for the proposed circuit
is because of the extra noise generated by M21 and M22.
The parasitic extracted simulated delay with respect to the input
differential voltages of both the proposed and conventional compara-
tor circuits is shown in Fig. 8. For small input differential voltages,
the proposed circuit spends more time in the weak-inversion region
because of the less effective Vgs and reduced initial gm of the input
pair. This causes higher conversion time for the proposed circuit. The
proposed circuit could be tuned to have similar initial gm as of the
conventional circuit to improve the conversion delay.
By varying the differential input voltages, the comparator power
(including both the preamplifier and the regenerative latch) is mea-
sured at a clock rate of 25 MHz. The corresponding measured power

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 CHEVELLA et al.: LOW-POWER 1-V SUPPLY DYNAMIC COMPARATOR
TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON
Fig. 9. Measured comparator power plots as a function of differential input
voltages for the conventional and the proposed comparator; VCM = 0.5 V.
plot is shown in Fig. 9. From the measured data presented, by hav-
ing similar noise levels, a 30% reduction in the proposed comparator
power is observed versus the conventional circuit.
Table I summarizes the performance of the different comparators.
Compared to [7] and [8], the proposed comparator is implemented
with lower supply voltage of 1 V and without using any extra passive
components or any other complex logic and thus achieves less area
penalty with the modification proposed. The proposed design com-
pares favorably in terms of other performance parameters against the
current state-of-the-art, as shown in Table I.
IV. C ONCLUSION
In conclusion, the proposed comparator presented here achieves
about a 30% reduction in measured power compared to the con-
ventional comparator [4] at a similar noise levels. This is achieved
by only partially discharging the comparator internal nodes with the
use of a simple cross-coupled mechanism. This makes the presented
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157
architecture a good design choice in ultralow power applications. The
proposed circuit is also a low area solution as it does not require any
external capacitors or complex logic.
ACKNOWLEDGMENT
The authors would like to acknowledge the support of Analog
Devices, Cork.
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