K L Deemed to be University

Department of Electronics and Communication Engineering

Course Handout for II/IV Year B.Tech PROGRAM
A.Y.2017-18, Even Semester

Course Title : Computer Organization and Architecture

Course Code : 15EM2001
L-T-P Structure : 2-2-2
Credits : 4
Pre-requisite : 15EC1101
Course Coordinator : Y. Usha Devi
: Dr. Habibulla Khan , Dr.B.T.P.Madhav, Dr.P.Pardhasaradhi,
Dr.K.Kiran Kumar, M. Ajay Babu, Sanam Nagendram,
Team of Instructors G.Venkata Ganesh, S.Raja Gopal, K Anusha, P.Gopi Krishna,
M.Ramesh Kumar, PSG Aruna Sri , Ch. Sree Vardhan,
B. Murali Krishna, N. Siddaiah, N. Srinivasulu.

COURSE OBJECTIVE:
This courses aims at providing a comprehensive knowledge on the structure and behavior of
computer hardware architecture and application of the design concepts with combinational or
sequential digital systems including various peripheral devices. It culminates in realization of the
concepts with logical verification in Logisim and various case studies.

COURSE RATIONALE:

The purpose of learning this course is a set of components like Processor, Memory and Storage,
Input / Output Devices interconnected by bus in such a way as to enable the execution of a
program stored in memory. It encompasses the definition of the machine’s instruction set
architecture. The course emphasizes performance and cost analysis, instruction set design,
pipelining, memory technology, memory hierarchy, virtual memory management, and I/O
systems. Starting with the design of gate logic with combinational logic circuits to sequential logic
circuits and some complex digital systems will be carried out in this course which is essential for
design engineers in the industry.

COURSE OUTCOMES (COs):

 Blooms Taxonomy
CO No Course Outcome (CO) PO/PSO
Level (BTL)
Understand the functionality of computer, functional
units - control unit, memory unit, the arithmetic and
1 PO1, PO2 1
logic unit, design of ALU and different programming
languages.
Understand the CPU, instruction execution unit,
addressing modes and instruction set. Understand
2 the concepts of micro-operations and RTL operations PO2 2
and the concepts of main, cache and virtual memory
organizations.
Understand different types of I/O subsystems and I/O
3 PO1, PO2 2
transfer techniques.
Understand the design issues of RISC and CISC CPUs
4 PSO1 2
and the design issues of pipeline architectures.
Design and simulation of system level design lab using
5 PO6 3
Logisim tool.
COURSE OUTCOME INDICATORS:
CO Highest COI-1
No. BTL
Understand the functionality
of the Computer and its
CO-1 1 functional units. Number
System and Representation
of information.
Understand the CPU design,
Understand the Various
addressing modes, Designing
CO-2 2 of instruction set, Concepts
of Subroutine and use of
stack for handling
subroutine call and return.
Understand input/output
processing, working with
CO-3 2 video display unit and
keyboard and routine to
control them
Understand RISC and CISC
paradigm. Design issues of a
CO-4 2 RISC processor and
CO-5 3 Design and simulation of system level design lab using Logisim tool.
COI-2 COI-3
Understand the functioning Understand memory
of ALU. Hardware control unit. Concept
implementation of ALU Machine level programm
Assembly level program
and High level Programm
Understand Micro-operation Understand, analyze ma
and their specification. cache and virtual memo
Hardwired and Micro organizations
programmed control,
Concepts of semiconductor
memory, organization of
memory modules.
Understand Program Understand Secon
controlled I/O storage and type of sto
transfer ,Interrupt controlled devices, buses
I/O transfer, DMA controller Connecting I/O device
CPU and memory.
Example of an existing RISC Understand design issu
processor, Understand pipeline architec
pipelining and pipeline Instruction level paralle
hazards and advanced issues.
 SYLLABUS

Course Name: Computer Organization and Architecture Course Code: 15EM2001

Introduction to computer system and its sub modules, Number System and
Representation of information, Arithmetic and Logical operation and hardware
implementation of Arithmetic and Logic Unit, Introduction to memory Unit, control unit
and Instruction Set. Working with an ALU, Concepts of Machine level programming,
Assembly level programming and High level Programming.

Various addressing modes and designing of an Instruction set. Concepts of subroutine

and subroutine call, use of stack for handling subroutine call and return. Introduction to
CPU design, Instruction interpretation and execution, Micro-operation and their RTL
specification. Hardwired control CPU design. Micro programmed control CPU design.
Concepts of semiconductor memory, CPU-memory interaction, organization of memory
modules. Cache memory and related mapping and replacement policies. Virtual
memory.

Introduction to input/output processing, working with video display unit and keyboard
and routine to control them. Program controlled I/O transfer. Interrupt controlled I/O
transfer, DMA controller. Secondary storage and type of storage devices. Introduction to
buses and connecting I/O devices to CPU and memory.

Introduction to RISC and CISC paradigm. Design issues of a RISC processor and example
of an existing RISC processor. Introduction to pipelining and pipeline hazards, design
issues of pipeline architecture. Instruction level parallelism and advanced issues.
Text Books:
1. William Stallings, Computer Organization and Architecture: Designing for
Performance, 8/e, Pearson Education India. 2010.
Reference Books:
1. V. C. Hamacher, Z. G. Vranesic and S. G. Zaky, Computer Organization, 5/e, McGraw
Hill, 2002.
2.M.Morris Mano, Computer System Architecture, 3/e, Pearson, 2008.

Reference e-material:
1. NPTEL Computer Organization and Architecture Lecture by IIT Guwahati.

4
 COURSE DELIVERY PLAN:

Sess. C Teaching- Evaluation

COI Topic (s) Learning Component
No. O
Methods s
Introduction, Course plan and pattern
0 0 0 Chalk and
of delivery, Recap of the content given --
Talk
from the Pre- Requisite
1 1 1 Introduction to computer system and Chalk and Test-1 &
its sub modules Talk, PPT SEE
2 1 1 Number System and Representation of Chalk and Test-1 &
information Talk, PPT SEE
3 1 2 Arithmetic and logical operation, Chalk and Test-1 &
Hardware implementation of ALU Talk, PPT SEE
4 1 2 Design of ALU, Implementation issues Chalk and Test-1 &
of some operations of ALU. Talk, PPT SEE
5 1 3 Chalk and Test-1 &
Introduction to Memory unit
Talk, PPT SEE
6 1 3 Concepts of semiconductor memory, Chalk and Test-1 &
CPU-memory interaction Talk, PPT SEE
7 1 3 Chalk and Test-1 &
Control unit
Talk, PPT SEE
8 1 3 Programming Languages: Machine Chalk and Test-1 &
level, Assembly level, high level Talk, PPT SEE
9 2 1 Introduction to CPU Design, CPU Chalk and Test-1 &
system bus , internal structure of CPU Talk, PPT SEE
10 2 1 Register Organization , Processor Status Chalk and Test-1 &
Word Talk, PPT SEE
11 2 1 Concept of Program Execution, Various Chalk and Test-1 &
addressing modes Talk, PPT SEE
12 2 1 Chalk and Test-1 &
Instruction Representation
Talk, PPT SEE
Chalk and
13 2 1 Talk, Test-1 &
Designing of instruction set
Programm SEE
ing
14 2 1 Concepts of Subroutine , Use of stack Chalk and Test-1 &
for handling subroutine call and return Talk SEE
15 2 2 Understand Micro-operation and their Chalk and Test-1 &
specification Talk, PPT SEE
16 2 2 Hardwired control, Micro programmed Chalk and Test-1 &
control, Design of Control Unit Talk, PPT SEE
17 2 2 Organization of memory modules, Main Chalk and Test-1 &
memory Talk, PPT SEE
Understand, analyze the cache
18 2 3 Chalk and Test-1 &
Memory, Mapping and replacement
Talk, PPT. SEE
policies
5
19 2 3 Understand the virtual memory Chalk and Test-1 &
organization. Talk, PPT. SEE
20 3 1 Introduction to input/output Chalk and Test-2 &
processing, Talk, PPT SEE
Working with video display unit,
21 3 1 Chalk and Test-2 &
Working with keyboard and routine to
Talk, PPT SEE
control them.
22 3 2 Introduction to I/O , Program Chalk and Test-2 &
controlled I/O transfer Talk, PPT SEE
23 3 2 Chalk and Test-2 &
Interrupt controlled I/O transfer.
Talk, PPT SEE
24 3 2 Chalk and Test-2 &
DMA controlled I/O
Talk, PPT SEE
25 3 3 Secondary storage , Types of storage Chalk and Test-2 &
devices Talk, PPT SEE
Introduction to buses, Connecting I/O
26 3 3 Chalk and Test-2 &
devices to CPU, Connecting I/O devices
Talk, PPT SEE
to memory.
27 4 1 Introduction to RISC and CISC Chalk and Test-2 &
paradigm. Talk, PPT SEE
28 4 1 Design issues of a RISC processor , Chalk and Test-2 &
Example of an existing RISC processor Talk, PPT SEE
29 4 2 Chalk and Test-2 &
Introduction to pipelining
Talk, PPT SEE
Test-2 &
30 4 2 Chalk and
Pipeline hazards SEE
Talk, PPT
Test-2 &
31 4 3 Chalk and
Design issues of pipeline architecture. SEE
Talk, PPT
Test-2 &
32 4 3 Instruction level parallelism and Chalk and
advanced issues Talk, PPT SEE

SESSION PLAN:

Session – 0

At the end of the session students will be able to

1. Understand about course handout

2. Understand about course pre requisite

Teaching Learning
Time Topic BTL
Method
10 Introduction - -
6
 10 Course Handout explanation
1 PPT
10 Discussion on Prerequisite subjects - DISCUSSION
10 Basics of Pre Requisite
- DISCUSSION
5 Discussion on numbers systems
- PARTICIPATE/VERIFY
Session – 1

At the end of the session on Computer Organization and Architecture, my students will
be able to
1. Understand the basic model of computer
2. Introduction to Computer Organization and Architecture

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Introduction -
15 Basic Computer Model and different units of 1
Chalk and Talk, PPT
Computer
10 Basic Working Principle of a Computer 1 Chalk and Talk, PPT
10 The terms computer organization and 1
Chalk and Talk, PPT
architecture, attributes and examples
5 Conclusion/Summary - -
Session – 2

At the end of the session on Number Systems, my students will be able to

1. Understand the Number Systems

2. Understand the representation of numbers

Teaching Learning Active Learning

Time Topic BTL
Method Method
5 Recap on session 1 -
10 Binary Number System 1 Chalk and Talk, PPT
10 Representation of Real Numbers 1 Chalk and Talk, PPT Discussion
10 Number systems conversions and problems 1 Chalk and Talk, PPT
10 Conclusion/Summary - -
Session – 3

At the end of the session on Arithmetic and Logical operation and H/W implementation, my
students will be able to

1. Understand the ALU implementation and operation

2. Understand Logical Circuit like AND, OR, EX-OR, ALU hardware implementation.

7
 Teaching Active Learning
Time Topic BTL
Learning Method Method
05 Recap on session 2 -
10 ALU operation 1 Chalk and Talk, PPT
10 Logical circuit: AND, OR, EX-OR, 1
Chalk and Talk, PPT Quiz
Arithmetic circuit: ADDER, SUBTRACTOR
15 ALU hardware implementation 1 Chalk and Talk, PPT
05 Conclusion/Summary - -
Session – 4

At the end of the session on Implemental issue of some operations of ALU, my students
will be able to

1. Understand the design of 4- bit ALU

2. Understand Multiplication of two numbers in binary

Teaching Active Learning

Time Topic BTL
Learning Method Method
05 Recap on session 3 -
25 Design of 4-bit ALU 1 Chalk and Talk, PPT
10 Multiplication of two numbers in binary 1 Quiz and discussion
Chalk and Talk, PPT
representation.
05 Conclusion/Summary - -
Session – 5

At the end of the session on programming languages and introduction to CPU, my

students will be able to

1. Understand the memory classification

2. Understand the memory unit and organisation

Teaching Learning Active Learning

Time Topic BTL
Method Method
05 Recap on session 4 -
25 Classification of memories, memory unit 1 Chalk and Talk, PPT
Quiz
10 Memory organization 1 Chalk and Talk, PPT
05 Conclusion/Summary - -
Session – 6

At the end of the session on programming languages and introduction to CPU, my

students will be able to

1. Understand the memory classification

2. Understand the memory unit and organisation

8
 Teaching Learning Active Learning
Time Topic BTL
Method Method
05 Recap on session 5 -
25 Semiconductor memories 1 Chalk and Talk, PPT
Fish bowl
10 CPU memory interaction 1 Chalk and Talk, PPT
05 Conclusion/Summary - -
Session – 7

At the end of the session on programming languages and introduction to CPU, my

students will be able to

1. Understand Hardwired control

2. Understand micro-programmed control

Teaching Learning Active Learning

Time Topic BTL
Method Method
05 Recap on session 6 -
20 Control unit, hardwired control 1 Chalk and Talk, PPT
Discussion
15 Micro-programmed control 1 Chalk and Talk, PPT
05 Conclusion/Summary - -
Session – 8

At the end of the session on programming languages and introduction to CPU, my

students will be able to

1. Understand types of programming languages

2. Understand the tools to load program in to memory

Teaching Active Learning

Time Topic BTL
Learning Method Method
05 Recap on session 7 -
25 Different programming languages 1 Chalk and Talk, PPT
Fish bowl
10 Development tools 1 Chalk and Talk, PPT
05 Conclusion/Summary - -
Session – 09

At the end of the session on CPU design, my students will be able to

1. Understand the bus system of CPU

2. Understand the internal structure of CPU

Teaching Learning Active Learning

Time Topic BTL
Method Method
05 Recap on session 8 -
05 Introduction to CPU 1 Chalk and Talk, PPT One minute paper
9
 15 CPU Bus system 1 Chalk and Talk, PPT
15 Internal structure of CPU 1 Chalk and Talk, PPT
05 Conclusion/Summary - -
Session – 10

At the end of the session on CPU design, my students will be able to

1. Understand the register organization

2. Understand the processor status word

Teaching Active Learning

Time Topic BTL
Learning Method Method
05 Recap on session 9 -
20 Register organization, User visible, 1
Chalk and Talk, PPT
control registers Fish Bowl
15 Processor Status word 1 Chalk and Talk, PPT
05 Conclusion/Summary - -
Session – 11

At the end of the session on Concept of Program Execution, my students will be able to
1. Understand program execution and instruction cycle
2. Understand an example of processor, 8086, various addressing modes

Teaching Active
Time Topic BTL Learning Learning
Method Method
05 Recap on session 10 -
15 Basic Instruction cycle, Concept of 1
Chalk and Talk, PPT
program execution
Quiz
20 8086 architecture example, Various 1
Chalk and Talk, PPT
addressing modes
05 Conclusion/Summary - -
Session – 12

At the end of the session on Instruction Representation, my students will be able to

1. Understand Instruction Representation

2. Remember Instruction Representation

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 11 - -
35 Instruction Representation, 1
Chalk and Talk, PPT Discussion
Instruction formats
05 Conclusion/Summary - -
Session – 13
10
At the end of the session Instruction Set Design, my students will be able to

1. Understand of a instruction design issues

2. Understand Instruction Format, Operands and Types of Operations.

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 12 - -
10 Instruction Set fundamental 1 Chalk and Talk
design issues
Quiz
25 Types of Operands and Types of 1
Chalk and Talk
Operations
05 Conclusion/Summary - -
Session – 14
At the end of the session on Concepts of subroutine, my students will be able to
1. Discuss about Stack operations
2. Understand about concepts of subroutine

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 13 - -
20 Concepts of Subroutine, 1
Procedure CALL and RET Chalk and Talk, PPT
Instruction One Minute Paper
15 Stack operations , use of stack for 1
Chalk and Talk, PPT
handling subroutine
05 Conclusion/Summary - -
Session – 15
At the end of the session on Micro-operation and their RTL Specification, my students
will be able to
1. Understand micro-operations
2. Understand various types of micro-operations

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 14 - -
10 Micro-operations 1 Chalk and Talk, PPT
25 Register Transfer Operations and 1 Chalk and Talk, PPT Discussion
types of micro-operations
05 Conclusion/Summary
Session – 16
At the end of the session on Hardwired Control my students will be able to
1. Understand about Hardwired Control

11
 2. Understand about micro-programmed control and microinstruction format

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 15 - -
10 1. Hardwired Control: Control Unit 1
Chalk and Talk,PPT
Organization
15 Micro-programmed Control: 1
One Minute Paper
Basic organization of a micro-
Chalk and Talk,PPT
programmed control,
Instruction format, fields
10 Design of control unit 1 Chalk and Talk,PPT
5 Conclusion/Summary
Session – 17

At the end of the session Concepts of semiconductor memory, my students will be able
to

1. Understand The memory hierarchy and Main memory.

2. The data transfer between main memory and the CPU.

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 16 - -
10 Concept of Memory 1 Chalk and Talk,PPT
25 The memory hierarchy, 1 Fish Bowl
Semiconductor memories(Main Chalk and Talk,PPT
Memory)
05 Conclusion/Summary - -
Session – 18

At the end of the session on Analyze the cache Memory; my students will be able to

1. Understand about Operation of Cache Memory

2. Understand Mapping Functions

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 17 - -
05 Locality of reference, Operation of 1
Chalk and Talk,PPT
Cache Memory
Quiz
30 Mapping Functions , Replacement 2
Chalk and Talk,PPT
Algorithms
05 Conclusion/Summary - -
Session – 19
12
 At the end of the session on Concept of Virtual Memory, my students will be able to

1. Understand about Virtual Memory Organization

2. Paging and Address Translation and Translation Look aside Buffer (TLB).

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 18 - -
20 Concept of Virtual Memory 2
Chalk and Talk,PPT
Organization, paging
Discussion
15 Address Translation and Translation 2
Chalk and Talk,PPT
Look aside Buffer (TLB)
05 Conclusion/Summary - -
Session –20

At the end of the session on Input/output processing, my students will be able to

1. Understand the Input/output processing

Teaching Active Learning

Time Topic BTL
Learning Method Method
05 Recap session 19
35 Input/output processing 1 Chalk and Talk,PPT Discussion
05 Conclusion/Summary - -
Session –21

At the end of the session on video display unit, my students will be able to

1. Understand the working with video display unit

2. Understand keyboard and its sub-routine

Teaching Active Learning

Time Topic BTL
Learning Method Method
05 Recap session 20
20 Video display unit 1 Chalk and Talk,PPT
One Minute Paper
15 Keyboard and control routine 1 Chalk and Talk,PPT
05 Conclusion/Summary - -
Session –22

At the end of the session on Input/output Organization, my students will be able to

1.Understand the Input/output Organization

2.Understand the types of I/O addressing.

13
 Teaching Active Learning
Time Topic BTL
Learning Method Method
05 Recap session 21
10 Input/output Modules 1 Chalk and Talk,PPT
10 Two types of addressing: Memory- 2
mapped I/O, Isolated or I/O Chalk and Talk,PPT
Discussion
mapped I/O
15 Input / Output Subsystem: 2
Chalk and Talk,PPT
Programmed I/O
05 Conclusion/Summary - -
Session – 23
At the end of the session on Interrupt driven I/O, my students will be able to

1. Understand Interrupt Processing

2. Design Issues for Interrupt, Device Identification

Teaching Active Learning

Time Topic BTL
Learning Method Method
05 Recap session 22
15 Interrupt driven I/O: Interrupt 1
Chalk and Talk,PPT
Processing
One Minute Paper
10 Design Issues for Interrupt 2 Chalk and Talk,PPT
10 Device Identification 2 Chalk and Talk,PPT
05 Conclusion/Summary - -
Session – 24
At the end of the session on DMA controlled I/O, my students will be able to

1. Understand the Direct Memory Access Controller and

2. DMA mechanism

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 23 - -
10 2. Direct Memory Access Controller 1 Chalk and Talk,PPT
10 DMA mechanism: Single bus, 2
Chalk and Talk,PPT
detached DMA - I/O configuration Discussion
15 1. Single bus, Integrated DMA - I/O 2
Chalk and Talk,PPT
configuration
05 Conclusion/Summary
Session – 25
At the end of the session on Secondary storage, my students will be able to

1. Understand secondary storage devices and classification

2. Magnetic devices operation and optical devices

14
 Teaching Active Learning
Time Topic BTL
Learning Method Method
5 Recap session 24 - -
10 3. Secondary storage devices, 2
Chalk and Talk,PPT
classification
10 Magnetic Devices: Magnetic 2 Chalk and Talk,PPT Quiz
Disk, Data Striping, Redundancy
15 Optical Devices: CD- ROM, DVD 2 Chalk and Talk,PPT
05 Conclusion/Summary
Session – 26
At the end of the session on introduction to buses, my students will be able to

1. Understand Data transfer over a bus: Synchronous bus and Asynchronous bus
2. Understand how to connect I/O devices and memory with CPU

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 25 - -
5 4. I/O Buses: The bus lines 1 Chalk and Talk,PPT
10 Data transfer over a bus: 1
Synchronous bus, Asynchronous Chalk and Talk,PPT
One Minute Paper
bus
10 Connecting I/O devices with CPU 1 Chalk and Talk,PPT
10 1. Connecting I/O devices to memory 1 Chalk and Talk,PPT
05 Conclusion/Summary
Session – 27
At the end of the session on RISC and CISC paradigm, my students will be able to
1. Understand the Operations, Implications and
2. Characteristics of RISC

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 26 - -
15 2. Introduction to RISC,CISC 1 Chalk and Talk, PPT
10 Operations, Implications 1 Chalk and Talk, PPT
10 Characteristics of Reduced 1 Chalk and Talk, PPT Fish Bowl
Instruction Set Architecture, , RISC
Vs CISC
05 Conclusion/Summary
Session – 28
At the end of the session on Design issues of a RISC processor, my students will be able
to
1. Understand the use of a large register file and Register Window

15
 2. Compiler based Register Optimization.

Teaching
Active Learning
Time Topic BTL Learning
Method
Method
5 Recap session 27 - -
10 3. The use of a large register file: 1 Chalk and Talk,PPT
10 Register Window 1 Chalk and Talk,PPT
15 Compiler based Register 1 Chalk and Talk,PPT Discussion
Optimization, Example of RISC
processor
05 Conclusion/Summary
Session – 29
At the end of the session on Introduction to Pipeline, my students will be able to
1. Understand about The concept of instruction execution in pipeline and
2. Understand 4-stage pipelining

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 28 - -
35 4. The concept of instruction 2
execution in pipeline with the Chalk and Talk,PPT One minute Paper
timing diagrams
05 Conclusion/Summary
Session – 30
At the end of the session on pipeline hazards, my students will be able to
1. Understand about the concept Pipeline Hazards
2. Understand and analyze how to resolve hazards

Teaching Active Learning

Time Topic BTL
Learning Method Method
5 Recap session 29 - -
20 Pipeline Hazards: Data Hazards, 1 Chalk and Talk,PPT
Structural Hazards, Control Hazards Fish Bowl
20 Resolving Hazards 2 Chalk and Talk,PPT
05 Conclusion/Summary
Session – 31
At the end of the session on towards design issues of pipelining, my students will be able
to

1. Understand about pipeline performance

2. Understand design issues of pipelining

16
 Teaching
Active Learning
Time Topic BTL Learning
Method
Method
5 Recap session 30 - -
20 Pipeline performance 1 Chalk and
Talk,PPT
Quiz
15 Design issues 2 Chalk and
Talk,PPT
05 Conclusion/Summary
Session – 32

At the end of the session on towards instruction-level parallelism, my students will be

able to

1. Understand about instruction level parallelism

2. Understand about limitations and issues of parallelism

Active
Teaching
Time Topic BTL Learning
Learning Method
Method
5 Recap session 31 - -
35 Instruction-level parallelism, 1
Chalk and Talk,PPT Discussion
limitations and issues
05 Conclusion/Summary

17
Laboratory delivery plan

Lab session CO-

List of Experiments
no Mapping
Batch division, Introduction to Logisim software and -
1
Project based Lab
Design and Implementation of Coding Mechanism in Digital
2 Hardware CO1

Design of Computational Processing System for Arithmetic

3 and Logical Operations. CO1

Implementation of information transmission system

4 CO2
Development of Instruction processing system from
5 CO2
fetching to execution
6 Implementation of Cache memory CO2

7 Choice based control of Vending Machine CO3

8 Peripheral to Peripheral data Transfer using DMA CO3

9 Implementation of three stage pipelining CO4

10 Lab experiment – Assessment through review -

11 Lab Internal Exam -

List of tutorials, tutorial delivery plan

Tutorial CO-
Topics
session no Mapping
Generations of computer systems with current
configurations and comparison between the technical
1 CO1
specifications, Different number systems, interrelated to
the real-world computer hardware ( ALM )
Number Systems, combinational circuits, Number system
2 CO1
formats, ALU
3 Instructions set, addressing modes, micro-operations CO2
4 RAM and ROM memories , control unit( LTC ) CO2
5 DMA and storage memories CO3
6 Daisy chain and priority encoder ( LTC ) CO3
7 Simple CPU design ( LTC ) and case studies(ALM) CO4
8 Pipelining CO4

*** LTC using Logisim tool**

18
 Evaluation

Evaluation Assessment
Evaluation Duration CO 1 CO 2 CO 3 CO 4 CO5
Component Weightage /Marks Dates
Type
Blooms Taxonomy Level 1 1 1 2 3

Weightage 5 1.25 1.25 1.25 1.25

ALM &
Continuous Evaluation
Tutorial
Max Marks 80 20 20 20 20

Weightage 5 Lab experiment continuous 5

evaluation will be for 25 marks
Formative for each experiment and the
Evaluation Lab average of all experiments is
Total = 15% Continuous Continuous Evaluation scaled to 5%. Initial rubrics for
Evaluation Max Marks 25 evaluation are: 25
[ Record(5) + Experimentation
(10) + Viva-voce(10)]

Weightage 5
Attendance Continuous Evaluation (Equal weightage to all sessions)
Max Marks 5

Weightage 15 7.5 7.5

Test 1 Test 1 Dates 1.5 hrs
Max Marks 30 15 15

Weightage 15 7.5 7.5

Test 2 Test 2 Dates 1.5 hrs
In-Semester
Max Marks 30 15 15
Summative
Evaluation
Total = 35% Weightage Lab exam will be conducted for 5
5
25 marks and scaled to 5%.
Lab Internal Initial rubrics for evaluation are:
Lab Internal
1.5 hrs [Write up (10) +
Tests Dates
Max Marks 25 Experimentation (10) + Viva- 25
voce(5)]

Weightage Lab exam will be conducted for 10

10
50 marks and scaled to 15%.
Initial rubrics for evaluation are:
End- SE Lab Exam Lab External 1.5 hrs [Record (10) + Write up (10) +
Semester Max Marks 50 Dates 50
Experimentation (20) + Viva-
Summative
Evaluation voce(10)]
Total = 50%
Weightage 10 10 10 10
Semester End 40
Sem End 3 hrs
Exam
Max Marks 60 Exam Dates 15 15 15 15

19
Course Team members, Chamber Consultation Hours and Chamber Venue details:

Chamber
Chamber Chamber Signature of
Consultation
S.No. Name of Faculty Consultatio Consultation Course
Timings for
n Day (s) Room No: faculty
each day
1 Dr. Habibulla Khan C-103
2 Dr. BTP Madhav L-706
3 Dr. D. Pardhasaradhi
4 Dr. K. Kiran Kumar
Main Exam
5 Mr. M. Ajay Babu
Section
6 Mr.Ch.Sree Vardhan C-106
7 Mr. N. Siddaih C-223
8 Mr. GV Ganesh C-223
9 Mr. B. Murali Krishna C-105
10 Mrs. S. Nagendram C-205
11 Mrs. K. Anusha C-105
12 Mrs. Y.Usha Devi C-105
13 Mr. S. Raj Gopal C-206
14 Mr. N. Srinivasulu C-223
15 Mr. P. Gopi Krishna C-324
16 Mr. M.Ramesh Kumar C-324
17 Mrs. PSG Aruna Sri C-304

Signature of COURSE COORDINATOR:

Signature of Department Prof. Incharge Academics &Vetting Team Member:

Recommended by HEAD OF DEPARTMENT:

Approved By: DEAN-ACADEMICS

(Sign with Office Seal)

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