Timing Diagram

Lecture objectives: at the end of this lecture the student will able to:
• 1- Define the timing diagram.
• 2- Study and representation of the clock signal.
• 3- Determine the types of 8085 machine cycles

PRITAM
• Timing Diagram: Timing diagram is the display of initiation of
read/write and transfer of data operations under the control of 3-status
signals IO / M , S1, and S0
• Instruction Cycle: It is fetching, decoding and executing of a single
instruction, which consists of one to five read or writing operations
between processor and memory or I/O devices
• Machine Cycle: It is the one cycle that required to move one byte of
data in or out of the microprocessor. Each one machine cycle consists 3
to 6 clock period, referred to as T-state
• T-state: It is the time of one clock period which depends on operating
frequency
Another definition of the T-state is a portion of an operation carried out in one system clock period

PRITAM
• There are seven different types of machine cycles in 8085A. And depend on
status signals i.e. IO / M , S1, and S0. These signals are generated at the
beginning of each machine cycle and remained valid for the duration of
the cycle.
• Clock Signal: The 8085 divide the clock frequency provided by X1 and X2
inputs by 2 which is called operating frequency. Ideally, the clock signals
should be square wave with zero rise and fall time, but practically, cannot get
zero rise time and fall time. Therefore, the clock and other signals are always
shown with finite rise and fall times

PRITAM
PRITAM
 Single signal representation

Group signal representation

PRITAM
 Signal Timing
• Ex.1/
ALE is active high signal. It is activated in the beginning of T1 state
of machine cycle, except bus idle machine cycle, and it remain active in
T1state only as shown in

PRITAM
Ex.2/
A0-A7(Lower Byte Address) is available on the multiplexed address/data bus
(AD0-AD7) during T1 state of machine cycle, except bus idle machineycle as
shown in Fig. below:

PRITAM
• Ex.3/
D0-D7(Data Bus) it used to transfer the data from I/O devices or memory
to microprocessor or from microprocessor to IO device or memory during T2 and
T3 states. It is important to note that through reading data operation, the data will
appear on the data bus during the later part of the T2 state. while, in writing
data operation the data will appear on data bus at the beginning of T2 state, see
Fig.

PRITAM
• Ex.4/
A8-A15 (Higher Byte Address) is available on the address bus during
T1, T2, and T3 states of each machine cycle, except bus idle machine
cycle s shown in Fig. below:

PRITAM
• Ex.5/
IO/M, S1, S2 signals are called status signals. They determine the type of
machine cycle to be executed. They are activated at beginning of T1-state
of each machine cycle and remain active till the end of the machine cycle
as shown in Fig.

PRITAM
• Ex.6/
RD and WR are determine the direction of data follow between microprocessor
and IO devices or memory locations. As we noted that these signals activated
through T2 & T3 states of machine cycle. Both signals are never active at a
time. The Fig. shows the timing diagram of RD and WR signals.

PRITAM
8085 Machine Cycles and their Timings:
The 8085 has seven machine cycle. These are:

• 1. Opcode fetch
• 2. Memory read
• 3. Memory write
• 4. I/O read
• 5. I/O write
• 6. Interrupt acknowledge
• 7. Bus idle

PRITAM
Opcode fetch
• The first machine cycle of every instruction is opcode fetch cycle in
which the 8085 finds the nature of the instruction to be executed. In
this machine cycle, the microprocessor places the contents of PC on
the address bus then by reading operation it reads the opcode of an
instruction from determined memory location.
• The length of this cycle is not fixed

PRITAM
• Step1: (T1 state) The 8085 processor places the contents of program counter on the address
bus, activate the ALE and send the status signals IO/M, S1, and S0 with logical status (0 1 1)
respectively

• Step 2: (T2 state) The low order address disappears from AD0-AD7 lines. Also, 8085 processor
activates the RD signals to enable the addressed memory location which places its contents
on the data bus (AD0-AD7)

• Step 3: (T3 state) The processor loads the contents of data bus on its Instruction Register
and deactivates the RD signal to disables the memory devices

• Step4: (T4 state) the processor decode the opcode, and on the basis of the instruction received,
it decides whether to enter T5 or to enter T1 of new machine cycle. One byte instructions those
operate on eight bit data (8 bit operand) are executed in T4. for example: MOV C,B- ANA E-
ADD BINR C- RAR …etc

• Step5: (T5 & T6 states) the processor performs stack write, internal 16 bits, or conditional
return operations depending upon the type of instruction. One byte instructions those
operate on 16 bit data are executed in T5 & T6. For example DCX H, PCHL, SPHL, INX H, etc

PRITAM
PRITAM
Memory read cycle:
• The microprocessor executes the memory read cycle to read the
data from RAM or ROM memory. 8085 processor executes this
machine cycle in 3 T-states. Steps below show the details of this
machine cycle

PRITAM
• Step1 (T1 state): processor places the address on the address lines
from SP, Rp, or PC and activates ALE in order to latch low-order of
address. Also, it sends the status signals with logical status (0 1 0) for
memory read machine cycle

• Step2 (T2 state): , 8085 processor activates the RD signals to

enable the addressed memory location which places its contents on
the data bus (AD0-AD7)

• Step 3: (T3 state) The processor loads the contents of data bus on
specified register (F, A, B, C, D, E, H, and L) and deactivates the RD
signal to disables the memory devices

PRITAM
PRITAM
Memory write cycle
• The microprocessor executes the memory write cycle to store
the data into RAM or stack memory. 8085 processor executes this
machine cycle in 3 T-states. Steps below show the details of this
machine cycle

PRITAM
• Step1 (T1state): processor places the address on the address lines
from SP or Rp and activates ALE in order to latch low-order of
address. Also, it sends the status signals with logical status (0 0 1) for
memory write machine cycle

• Step2 (T2 state): , 8085 processor places tha data on data bus and
activates the WR signal to writing data into addressed memory
location

• Step 3: (T3state) The processor deactivates the WR signal which

disables the memory device and terminates the write operation.

PRITAM
PRITAM
IO read cycle:
• The microprocessor executes the IO read cycle to read the data
from input device. 8085 processor executes this machine cycle in 3 T-
states. Steps below show the details of this machine cycle

PRITAM
• Step1 (T1 state): processor places the address on the address lines
from SP, Rp, or PC and activates ALE in order to latch low-order of
address. Also, it sends the status signals with logical status (1 1 0) for
IO read machine cycle

• Step2 (T2 state): , 8085 processor activates the RD signals to

enable the addressed input device which places its contents on the
data bus (AD0-AD7)

• Step 3: (T3 state) The processor loads the contents of data bus on
specified register (F, A, B, C, D, E, H, and L) and deactivates the RD
signal to disables the input device

PRITAM
PRITAM
IO write cycle
• The microprocessor executes the IO write cycle to store the data into
output device. 8085 processor executes this machine cycle in 3 T-
states. Steps below show the details of this machine cycle

PRITAM
• Step1 (T1 state): processor places the address on the address lines
from SP or Rp and activates ALE in order to latch low-order of
address. Also, it sends the status signals with logical status (1 0 1) for
IO write machine cycle

• Step2 (T2 state): , 8085 processor places the data on data bus and
activates the WR signal to writing data into addressed output device

• Step 3: (T3 state) The processor deactivates the WR signal which

disables the output device and terminates the writing operation

PRITAM
PRITAM