PH 208 P lecture #1b

Intel 8085 μP instructions (246) - opcode with or without operands

• Data transfer/copy/memory/IO [MOV, MVI, LDA, STA, IN, OUT, …..]
• Arithmetic operation [ADD, SUB, INR, INX, DCR, DCX]
• Logical operation [AND, OR, XOR, RLC. RAL, RRC, RAR, CMP, CPI, CMA …]
• Branching operation [JMP, CALL, Jx, Cx]
• Machine control [HLT, NOP, PUSH, POP, DI. EI, SIM, RIM, …..]

• Every instruction of a program has to operate on a data.

• Instructions are of 1-, 2- or 3-bytes [MOV A, B MVI B 1AH LDA 05 20H]
• Method of specifying data to be operated by the instruction is called
addressing mode. The 8085 has five different modes of addressing, viz.,
1. Immediate Addressing
2. Direct Addressing
3. Register Addressing
4. Register Indirect Addressing
5. Implicit Addressing
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
 PH 208 P lecture #1b

Addressing modes in 8085 μP

1. Immediate Addressing:
In immediate addressing mode, the data is specified in the instruction itself. The
data will be a part of the program instruction. e.g. MVI B, 3EH LXI SP, 2700H.
2. Direct Addressing:
In direct addressing mode, the address of the data is specified in the instruction.
The data will be in memory. In this addressing mode, the program instructions
and data can be stored in different memory. e.g. LDA 1050H SHLD 3000H
3. Register Addressing:
In register addressing mode, the instruction specifies the name of the register in
which the data is available. e.g. MOV A, B SPHL ADD C
4. Register Indirect Addressing:
In register indirect addressing mode, the instruction specifies the name of the
register in which the address of the data is available. Here the data will be in
memory and the address will be in the register pair. e.g. , MOV A, M LDAX B
5. Implicit Addressing:
In implicit addressing mode, the instruction itself specifies the data to be
operated. e.g. CMA RAL

A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati

 PH 208 P lecture #1b

Data transfer instructions and their OPCODES DDD/ Register

D7 D0 SSS
MOV rD, rS (rD) ← (rS) 0 1 D D D S S S 111 A
D7 D0 000 B
MOV rD, M (rD) ← ((H)(L)) 0 1 D D D S S S 001 C
010 D
D7 D0 011 E
MVI rD, data (rD) ← (byte) 0 0 D D D 1 1 0 100 H
data 101 L
D7 D0 110 M
MVI M, data ((H)(L)) ← data 0 0 D D D 1 1 0
data RP Reg. Pair
00 B-C
D7 D0 01 D-E
LXI rp , data16 (rh) ← (byte3) 0 0 R P 0 0 0 1 10 H-L
(rl) ← (byte2) lower order byte rl 11 SP
higher order byte rh
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
 PH 208 P lecture #1b
LDA C0 20 Load Acc Direct 3A 20 C0 <C020> → <A>
If C020 <F8>, then <A> = F8
STA C0 50 Store Acc Direct 32 50 C0 <A> → <C050>
If <A> = E1, then C050 = <E1>
LDAX rp Load Acc indirect Let <B C> & D020 <7F> <D020> → <A>
LDAX B D0 20 So <A> = 7F
STAX rp Store Acc indirect Let <D E> and <A> = <2B> <A> → <D050>
STAX D D0 50 So <D050> = 2B
LHLD E010 Load HL Direct 2A 10 E0 Let E010 <AB> <E010> → <L>
E011 <11> <E011> → <H>
So <H> = 11 & <L> = AB
SHLD F010 Store HL Direct 22 10 F0 Let <H> = 01 & <L> = FF
So, <L> → <F010>= FF & <H> → <F011>= 01
IN port # Acc is loaded data from specified port
OUT port# Specified port is loaded with Acc content
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
 PH 208 P lecture #1b
Arithmetic operations Logical operations
ADD r <A> ← <A> + <r> CMP r
ADI data <A> ← <A> + data CPI byte
ADC r <A> ← <A> + <r> + <CY> ORA r
ACI data <A> ← <A> + data + <CY> ORI data
SUB r <A> ← <A> - <r> ANA r
SUI data <A> ← <A> - data ANI data
SBB r <A> ← <A> - <r> - <CY> XRA r
SBI data <A> ← <A> - data - <CY> XRI data
INR r rotate opn. special opn.
DCR r RRC DAA
INX rp RAL CMA
DCX rp RLC STC
DAD rp RAR CMC
A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati
 PH 208 P lecture #1b

Branching opn. Sub-routine (CALL and RET) opn. M/C & other opn.
JMP addr CALL addr RET addr stack opn.
JZ addr CZ addr RZ addr PUSH rp

JNZ addr CNZ addr RNZ addr POP rp

JC addr CC addr RC addr control + interrupt

NOP
JNC addr CNC addr RNC addr
HLT
JP addr CP addr RP addr
EI
JM addr CM addr RM addr
DI
JPO addr CPO addr RPO addr
SIM
JPE addr CPE addr RPE addr
RIM
others
PCHL XTHL

RST x (x = 0 to 7) SPHL

A. Srinivasan, Department of Physics, Indian Institute of Technology Guwahati