library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity pwm_buck is
Port ( KEY : in STD_LOGIC_vector(1 downto 0);
GPIO: out std_logic_vector(33 downto 0);
LED: out std_logic_vector(7 downto 0);
SW: in std_logic_vector(3 downto 0);
CLOCK_50 : in STD_LOGIC
);
end pwm_buck;

architecture rtl of pwm_buck is

signal clock_aux: std_logic;

signal locked_aux: std_logic;

component pll_100
port
(
areset : IN std_logic;
inclk0 : IN std_logic;
c0 : OUT std_logic;
locked : OUT std_logic
);
end component;

component pwm_400_50
port
(
iniciar : IN std_logic;
reset : IN std_logic;
CLOCK_100 : IN std_logic;
ciclo_trabajo : IN std_logic_vector(6 downto 0);
salida_pwmh : OUT std_logic;
salida_pwml : OUT std_logic
);
end component;

begin

c1: pwm_400_50 port map (iniciar => locked_aux,

reset => not KEY(0),
CLOCK_100 => clock_aux,
ciclo_trabajo(6 downto 3) => SW,
salida_pwmh => GPIO(1),
salida_pwml => GPIO(0)
);

c2: pll_100 port map (areset => not KEY(0),

inclk0 => CLOCK_50,
c0 => clock_aux,
locked => locked_aux
);
LED(3 downto 0) <= SW;

end rtl;