Exam: Mid-term, 4th semester [Date:20-02-2023 Course title: DSD- Course code: PCCECEA3 Maximum marks: 35 Duration: 1% Hour Distinguish between linear and Non-linear systems with examples and Consider a stable LTI System characterized by the differential equation dy(t)/dt + 2y(t) = x(t). Find its impulse response. Ab aeneenannnee se ———B.Tech/B.E 4” SEMESTER (E&C Engé.) Session: March-April 2023 uae oo Digital System Design-II Min. Marks: 20 ‘Time Allowed : 2; Hours NOTE: arrewet att QUESTIONS FROM SECTION “A & 8” AND ONLY TWO QUESTIONS FROM SE 0x1 =10 Marks) TION °C" SECTION - A; (Very Short Answer Type Questions) Qi g. What is the main difference between CONSTANT, SIGNAL and VARIABLE? Jb. What is the significance VHDL? _ee What is the difference between gated array and FPGA? Mow is STD_LOGIC_VECTOR different from, STD_ULOGIC_VECTOR? _ of type conversion functions in P 1 code is inherently concurrent”. How do we implement any clocked circuit then? 4¢ How is PAL different from PLA? b What do you mean by glitching? SECTION ~ Bs. (Short Answer Type Questions) 4x5 =20 Nan @2 a. Write a VHDL code to design a 32-bit ripple carry adder using COMPONENTS. . How is Mealy machine different from Moore machine? What are the fundamental sections of a VHDL code? Write the general syntax of cach section. sMention one application where multiplexers are used. Construct and discuss a 16-to-I-line multiplexer with two 8- to-l-line multiplexers and one 2-to-1-line multiplexer. Use block diagram for the three multiplexersB.Tech/B.£ 4” Sem Mar-Aprit-2023 m sequential _& How are combinational circuits different fro circuits? With the help of diagram, discuss the master-slave flip-flop. (2110 = 2omarko 3 SECTION - CG; (Long Answer Type Questions) } Q.3 ac RAM and ROM chips are connected to a CPU through the data and address buses. The system has a memory capacity of 512 bytes of RAM and 512 bytes of ROM. Draw the memory connections to the CPU, list the memory address map and indicate what size decoders are needed. a b. Using FSM approach, design a sequential binary 0-to-9 counter. The inputs are clk and RST and the output is output (3:0). Draw the state diagram also. K _¢ Discuss the significance of data converters. Design a 3-bit ; DAC using R-2R architecture with R=1 kQ, R=2 kQ and 4 Varr= 5V. Assume that the resistances of the switches are negligible. Determine the value of Iyor for each digital input Vout. memory in is ative fy advantageous over random access memory? Describe in words and by means of os block diagram how multiple matched words can be read out from an associative memory. sdeseannnnanae o