APS12205, APS12215,

and APS12235
High-Temperature Hall-Effect Latches
for Low Voltage Applications

FEATURES AND BENEFITS DESCRIPTION

• Optimized for applications with regulated power rails The APS12205, APS12215, and APS12235 Hall-effect sensor
□ Operation from 2.8 to 5.5 V ICs are extremely temperature-stable and stress-resistant
• AEC-Q100 automotive qualified devices especially suited for operation over extended junction
• Operation up to 175°C junction temperature temperature ranges up to 175°C. Superior high-temperature
• Dynamic offset cancellation performance is made possible through dynamic offset
□ Resistant to physical stress cancellation, which reduces the residual offset voltage normally
□ Superior temperature stability caused by device overmolding, temperature dependencies, and
• Symmetrical latch switchpoints thermal stress.
• Output short-circuit protection The single silicon chip includes: a Hall plate, small signal
• Solid-state reliability amplifier, chopper stabilization, Schmitt trigger, and a short-
• Industry-standard packages and pinouts circuit-protected open-drain output. A south pole of sufficient
strength turns the output on; a north pole of sufficient strength
is necessary to turn the output off. For applications requiring
PACKAGES:
Not to scale operation from greater than 5.5 V or operation directly from
a battery, refer to the A1220, A1221, or A1223.
Two package styles provide a choice of through-hole or surface
mounting. Package type LH is a modified 3-pin SOT23W
surface-mount package, while UA is a three-pin ultramini SIP
for through-hole mounting. Both packages are lead (Pb) free,
with 100% matte-tin-plated leadframes.

3-pin SOT23W
(suffix LH)
3-pin SIP
(suffix UA)

Functional Block Diagram

VCC

To All Subcircuits

Low-Pass VOUT
Sample and Hold

Filter
Dynamic Offset
Cancellation

Amp Control

Current Limit

GND

APS12205-15-35-DS, Rev. 5 September 10, 2021

MCO-0000479
APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

SELECTION GUIDE
Part Number Packing [1] Mounting Branding Ambient, TA BRP (Min) BOP (Max)
APS12205ELHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A04
–40°C to 85°C
APS12205ELHALT [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A04
APS12205LLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A04 –40 G 40 G
APS12205LLHALT [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A04 –40°C to 150°C
APS12205LUAA Bulk, 500 pieces/bag 3-pin SIP through hole A18
APS12215LLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A01
APS12215LLHALT [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A01 –40°C to 150°C –90 G 90 G
APS12215LUAA Bulk, 500 pieces/bag 3-pin SIP through hole A03
APS12235LLHALX 13-in. reel, 10000 pieces/reel 3-pin SOT23W surface mount A35
APS12235LLHALT [2] 7-in. reel, 3000 pieces/reel 3-pin SOT23W surface mount A35 –40°C to 150°C –180 G 180 G
APS12235LUAA Bulk, 500 pieces/bag 3-pin SIP through hole A36

[1] Contact Allegro for additional packing options.

[2] Available through authorized Allegro distributors only.

RoHS
COMPLIANT

ABSOLUTE MAXIMUM RATINGS

Characteristic Symbol Notes Rating Units
Forward Supply Voltage VCC 6 V
Reverse Supply Voltage VRCC –0.3 V
Output Off Voltage VOUT 6 V
Output Current IOUT Through short-circuit current limiting device. 60 mA
165 °C
Maximum Junction Temperature TJ(max)
For 1000 hours. 175 °C
Storage Temperature Tstg –65 to 170 °C

2
Allegro MicroSystems
955 Perimeter Road
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

PINOUT DIAGRAMS AND TERMINAL LIST TABLE

GND

1 2 3

VCC

VOUT
GND
1 2
VCC

VOUT

Package LH Package UA

Terminal List
Number
Name Description Package Package
LH UA
VCC Connects power supply to chip 1 1
VOUT Output from circuit 2 3
GND Ground 3 2

3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

ELECTRICAL CHARACTERISTICS: Valid over full operating voltage and ambient temperature range, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ.[1] Max. Unit [2]
ELECTRICAL CHARACTERISTICS
Forward Supply Voltage VCC Operating, TJ < 175°C 2.8 – 5.5 V
Supply Current ICC VCC = 5.5 V – 2 3 mA
Output Leakage Current IOUTOFF VOUT = 5.5 V, B < BRP – – 10 µA
Output Saturation Voltage VOUT(SAT) IOUT = 5 mA, B > BOP – 50 500 mV
Output Current IOUT Recommended value used during characterization – 5 – mA
Output Short-Circuit Current Limit IOM B > BOP 30 – 60 mA
VCC ≥ 2.8 V, B < BRP(min) – 10 G,
Power-On Time [3] tON – – 25 µs
B > BOP(max) + 10 G
Power-On State, Output [3] POS VCC ≥ VCC(min), t < tON Low –
Chopping Frequency fC – 800 – kHz
Output Rise Time [3][4] tr RPULL-UP = 1 kΩ, CL = 20 pF – 0.2 2 µs
Output Fall Time [3][4] tf RPULL-UP = 1 kΩ, CL = 20 pF – 0.1 2 µs
MAGNETIC CHARACTERISTICS
APS12205 5 22 40 G
Operate Point BOP APS12215 15 50 90 G
APS12235 100 150 180 G
APS12205 –40 –22 –5 G
Release Point BRP APS12215 –90 –50 –15 G
APS12235 –180 –150 –100 G
APS12205 10 45 80 G
Hysteresis BHYS APS12215 (BOP – BRP) 30 100 180 G
APS12235 200 300 360 G

[1] Typical
data are are at TA = 25°C and VCC = 5 V, and are for initial design estimations only.
[2] 1G (gauss) = 0.1 mT (millitesla).
[3] Guaranteed by device design and characterization.
[4] C = oscilloscope probe capacitance.
L

4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

THERMAL CHARACTERISTICS: May require derating at maximum conditions; see application information
Characteristic Symbol Test Conditions Value Units
Package LH, 1-layer PCB with copper limited to solder pads 228 °C/W
Package LH, 2-layer PCB with 0.463 in.2 of copper area each
Package Thermal Resistance RθJA 110 °C/W
side connected by thermal vias
Package UA, 1-layer PCB with copper limited to solder pads 165 °C/W

Power Derating Curve

TJ(max) = 175°C; ICC = ICC(max), IOUT = 0 mA (Output Off)
6

VCC(max)
Maximum Allowable VCC (V)

5
Package LH, 2-layer PCB
(RθJA = 110 °C/W) (Right)
Package UA, 1-layer PCB
(RθJA = 165 °C/W) (Center)
Package LH, 1-layer PCB
4 (RθJA = 228 °C/W) (Left)

3
VCC(min)

2
25 45 65 85 105 125 145 165 185
Temperature (°C) TJ(max)

Package Power Dissipation versus Ambient Temperature

1900
1800
1700
1600
Power Dissipation, PD (mW)

1500
1400
Package LH, 2-layer PCB
1300 (RθJA = 110°C/W)
1200 Package UA, 1-layer PCB
1100 (RθJA = 165°C/W)
1000
900
800
700
600
500
400
300
200 Package LH, 1-layer PCB
(RθJA = 228°C/W)
100
0
20 40 60 80 100 120 140 160 180

Temperature (°C)

5
Allegro MicroSystems
955 Perimeter Road
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

CHARACTERISTIC PERFORMANCE
Electrical Characteristics

Average Supply Current versus Supply Voltage Average Supply Current versus Ambient Temperature
4.0 4.0
3.5 3.5
3.0 3.0
TA (°C) VCC (V)

ICC (mA)
2.5 2.5
ICC (mA)

-40 2.8
2.0 2.0
25 5
1.5 1.5
150 5.5
1.0 1.0
0.5 0.5
0.0 0.0
2.5 3 3.5 4 4.5 5 5.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VCC (V) TA (°C)

Average Low Output Voltage versus Supply Voltage for IOUT = 5 mA Average Low Output Voltage versus Ambient Temperature for IOUT = 5 mA
500 500
450 450
400 400
VOUT(SAT) (mV)

350 TA (°C) VCC (V)

VOUT(SAT) (mV)

350
300 -40 300
2.8
250 250
25
200 200 5
150 150
150 5.5
100 100
50 50
0 0
2.5 3 3.5 4 4.5 5 5.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VCC (V) TA (°C)

6
Allegro MicroSystems
955 Perimeter Road
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

CHARACTERISTIC PERFORMANCE (continued)

APS12205 Magnetic Characteristics

Average Operate Point versus Supply Voltage Average Operate Point versus Ambient Temperature

40 40

35 35
TA (°C) 30
30
VCC (V)
-40

BOP (G)
25
BOP (G)

25 2.8

20 25 20 5

150 15 5.5
15

10 10

5
5
-60 -40 -20 0 20 40 60 80 100 120 140 160
2.5 3 3.5 4 4.5 5 5.5 6
VCC (V) TA (°C)

Average Release Point versus Supply Voltage Average Release Point versus Ambient Temperature

-5 -5

-10 -10
TA (°C) -15
-15
VCC (V)
-40
BRP (G)

-20
BRP (G)

-20 2.8

-25 25 -25 5

150 -30 5.5

-30

-35 -35

-40
-40
-60 -40 -20 0 20 40 60 80 100 120 140 160
2.5 3 3.5 4 4.5 5 5.5 6
VCC (V) TA (°C)

Average Switchpoint Hysteresis versus Supply Voltage Average Switchpoint Hysteresis versus Ambient Temperature
80 80

70 70

60 VCC (V)
60 TA (°C)
2.8
BHYS (G)
BHYS (G)

50 -40 50
5
40 25 40
5.5
30 150 30

20 20

10 10
2.5 3 3.5 4 4.5 5 5.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VCC (V) TA (°C)

7
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

CHARACTERISTIC PERFORMANCE (continued)

APS12215 Magnetic Characteristics

Average Operate Point versus Supply Voltage Average Operate Point versus Ambient Temperature
90 90
85 85
80 80
75 75
70
TA (°C) 70
65 65 VCC (V)
60 -40 60

BOP (G)
BOP (G)

55 55 2.8
50 25 50
45 45 5
40 40
150 35 5.5
35
30 30
25 25
20 20
15 15
2.5 3 3.5 4 4.5 5 5.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VCC (V) TA (°C)

Average Release Point versus Supply Voltage Average Release Point versus Ambient Temperature

-15 -15
-20 -20
-25 -25
-30 -30
-35
TA (°C) -35
-40 -40 VCC (V)
-40 -45
BRP (G)

-45
BRP (G)

-50 2.8
-50
-55 -55
25 -60 5
-60
-65 -65
150 -70 5.5
-70
-75 -75
-80 -80
-85
-85
-90
-90
-60 -40 -20 0 20 40 60 80 100 120 140 160
2.5 3 3.5 4 4.5 5 5.5 6
VCC (V) TA (°C)

Average Switchpoint Hysteresis versus Supply Voltage Average Switchpoint Hysteresis versus Ambient Temperature
180 180
170 170
160 160
150 150
140 140 VCC (V)
130
TA (°C) 130
2.8
BHYS (G)
BHYS (G)

120 -40 120

110 110
5
100 100
90 25 90 5.5
80 80
70 150 70
60 60
50 50
40 40
30 30
2.5 3 3.5 4 4.5 5 5.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VCC (V) TA (°C)

8
Allegro MicroSystems
955 Perimeter Road
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

CHARACTERISTIC PERFORMANCE (continued)

APS12235 Magnetic Characteristics

Average Operate Point versus Supply Voltage Average Operate Point versus Ambient Temperature
180 180

170 170

160 TA (°C) 160

150 VCC (V)
150 -40

BOP (G)
BOP (G)

2.8
140 140
25 5
130 130
150 5.5
120 120

110 110

100 100
2.5 3 3.5 4 4.5 5 5.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VCC (V) TA (°C)

Average Release Point versus Supply Voltage Average Release Point versus Ambient Temperature

-100 -100

-110 -110

-120 TA (°C) -120

-130 VCC (V)
-130 -40
BRP (G)
BRP (G)

2.8
-140 -140
25 5
-150 -150
150 5.5
-160 -160

-170 -170
-180
-180
-60 -40 -20 0 20 40 60 80 100 120 140 160
2.5 3 3.5 4 4.5 5 5.5 6
VCC (V) TA (°C)

Average Switchpoint Hysteresis versus Supply Voltage Average Switchpoint Hysteresis versus Ambient Temperature
360 360
350 350
340 340
330 330
320 320 VCC (V)
310 TA (°C) 310
300 300 2.8
BHYS (G)
BHYS (G)

290 -40 290

280 280 5
270 25 270
260 260 5.5
250 250
240 150 240
230 230
220 220
210 210
200 200
2.5 3 3.5 4 4.5 5 5.5 6 -60 -40 -20 0 20 40 60 80 100 120 140 160
VCC (V) TA (°C)

9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

FUNCTIONAL DESCRIPTION

OPERATION
The output of these devices switches low (turns on) when a mag-
netic field perpendicular to the Hall element exceeds the operate
point threshold, BOP (see Figure 1). After turn-on, the output volt-
age is VOUT(SAT) . The output transistor is capable of continuously
sinking up to 30 mA. When the magnetic field is reduced below
the release point, BRP , the device output goes high (turns off).
The difference in the magnetic operate and release points is the
hysteresis, BHYS , of the device. This built-in hysteresis allows
clean switching of the output even in the presence of external
mechanical vibration and electrical noise.
Removal of the magnetic field will leave the device output
latched on if the last crossed switchpoint is BOP, or latched off if
the last crossed switch point is BRP.
Device power-on occurs once tON has elapsed. During the
time prior to tON, and after VCC ≥ VCC(min), the output state is
VOUT(SAT) (Low). After tON has elapsed, the output will corre-
spond with the applied magnetic field for B > BOP or B < BRP.
See Figure 2 for an example.
Powering-on the device in the hysteresis range (less than BOP and
higher than BRP) will give an output state of VOUT(SAT). The cor-
rect state is attained after the first excursion beyond BOP or BRP .
POS
B > BOP, BRP < B < BOP
V
B < BRP

POWER-ON BEHAVIOR VOUTOFF

Output State
VOUT

V+ Undefined for
VOUTOFF VCC< VCC(min) POS
VOUT(SAT )
Switch to High

Switch to Low

t
V
VOUT

VCC (min)
VCC

VOUT(SAT)
0 0
B– 0 B+
t ON t
BOP
BRP

BHYS Figure 2: Power-On Timing Diagram

Figure 1: Switching Behavior of Latches
On the horizontal axis, the B+ direction indicates increasing
south polarity magnetic field strength, and the B– direction
indicates decreasing south polarity field strength (including the
case of increasing north polarity.

10
Allegro MicroSystems
955 Perimeter Road
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

APPLICATIONS
It is strongly recommended that an external bypass capacitor be
VS
connected (in close proximity to the Hall element) between the
supply and ground of the device to guarantee correct performance
under harsh environmental conditions and to reduce noise from VCC RPULL-UP
internal circuitry. As is shown in Figure 3, a 0.1 µF capacitor is
typical. CBYP
APS122xx
VOUT
0.1 µF
Extensive applications information on magnets and Hall-effect Output
sensors is available in:
GND
• Hall-Effect IC Applications Guide, AN27701,
• Hall-Effect Devices: Guidelines for Designing Subassemblies
Using Hall-Effect Devices AN27703.1
• Soldering Methods for Allegro’s Products – SMD and
Through-Hole, AN26009 Figure 3: Typical Application Circuit

All are provided on the Allegro website:

www.allegromicro.com

11
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

CHOPPER STABILIZATION
A limiting factor for switchpoint accuracy when using Hall-effect
technology is the small signal voltage developed across the Hall
plate. This voltage is proportionally small relative to the offset
that can be produced at the output of the Hall sensor. This makes
it difficult to process the signal and maintain an accurate, reliable
output over the specified temperature and voltage range. Chopper
stabilization is a proven approach used to minimize Hall offset.
The Allegro technique, dynamic quadrature offset cancellation,
removes key sources of the output drift induced by temperature
and package stress. This offset reduction technique is based on a
signal modulation-demodulation process. Figure 4 illustrates how
it is implemented.
The undesired offset signal is separated from the magnetically
induced signal in the frequency domain through modulation. The
subsequent demodulation acts as a modulation process for the
offset, causing the magnetically induced signal to recover its orig-
inal spectrum at baseband while the DC offset becomes a high-
frequency signal. Then, using a low-pass filter, the signal passes
while the modulated DC offset is suppressed. Allegro’s innova-
tive chopper stabilization technique uses a high-frequency clock.
The high-frequency operation allows a greater sampling rate
that produces higher accuracy, reduced jitter, and faster signal
processing. Additionally, filtering is more effective and results in
a lower noise analog signal at the sensor output. Devices such as
the APS12205, APS12215, and APS12235 that use this approach
have an extremely stable quiescent Hall output voltage, are
immune to thermal stress, and have precise recoverability after
temperature cycling. This technique is made possible through the
use of a BiCMOS process which allows the use of low offset and
low noise amplifiers in combination with high-density logic and
sample-and-hold circuits.

Clock/Logic
Low-Pass
Hall Element Filter
Sample and
Hold

Amp

Figure 4: Model of Chopper Stabilization

(Dynamic Offset Cancellation)

12
Allegro MicroSystems
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

POWER DERATING For example, given common conditions such as: TA= 25°C,
The device must be operated below the maximum junction tem- VCC = 5 V, ICC = 2.5 mA, VOUT = 185 mV, IOUT = 2 mA (output
perature of the device, TJ(max). Under certain combinations of on), and RθJA = 165°C/W, then:
peak conditions, reliable operation may require derating supplied
PD = (VCC × ICC) + (VOUT × IOUT) =
power or improving the heat dissipation properties of the appli-
(5 V × 2.5 mA) + (185 mV × 2 mA) =
cation. This section presents a procedure for correlating factors
12.5 mW + 0.4 mW = 12.9 mW
affecting operating TJ. (Thermal data is also available on the
Allegro MicroSystems website.) ΔT = PD × RθJA = 12.9 mW × 165°C/W = 2.1°C
The Package Thermal Resistance, RθJA, is a figure of merit sum- TJ = TA + ΔT = 25°C + 2.1°C = 27.1°C
marizing the ability of the application and the device to dissipate
A worst-case estimate, PD(max), represents the maximum allow-
heat from the junction (die), through all paths to the ambient air.
able power level (VCC(max), ICC(max)), without exceeding
Its primary component is the Effective Thermal Conductivity, K,
TJ(max), at a selected RθJA.
of the printed circuit board, including adjacent devices and traces.
Radiation from the die through the device case, RθJC, is relatively For example, given the conditions RθJA = 228°C/W, TJ(max) =
small component of RθJA. Ambient air temperature, TA, and air 175°C, VCC(max) = 5.5 V, ICC(max) = 4 mA, VOUT = 500 mV,
motion are significant external factors, damped by overmolding. and IOUT = 5 mA (output on), the maximum allowable operating
ambient temperature can be determined.
The resulting power dissipation capability directly reflects upon
the ability of the device to withstand extreme operating condi- The power dissipation required for the output is shown below:
tions. The junction temperature mission profile specified in the
PD(VOUT) = VOUT × IOUT = 500 mV × 5 mA = 2.5 mW
Absolute Maximum Ratings table designates a total operating life
capability based on qualification for the most extreme conditions, The power dissipation required for the IC supply is shown below:
where TJ may reach 175°C.
PD(VCC) = VCC × ICC = 5.5 V × 4 mA = 22 mW
The silicon IC is heated internally when current is flowing into
Next, by inverting using equation 2:
the VCC terminal. When the output is on, current sinking into the
VOUT terminal generates additional heat. This may increase the ΔT = PD × RθJA = [PD(VOUT) + PD(VCC)] × 228°C/W =
junction temperature, TJ, above the surrounding ambient tempe- (2.5 mW + 22 mW) × 228°C/W =
rature. The APS12205, APS12215, and APS12235 are permitted 24.5 mW × 228°C/W = 5.6°C
to operate up to TJ = 175°C. As mentioned above, an operating
Finally, by inverting equation 3 with respect to voltage:
device will increase TJ according to equations 1, 2, and 3 below.
This allows an estimation of the maximum ambient operating TA(est) = TJ(max) – ΔT = 175°C – 5.6°C = 169.4°C
temperature.
In the above case there is only sufficient power dissipation
PD = VIN × IIN (1) capability to operate up to TA(est). This particular result indicates
that, at TJ(max), the application and device can only dissipate
ΔT = PD × RθJA (2) adequate amounts of heat at ambient temperatures ≤ TA(est);
the APS12205, APS12215, and APS12235 performance is not
TJ = TA + ΔT (3) guaranteed above T = 150°C for the “L” temperature variant and
A
TA = 85°C for the “E” temperature variant.

13
Allegro MicroSystems
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APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

Package LH, 3-Pin (SOT-23W)

For Reference Only – Not for Tooling Use

(Reference Allegro DWG-0000628, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown

+0.125
2.975 –0.075

4°±4°
3 Active Area Depth
0.28 ±0.04 mm
+0.020
0.180–0.053

Die Rotation
Error 4° Max 2.40
0.70
+0.10 +0.19
2.90 –0.20 1.91 –0.06

1.00
Hall Element 0.25 MIN
(not to scale) 0.38 NOM

1 2
Package Centerline
to Die Centerline ±0.20
Package Centerline
to Die Centerline ±0.15 0.95
PCB Layout Reference View
0.55 REF 0.25 BSC All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
Seating Plane to meet application process requirements and PCB layout tolerances
Gauge Plane

8× 10° ±5° Branded Face Standard Branding Reference View

0.57 ±0.04
3× 1.00 ±0.13 C

0.10 C 0.41 ±0.04 A04

SEATING
PLANE
+0.10
0.05 –0.05
1
0.95 BSC APS12205ELHA and APS12205LLHA
0.40 ±0.10
Lead Foot Centerline
To Package Centerline ±0.18

A01 A35

1 1
APS12215LLHA APS12235LLHA

14
Allegro MicroSystems
955 Perimeter Road
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www.allegromicro.com
APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

Package UA, 3-Pin SIP

For Reference Only – Not For Tooling Use
(Reference DWG-0000404, Rev. 1)
NOT TO SCALE
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown

Ejector pin flash Mold gate and tie bar

protrusion protrusion zone

R0.25 MAX (2×) 5° (2×) 0.56 MAX

45° (2×) 1.52 ±0.05 1.68 MAX

0.10 MAX
5° (2×)

+0.08
4.09 –0.05

3.00 ±0.05
2.04
Mold gate and tie bar Sensor element location tolerance
protrusion zone Standard ±0.20
0.15 MAX
Ejector pin 0.50 ±0.08 Active Area Depth
(far side) +0.05
Including gate and 0.08 –0.00
tie bar burrs
Ejector pin flash
Sensor element location tolerance protrusion
1.44 Standard ±0.20
3.10 MAX +0.08
3.02 –0.05
Hall Element
(not to scale) 45°
10° (3×)

1.02 MAX 0.79 REF

0.51 REF

0.05 NOM
0.05 NOM

14.99 ±0.25 +0.03

0.41 –0.06

0.10 MAX

0.10 MAX
Dambar Trim Detail

1.27 NOM (2×) +0.05

0.43 –0.07 (3×)

Standard Branding Reference View

Branding scale and appearance at supplier discretion.

A18 A03 A36

1 1 1
APS12205LUAA APS12215LUAA APS12235LUAA

15
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
APS12205,
APS12215,
High-Temperature Hall-Effect Latches
and APS12235 for Low Voltage Applications

Revision History
Number Date
– June 3, 2016
1 June 20, 2016
2 September 23, 2016
3 July 5, 2018
4 June 18, 2019
5 September 10, 2021
Description
Initial release
Updated Functional Block Diagram (page 1);
Updated Selection Guide (page 2) and package outline drawing brand information (pages 14-
15).
Updated Title (all pages), Selection Guide (page 2), Absolute Maximum Ratings (page 2);
Electrical Characteristics (page 4); added Characteristic Performance Data (pages 6-9);
updated Functional Description (page 6), Chopper Stabilization (page 12), and Power
Derating sections (page 13).
Updated TJ(max) notes (page 2), Typical Application Circuit (page 11), Power Derating section
(page 13), Package Outline Drawings (pages 14-15), and other minor editorial updates.
Updated Selection Guide (page 2), Power Derating section (page 13), and Package Outline
Drawing branding (page 14).
Updated Supply Current maximum value (page 4) and package drawings (page 14-15)

Copyright 2021, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
Copies of this document are considered uncontrolled documents.

For the latest version of this document, visit our website:

www.allegromicro.com

16
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com