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mt2 Solution
mt2 Solution
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EECS251A ______________________________
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_ Fall 2023 Midterm 2 ______________________________
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xam Location(building and classroom) Name of person behind you↑
Points
o NOT proceed to the next page until you are instructed to do. Only fill out the upper part of the first
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page.
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aron is using a process where an inverter sized for equal rise and fall times has a PMOS width twice that of
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the NMOS. Assume gamma = 1 and that all gates are sized for equal worst-case rise and fall times.
rite an expression for the delay (normalized to tinv)of each stage in terms of the input and/or load
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capacitances labeled in the diagram (C0, C1, …, CL). The labels above each gate indicate the input
capacitance of that gate.Fully simplify any fractionsin your answer. Do not assume anything in
particular about the sizing of the gates.
d0 = 1 + C1/C0
d2 = 3 + 7*C3/C2
d3 = 1 + C4/C3
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b)(5 pts)Consider the logic chain shown below. Eachgate is labeled with its input capacitance.
alculate the relative sizes of all gates such that the total path delay is minimized. Simplify your answers. Be
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sure to enter your answers in the correct order!
E = 1 * 4/3 * 1 * 4/3 * 1
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B = 4 * 1 * 8 * 1 * 1
F = CL / C1 = 18
H = LE * B * F = 1024 = 4^5
h = H^(⅕) = 4
2/C1 = 1
C
C3/C1 = 3
C4/C1 = 3/2
C5/C1 = 9/2
Space for scratch work (only your answers in the blanks will be graded):
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ou need to insert a NOR2 gate somewhere in this chain. Assume that when you insert the NOR2 gate, you
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re-size all the gates for minimum delay. The first gate in the chain will always have an input capacitance Cin=1
unit, regardless of whether it is an inverter or a NOR2 gate.
here should you insert the NOR2 gate for minimum delay? If all options result in the same delay, select
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“Does not matter”. (Circle one)
If the gates are optimally sized, the total delay will be 5 * H^(⅕)) + 4*1 + 2, where H = F * LE * B = CL/C1 *
(5/3).
So the delay is independent of where we place the NOR2 gate.
here should you insert the NOR2 gate for minimum energy consumption? If all options result in the same
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energy, select “Does not matter”. (Circle one)
he logical effort of a NOR2 gate is larger than that of an inverter, so we want it to be sized as small as
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possible (energy is proportional to capacitance). Thus, we should place it first in the chain.
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aúl looks at this circuit, and finds that it is logically equivalent to this logic chain:
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Circuit 2:
aúl wants to know if his seemingly simpler circuit is actually faster. Calculate the input-to-output delay of each
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circuit as a function of CL, assuming all gates are optimally sized for each value of CL. Normalize your
answers to tinv.
our answers should contain numeric constants and CL, but no other variables. Simplify all fractions where
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possible. You do not need to simplify roots; an answer like 4(16/3)⅓ is acceptable.
ualitatively, for which regime is Raúl’s simplified circuit (Circuit 2) faster? Assume all gates are optimally sized
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for each value of CL. (circle one)
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𝑉𝐷𝐷−𝐾𝑉𝐷𝐷
𝑡 = 𝑅𝐶𝑙𝑛( 𝑉𝐷𝐷−𝑍𝑉𝐷𝐷 )
1−𝐾
𝑡 = 𝑅𝐶𝑙𝑛( 1−𝑍 )
) (3 pts)Sir Topham Hatt is working on a chip designedfor locomotive applications. He observes the
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following current drawon his chip over the span of12 seconds. Assume a VDD of5 V.Fill in the tablebelow.
5A*5V = 25 W.
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Figure 1:Current drawn by the chip over time. Average Power @ 12 Seconds (Fill Below):
) (4 pts)Oski Bear is designing a large cell, calledGolden Gate, shown below. Find the activity factors at its
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two outputs. InputsA, B, Care1with probabilityPA, PB, PC.
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) (4 pts)Big Bird has helped to design a new wirelinenetwork for Sesame Street’s digital ASIC department.
b
Fill in the table below.
Critical Assumptions:
● VCTRL is currently set toHIGH.
● The propagation delay will be defined for a50% switchpoint.
● You may ignore all capacitances except those shown.
● NFET on-resistance is2R, PFET on-resistance is4R.Any transistorthat is not onhasinfinite
resistance.
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ln(2)*(25RC)
) (6 pts)
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FOR 251A ONLY! 151A STUDENTS WILL NOT RECEIVE CREDIT FOR THIS PROBLEM.
ski Bear is also working part-time at RISC-Y, where he has developed the Sather Gate. It is a special form of
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inverter implementinghysteresis. Its input and outputcharacteristics and circuit symbol are shown below.
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Critical Assumptions:
● Sather Gatehasinfinite resistancewhen looking infrom the supply port. This is true forall modesof
operation. That is to say, it never loads the powersupply network.
● R1=0.25 ohms, R2 = 1 ohm.
● Digital core and IO behave like ideal current sources. IO draws1A. Digital core draws3A.
● There isground bounceoccurring from some unknowninductance. Hence the ground of theleft
Sather Gate is tied to2V.
● Note that att<0,Voltage A is initially at 2V,andVoltage Bis initially at12 V.
● Note that att=0, VIN of 3V is applied.
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6V
12V
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our coworker designed a complex CMOS logic gate, which is provided below. Your task is to make
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sure the input pins(A, B, C, D) are properly connected to achieve the following complex logic Y =
𝐴𝐶 + 𝐵𝐶 + 𝐴𝐵𝐷.
a) (3 pts)Fill in the signal connected to the gate of each transistor on the box below.
ote: There are multiple combinations of answers(e.g. (4), (5), and (6) can be mixed up), and any
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combination that implements the boolean logic Y = (AC+BC+ABD)’ would be considered correct.
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b) ( 3 pts)In this technology, determine the width of each transistor(M1~M12) so that the gate size is
minimized and the gate has the same pull-up and pull-down strength as a reference inverter. Assume
Wi (i=1~12) is the width of transistor Mi (i=1~12).Your answer should be a single integer OR a fully
simplified fraction. That is, if the answer is 4/3, write “4/3”, neither “1.333” nor “8/6”.Assume
that W1 and W10 are fixed to 4 and 3, respectively.
c) ( 5 pts)Your boss is satisfied with your work, andthey now require you to analyze the CMOS logic gate
that has been designed by your coworker in this technology. The logic gate is provided below, with each
transistor’s width provided. Calculate the logical effort(le) of each input pin (A, B, C, D) and the
parasitic delay(p) of this gate.Your answer shouldbe a single integer OR a fully simplified
fraction. That is, if the answer is 4/3, write “4/3”, neither “1.333” nor “8/6”.
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ote that the given gate has a half of pull-up/pull-down resistance compared to the reference inverter,
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which means that an inverter that has the same pull-up/pull-down resistance as the provided gate
would beWp=2 and Wn=4.
Logical effort of B = 2
a) ( 2 pts)The basic building block of most multi-bitadders and subtractors are single-bit full
adders. The simplest way we can compose multi-bit subtractors is by stringing them together
into a ripple-carry subtractor. How many single-bit full adders are needed to implement a 4-bit
two’s complement ripple-carry subtractor?
N =4
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b) ( 2 pts)How does the worst case delay of a ripple-carrysubtractor relate to the number of bits
N? Express your answer using big O notation.
T = O(_N_
)
c) ( 4 pts)Kogge-Stone adders are carry-lookahead adders,meaning they are based on propagate
and generate bits. Sana first wants to create a basic block that is just like a full adder, but
instead of taking in operands A and B it takes in P = A + B and G = AB. Find expressions for the
outputs S (sum) and Co (carry out) in terms of P, G, and Ci (carry in).
d) ( 6 pts)Since ripple-carry adders are fairly slowfor wider word lengths, Sana now wants to
create a tree carry lookahead adder that groups bits into groups of 3. The first step is to create a
unit cell that computes the propagate and generate bits for a group of 3 bits.
rite simplified sum-of-products expressions for P[2:0] and G[2:0] in terms of P0, P1, P2 (least
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to most significant propagate bits), G0, G1, and G2 (least to most significant generate bits),
where P2:0 and G2:0 are the propagate and generate bits for the group, respectively.
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e) ( 251a only, 4 pts)Sana now wants to build a 16-bit tree adder out of his 3-bit toblerone groups.
He is only allowed to use three-bit carry-merge gates to accomplish this. Please fill in the
missing propagate terms in the expressions below:
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