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A 70 mW 25 Gb/s Quarter-Rate SerDes Transmitter

and Receiver Chipset With 40 dB of Equalization
in 65 nm CMOS Technology
Shuai Yuan, Student Member, IEEE, Liji Wu, Member, IEEE, Ziqiang Wang,
Xuqiang Zheng, Chun Zhang, and Zhihua Wang, Senior Member, IEEE

Abstract—A 25 Gb/s transmitter (TX) and receiver (RX) chipset

designed in a 65 nm CMOS technology is presented. The proposed
quarter-rate TX architecture with divider-less clock generation
can not only guarantee the timing constraint for the highest-speed
serialization, but also save power compared with the conventional
designs. A source-series terminated (SST) driver with a 2-tap feed-
forward equalizer (FFE) and a far-end crosstalk canceller (XTC)
is implemented in the TX chip. The RX chip employs an adap-
tive quarter-rate 2-tap decision-feedback equalizer (DFE) and a
baud-rate clock and data recovery (CDR). The power-efficient
DFE uses the combination of the soft-decision technique and a new
dynamic structure. The DFE adaption logic and baud-rate CDR
logic share a set of error samplers to save power and area. A
hybrid alternate clock scheme is proposed to satisfy the timing
requirement and reduce the power consumption further. The
measurement results show that the TX and RX chipset totally
compensates for a Nyquist channel loss of more than 40 dB, and
consumes only 70 mW from a 1.2 V supply when operating at
25 Gb/s.
Index Terms—CMOS, crosstalk, equalization, low power,
quarter-rate, receiver, SerDes, transmitter.

Fig. 1. Traditional architecture: half-rate TX and quarter-rate RX with DFE

I. I NTRODUCTION adaption.

G LOBAL internet traffic will grow 3.2-fold from 2014 to

2019 with a compound annual growth rate of 26% based
on the estimation in [1]. In this regard the mainstream I/O
system, termed the high-speed SerDes has been widely used in
many applications, such as the computer systems, communica-
tion networks, and in the bulk of consumer electronics. To meet
the growing proliferation of bandwidth demand, the serial link
data rates have been increased to 25–28 Gb/s, which is more
than 75% higher than previous generation of SerDes [2]. They
are defined in several new standards such as OIF CEI-25G/28G,
100 Gb Ethernet, and InfiniBand EDR [3]. Power consumption
and signal integrity are two primary challenges for the design of
a 25 Gb/s high-speed SerDes. Some significant design advances
must be accomplished at both the transmitter (TX) side and the
receiver (RX) side.
Manuscript received December 28, 2015; revised March 4, 2016; accepted
March 21, 2016. This work is supported by National Natural Science Foun-
dation of China (NSFC), No. 61371011. This paper was recommended by
Associate Editor S. Levantino.
The authors are with the Institute of Microelectronics, Tsinghua University,
Beijing, 100084, China (e-mail: yuans07@mails.tsinghua.edu.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2016.2555250
1549-8328 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
Fig. 1 shows a traditional half-rate TX architecture including
a data path and a clock path. In the data path, the source-series
terminated (SST) driver topology is considered as an attractive
solution for low power consumption [4]–[6]. However, few
measures are taken to save the power of the clock path even
though it is usually as high as that of the data path. As presented
in Fig. 1, the half-rate input clock is used for the last stage
serialization, whereas the quarter-rate clock used for the former
stage serialization is generated by the power-hungry divider
circuit. To satisfy the timing constraints of the two clock path
delays, it usually requires 2 sets of clock buffers (BUF#1 and
BUF#2) to match the timing requirements and to drive the large
load simultaneously. However, even with this modification,
it is still difficult to match the delay across PVT variations
when the data rate attains 20 Gb/s and higher. In addition, the
power consumption of the buffers is also significant. Taking, for
example, a 20 Gb/s transmitter with only a 1-stage serialization
as reported by [7], the total power consumption is 57 mW, of
which the clock path consumes 22.5 mW. The power consump-
tion of the divider circuit and clock buffers is 8.5 mW and
7.2 mW respectively. To solve these power consumption prob-
lems, the quarter-rate TX architecture is proposed recently [8],
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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
[9], in which the highest-speed serialization is achieved by
using the quarter-rate clocks exclusively. However, an extra
delay-locked loop (DLL) [8] or a quadrature voltage-controlled
oscillator (VCO) [9] is also required to generate at least
4 phases at the quarter-rate frequency. Moreover, the 4:1 MUX
utilized in the aforementioned quarter-rate TX is far more
difficult to design than the common 2:1 MUX. Therefore, a
quarter-rate SST TX with a novel structure [10] is proposed in
this paper to save the power of both the data and clock paths.
It still uses the 2:1 CMOS MUX, but the divider circuit and the
clock buffers used for matching the delay are eliminated in the
proposed divider-less clock generation. On the other hand,
the channel loss that produces inter-symbol interference (ISI)
will affect the signal integrity at higher frequencies more
severely. The feed-forward equalizer (FFE) is normally em-
ployed as the TX equalization. However, for the multichannel
applications, the crosstalk between the multi-parallel channels
also exacerbates the signal integrity [4], which cannot be re-
solved by the FFE. To mitigate the far-end crosstalk (FEXT)
and the crosstalk-induced jitter (CIJ), several approaches using
a crosstalk canceller (XTC) have been adopted in the designs
of TX [11], [12]. In this paper, a SST driver merged with the
FFE and XTC is proposed, which can compensate for both the
channel loss and FEXT with relatively low power.
For the RX design, a quarter-rate solution (Fig. 1) is consid-
ered to be a good compromise between performance, complex-
ity, and power [4]. Due to the strong equalization ability without
enhancement of the noise and crosstalk, the decision-feedback
equalizer (DFE) has become the most attractive approach at
the RX side. To achieve the low-power implementation of DFE
and at the same time meet the tight requirements of the critical
timing path, soft-decision [13], current-integrating [14], and
charge-steering [15] techniques have been proposed in recent
years. Additionally, the adaption of DFE is also necessary for
diverse transmission channels. However, as shown in Fig. 1,
coexisting with the traditional clock and data recovery (CDR)
by oversampling the input signal, the DFE adaption will result
in more samplers with a large penalty in power and area. Thus
the baud-rate CDR has been introduced by [16], [17]. Because
the phase detection is established from the same data and error
samples used for the DFE adaptation, both the CDR and adap-
tion problems are simultaneously solved without any additional
circuits [16]. Although all of these referenced techniques have
been proposed to minimize power consumption, their effective
combinations have rarely occurred in recently reported works.
For lower power performance, this paper presents a quarter-
rate RX with a baud-rate CDR and an adaptive quarter-rate
2-tap DFE. Both the soft-decision technique and a new dynamic
circuit structure similar to the charge-steering technique are
implemented in the DFE to achieve a power efficiency of
0.24 mW/Gb/s. The power efficiency of the entire RX is less
than 2 mW/Gb/s. In addition, to obtain a more efficient com-
bination of these techniques, a novel hybrid alternate clock
scheme (HACS) [18] is also proposed in this RX.
This paper is organized as follows. Section II describes the
TX architecture and design considerations. Section III presents
the RX implementation including the overall architecture and
the circuit techniques. The measurement results as well as the
Fig. 2. Proposed quarter-rate TX architecture.
performance comparisons are shown in Section IV. Section V
states the conclusion.
II. T RANSMITTER
A. Overall Architecture
Fig. 2 presents the proposed quarter-rate TX architecture
with the divider-less clock generation. The input clock has a
quarter-rate frequency, i.e., 6.25 GHz when the output data
rate is 25 Gb/s. Unlike the recently reported quarter-rate TX,
this TX uses the 2:1 MUX rather than the direct 4:1 MUX to
achieve the data serialization, which means that it does not need
a generator for the multi-phase quarter-rate clocks. Moreover,
the 2:1 MUX is implemented using a CMOS transmission-
gate structure [10] with no static power consumption, which is
also more stable than the 4:1 MUX. Compared with traditional
half-rate TX architecture, the half-rate clock used for the last
stage serialization is generated by the proposed divider-less
clock generation circuit, so that a large number of clock buffers
used for matching the delay as well as the divider circuit are
completely removed. The implementation of the divider-less
clock generation is similar to the design of DLL [19]. The
input quarter-rate clock is delayed by a voltage controlled delay
line (VCDL), which operates at quarter-rate to minimize power
consumption. The phase difference between the input clock and
the delayed clock is detected by an XOR-based phase detector
(PD), these detection results are utilized by a voltage-to-current
(V/I) converter to adaptively adjust the delay of the VCDL.
When the phase delay is adjusted to 90 ◦ , the loop is locked.
At the same time, the output of the PD is just a half-rate
clock meeting the requirement of the last stage serialization.
This divider-less clock generation circuit can save significant
power compared to the conventional clock path, the consequent
shortcomings of which could be some risks of false locking or
duty cycle distortion, therefore some measures are taken in the
circuit designs to address these problems. Two same duty-cycle
correctors (DCC) [10] based on the phase blending technique
[19] are also adopted in the clock path to correct the duty cycle
of both the quarter-rate clock and the half-rate clock.
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YUAN et al.: A 70 mW 25 Gb/s QUARTER-RATE SerDes TRANSMITTER AND RECEIVER CHIPSET WITH 40 dB OF EQUALIZATION 3

Fig. 3. Timing diagram when loop locked.

Fig. 4. Schematic of VCDL.
TABLE I
S IMULATION R ESULTS OF T IMING PARAMETERS

Another significant benefit of introducing this divider-less

clock generation circuit is that the data path can also be greatly
simplified. As shown in Fig. 2, the 4:2 MUX and 2:1 MUX only
have 3 latches in total, whereas the conventional architecture
as presented in Fig. 1 requires 15 latches, which exhibits that
more than 50% power of the data path is saved. Because the
outputs of the pseudo-random-bit-sequence (PRBS) generator
Fig. 5. Simulated VCDL delay versus control voltage across corners.
are hitherto retimed by the quarter-rate clock, the first-stage
retiming latches can be eliminated. The second-stage retiming
latches can also be removed as a result of the adoption of the
divider-less clock generation. The timing diagram when the
loop locked is shown in Fig. 3, tC−Q is clock-to-output delay
of the first-stage selector. The phase difference between the
quarter-rate clock and the half-rate clock is tD , which is just the
delay time of an XOR PD. The hold time of the second-stage
latch is tH , which is expressed as

tH = tC−Q − tD . (1)

Table I shows the post layout simulation results of these 3

timing parameters across different process and temperature
corners. As shown, tH varies from 5.7 ps to 9.5 ps, which is
completely sufficient for the timing constraint of the 25 Gb/s
data transmission when 1 unit interval (UI) is equal to 40 ps.
Moreover, because of the decreased load, the power consump-
tion of the clock path is further reduced.
B. Divider-Less Clock Generation
The proposed divider-less clock generation circuit consists
of a VCDL, an XOR-based PD, and a V/I converter. To
eliminate the harmonic locking or false locking for this loop,
the delay time of the VCDL is designed within a limited
range. The schematic of the VCDL in Fig. 4 is realized by
cascading 3 same delay cells based on the differential buffer
delay stage with a cross-coupled PMOS pair and symmetric
loads. Fig. 5 presents the simulation results of the VCDL delay
across process and temperature variations. When the control
Fig. 6. Schematic of V/I converter.
voltage is from 0 V to 1 V, the simulated time delay and phase
delay of the VCDL at 6.25 GHz range from 25.6 ps to 68.7 ps
and 57.6◦ to 154.6◦ respectively. This delay range ensures that
90◦ is the unique phase locked point.
Fig. 6 shows the schematic of the V/I converter with a start-
up circuit. The start-up circuit is used to establish the initial
control voltage to 0 V so that it can also avoid the false locking
condition. Note that the current asymmetry of the up and down
paths in the V/I may lead to duty cycle distortion of the half-
rate clock, which will influence the jitter performance of the
TX output. Fig. 7 depicts the simulated duty cycle results of
the PD’s output across FF, TT, and SS process corners versus
temperature (sweeps from −40 ◦ C to 85 ◦ C), when the gate
voltage of the tail-current transistor VB is fixed to 580 mV. It
can be seen that the duty cycle is not sensitive to temperature.
However, when the process corner is changed, the duty cycle
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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Fig. 7. Simulated duty cycle of PD’s output versus temperature across corners
when VB = 580 mV.
Fig. 8. Simulated duty cycle of PD’s output versus temperature across corners
with different VB.
Fig. 9. Implementation of SST driver with 2-tap FFE and XTC.
range will deviate from around 50%. Thus, a simple calibration
approach is adopted to alleviate this issue. In this design, VB
is not fixed and can be calibrated through an off-chip digital to
analog converter (DAC). Fig. 8 shows the simulated duty cycle
results of the PD’s output across FF, TT, and SS process corners
versus temperature, when VB is sequentially set to 700 mV,
580 mV, and 500 mV. The duty cycle across extreme variations
varies form 48.2% to 50.9%. This deviation range is within 3%,
so that the following DCC circuit does not need to deal with
large duty cycle distortions.
C. SST Driver With FFE and XTC
The implementation of the SST driver with a 2-tap FFE and
a far-end XTC is shown in Fig. 9, which consists of 25 parallel
connected SST slice units needed to achieve the impedance
TABLE II
S IMULATION R ESULTS OF T ERMINATION I MPEDANCE
Fig. 10. Simulation environment setup.
matching of 50 Ω. Each slice unit includes a pre-driver employ-
ing the CMOS transmission-gate structure and a conventional
output stage. The MOS to poly resistance ratio in the output
stage is set to 1:4. These 25 units are divided into three parts
based on different function. The first part has 4 units, which
are normally connected to the main tap of the FFE. Moreover,
each of these 4 units can be disconnected from the SST driver’s
output to cover the process variations and deviations in the
matched impedance. Table II presents the simulation results of
the termination impedance across the process and temperature
variations. By choosing the total number of the parallel units,
the termination impedance can be calibrated to approximate
50 Ω across different corners. The second part has 15 SST slice
units that belongs to 4 groups with the weighting of 8 ×, 4 ×,
2 ×, 1 ×, respectively, which are controlled by a 4-bit signal
T 3 : 0 to select the connection to the main tap or the post tap.
The remaining 6 units make up the XTC, the principle of which
is similar to that described by [11]. The XTC is calibrated by
a 2-bit signal X1 : 0. When X = 1, the units are connected
to the main tap of the victim lane, meaning that the XTC is
disabled. When X = 0, the units are connected to both the
main tap and the post tap of the adjacent aggressor lane to
compensate for the FEXT.
The equalization value of the FFE can be represented as
 
(M − P )
EQFFE = −20 log (2)
K
where M and P are the number of the slice units connected
to the main tap and the post-cursor tap, respectively, and K =
M + P . Assuming that the XTC is disabled and four units of
the first part are all connected, then K = 25. When T 3 : 0 =
0111, M = 17, and P = 8, thus the equalization value calcu-
lated by (2) is 8.9 dB. The simulation environment setup is
shown in Fig. 10. The ideal capacitors and inductor are used
to mimic the output pads and the bonding wire. A 30 cm
RLGC transmission line model is utilized as a lossy channel.
The termination at the RX side is connected to the high power
rail. Fig. 11 shows the simulated eye diagrams before and after
the channel, when the FFE is disabled (T 3 : 0 = 1111). The
eye after the channel is completely closed without the effect of
FFE. Fig. 12 presents the eye diagrams at the same points when
T 3 : 0 = 0111. The eye after the channel is largely open with
a jitter of 5.7 ps.
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YUAN et al.: A 70 mW 25 Gb/s QUARTER-RATE SerDes TRANSMITTER AND RECEIVER CHIPSET WITH 40 dB OF EQUALIZATION
Fig. 11. Simulated eye diagrams when T 3 : 0 = 1111. (a) TX’s output at
point A when the channel is disconnected. (b) TX’s output after the channel at
the receiver side B.
Fig. 12. Simulated eye diagrams when T 3 : 0 = 0111. (a) TX’s output at
point A when the channel is disconnected. (b) TX’s output after the channel at
the receiver side B.
Fig. 13. Proposed quarter-rate RX architecture.
III. R ECEIVER
A. Overall Architecture
Fig. 13 shows the overall block diagram of the proposed
quarter-rate RX, which also includes a data path and a clock
path. The data path consists primarily of a continuous-time
linear equalizer (CTLE), a quarter-rate DFE and error sampler,
a DFE adaption logic with 3 current digital-to-analog converters
(IDACs) and a baud-rate CDR logic. Due to the benefit of baud-
rate CDR, the edge samplers used in the common oversampling
CDR are saved, which also induces the simplification in the
phase interpolator (PI) based clock path. As shown in Fig. 1,
the traditional quarter-rate RX with the DFE adaption requires
the PI to generate 8-phase clocks. However, the PI in
Fig. 13 only needs to generate 4-phase clocks, the power of
which is reduced considerably. An additional 25%-duty-cycle
clock generator is necessary in the clock path to realize the
HACS with little penalty in power and area. The details of the
proposed HACS will be described in the following paragraphs.
5
Fig. 14. Schematic of proposed CTLE with inductive peaking.
Fig. 15. Frequency response of CTLE. (a) Without inductive peaking. (b) With
inductive peaking.
B. CTLE
The implementation of the CTLE realized with RC degen-
eration and inductive peaking is described in Fig. 14. The
variable resistor consists of a NMOS transistor and a poly
resistor. By controlling the gate voltage VG of the transistor, the
CTLE’s boost gain at high frequency can been continuously cal-
ibrated. The inductive peaking technology is adopted to enlarge
the boost gain without increasing the power. Fig. 15 shows the
simulated frequency response of the proposed CTLE and the
traditional CTLE with no inductive peaking. When VG changes
from 1 V to 400 mV, the traditional CTLE’s boost gain at
12.5 GHz varies from 0.6 dB to 11 dB. By introducing the in-
ductive peaking, the boost gain ranges from 5.5 dB to 16 dB,
which means that an extra 5 dB compensation for the channel
loss can be provided.
C. Low Power DFE
Fig. 16 presents the implementation of the low-power
quarter-rate soft-decision DFE with 4 quarter-lanes ( Quarter_
Lane_0–3). In each quarter-lane, data after the equalization
of the CTLE is firstly sampled by the sample-and-hold (S/H)
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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Fig. 16. Implementation of quarter-rate DFE and error sampler.
Fig. 17. Schematic of dynamic summer block.
circuit. The quarter-rate clock used for S/H has a 25% duty
cycle, which allows the S/H to hold the data for 3 UIs. The
followed summer block employing a new dynamic structure
combines the incoming data with 2 feedback taps. The data flow
after the summer is divided into 2 branches, data sampler lane
(DSL) and error sampler lane (ESL). The DSL branch includes
2-stage dynamic latches and a CMOS SR latch. The first-stage
dynamic latch behaves as a slicer to produce the feedback
return-to-zero (RZ) data rather than the common non-return-to-
zero (NRZ) data. Then the second-stage dynamic latch and the
SR latch make up a RZ-to-NRZ converter. The ESL is similar
to the DSL, the only difference is that an error generator takes
the place of the first-stage latch. The error generator [18] is also
designed based on the same dynamic structure as the summer
of the DFE. The 2 reference levels (VH and VL) are input
and calibrated by the off-chip DACs. On account of the soft-
decision technique, the taps for each quarter-lane are obtained
from other 2 quarter-lanes, which means that it requires only 1
slicer in each DSL branch. Accordingly, the proposed DFE has
realized smaller hardware cost compared with [15] and [20] to
save the power dissipation.
The schematic of the proposed dynamic summer block is
shown in Fig. 17, which is implemented to eliminate static
power consumption thoroughly. The principle of the dynamic
summer is similar to the current-integrating summer [14],
but the clock-controlled NMOS switches (M1–M3) are added
above the tail bias transistors (M4–M7). During the reset phase,
the NMOS switches are off, so that the dynamic summer has no
static power consumption. The dynamic summer also exhibits 3
differences compared with the charge-steering structure in [15].
First, the tail transistors are responsible for adjusting the tap
Fig. 18. Schematic of latch. (a) First-stage latch. (b) Second-stage latch.
Fig. 19. Timing diagram of HACS and simulated eye diagrams.
coefficients instead of the tail capacitors [15], which can save
large chip area and also be convenient for the DFE adaption.
Second, a switch transistor (M8) is added to ensure the equal of
the output nodes (A_N + and A_N −) in the reset phase. Third,
the main tap is controlled by both Vmain and Vconst, the former
is created by the adaption logic whereas the latter is fixed. To
guarantee the amplitude range and make slight adjustment, the
transistor size ratio between M4 and M5 is set to 1:3.
As presented in Fig. 18(a), the first-stage dynamic latch is
similar to the summer block, which is used as the first-stage
slicer. The second-stage latch (Fig. 18(b)) has a complete clock-
controlled dynamic structure, whose output can be rushed to
the full swing. So this structure is employed in the RZ-to-NRZ
converter with a CMOS SR latch.
D. Proposed HACS
Note that, as the feedback tap, the output of the first-stage
dynamic latch is in the RZ form. How to use the RZ form to
achieve the soft-decision is a new design challenge. To realize
the combination of soft-decision and dynamic sampling, we
propose a hybrid alternate clock scheme. As shown in Fig. 16,
there are two sets of clocks in the DFE and error samplers,
CLK_N with a 25% duty cycle and CK_N with a 50% duty
cycle. The timing diagram of the HACS is reported in Fig. 19.
Taking Quarter_Lane_0 for example, CLK_0 controls the S/H
to sample the input data. When the CLK_0 is low, the summer
block is active. The first-stage latch’s output in the Quarter_
Lane_3 and Quarter_Lane_2 are also generated during this
phase, they behaves as the first tap and the second tap with three
quarters effective value. The output of the summer A_0n is just
in time sampled by the first-stage latch using the 90◦ shifted
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YUAN et al.: A 70 mW 25 Gb/s QUARTER-RATE SerDes TRANSMITTER AND RECEIVER CHIPSET WITH 40 dB OF EQUALIZATION
Fig. 20. Block diagram of CDR logic.
Fig. 21. Block diagram of DFE adaption logic.
Fig. 22. Definition of error. (a) Error in CDR. (b) Error in DFE adaption.
clock CLK_1’. At last, the second-stage latch uses the 50%-
duty-cycle CK_2 to amplify the signal. These two sets of clocks
are alternate from Quarter_Lane_0 to Quarter_Lane_3. The
proposed HACS provides 2 merits. First, to ensure the accurate
clock phase and adequate timing margin for the soft-decision
architecture. Second, to balance the load of the different clocks
and save the power of the clock distribution. The simulated
output eye diagrams of each part are also presented in Fig. 19,
in which both the eye height and the width of effective value
are indicated.
E. Baud-Rate CDR and DFE Adaption
Fig. 20 shows the block diagram of the CDR digital logic,
which includes a PD, a majority voter, a bandwidth controller
and a digital filter. The output of the digital filter controls the PI
to generate 4-phase clocks. The 2-bit external signal BW_CTRL
controls the bandwidth controller to calibrate the bandwidth of
the CDR loop. The DFE adaption logic (Fig. 21) is designed
based on the sign-sign least-mean-square (SS-LMS) algorithm,
and the structure is similar to the CDR logic. Differently,
the SS-LMS logic takes place of the PD, and at the end an
amplitude limiter is added to ensure the tap coefficient of the
DEF within a reasonable range. The different 2-bit external
signal controls the bandwidth of the DFE adaption loop.
Note that the actual required error signals in baud-rate CDR
logic (E) and SS-LMS logic (E  ) have a little different, the
definition of which are shown in Fig. 22(a) and Fig. 22(b) re-
spectively. The relationship between E  and E is given by
E  = −(D ∗ E).
7
Fig. 23. (a) Implementation of PD. (b) Implementation of SS-LMS logic.
Fig. 24. TX die micrograph.
The principles of the PD in baud-rate CDR [16] and the
SS-LMS logic in DFE adaption are also similar, which can be
described as
ΔPn = Dn−1 ∗ Dn ∗ (En − En−1 ) (4)
ΔH(k)n = − (Dn−k ∗ En ) = Dn−k ∗ Dn ∗ En (5)
where ΔPn is the phase error factor for the baud-rate CDR, and
ΔH(k)n means the coefficient error factor of the tap − k for the
DFE adaption. According to (4) and (5), the implementation of
the PD and SS-LMS logic are exhibited in Fig. 23(a) and (b)
separately. In the design of PD, 2 additional XORs are em-
ployed to accelerate the process of the phase detection.
IV. M EASUREMENTS
Both the TX chip and the RX chip are fabricated in a 65 nm
standard CMOS technology with 9 metal layers. The chips are
directly wire-bonded to the printed circuit board (PCB) for the
measurements.
A. Transmitter Chip
The TX die micrograph is shown in Fig. 24. To achieve a
multi-channel application and test the XTC function, this TX
prototype is designed with 4 data-channels, 2 PRBS generators,
and a clock path. The output of each data-channel is single-
ended. The PRBS generator is implemented on the basis of the
parallel structure, which generates 8-lane PRBS-7 data with dif-
ferent phases to make sure that the output of each data-channel
still owns the PRBS-7 pattern. The whole chip measures
1.01 mm × 0.69 mm including the decoupling capacitors and
I/O pads. The active area is 0.38 mm × 0.25 mm.
Fig. 25 depicts the simulated power breakdown for TX.
The 4-channel TX consumes a total power of 87 mW from
(3) a supply of 1.2 V when working at 25 Gb/s, which means
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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS
Fig. 25. TX power breakdown.
Fig. 26. (a) Testing PCB. (b) Measured channel loss and eye diagram of
20 Gb/s single-ended TX output without FFE and XTC.
Fig. 27. (a) Measured eye diagram of 20 Gb/s single-ended TX output with
FFE but without XTC. (b) Measured eye diagram of 20 Gb/s single-ended TX
output with both FFE and XTC.
that the average power consumption for each channel is less
than 22 mW. The proposed divider-less clock generation circuit
(including VCDL, PD, and V/I) consumes only 4.7 mW.
As shown in Fig. 26(a), the 2-inch coupled micro-strip lines
are realized as the test channels with the spacing of 30 mil.
Fig. 26(b) shows that the measured channel loss at 12.5GHz is
8.9 dB. A Keysight DSOX93204A Infiniium oscilloscope with
32 GHz bandwidth is used to measure the eye diagrams and
the jitter decomposition. Fig. 26(b) also shows the measured
20 Gb/s eye diagram of the TX output without the FFE and XTC.
The eye is completely closed. Fig. 27(a) presents the measured
eye diagram of the 20 Gb/s TX output when the FFE is enabled
but the XTC is disabled. The total jitter (TJ) is 36 ps and eye
height is 85 mV. The data dependent jitter (DDJ) is 19.4 ps. The
measured eye diagram of the 20 Gb/s TX output when the FFE
and XTC are both active is shown in Fig. 27(b). The TJ and
eye height is improved by 8.2 ps and 95 mV, respectively. The
Fig. 28. Measured eye diagrams of 22 Gb/s single-ended TX output with both
FFE and XTC. (a) VB = 500 mV. (b) VB = 600 mV.
Fig. 29. (a) Measured eye diagram of 24 Gb/s single-ended TX output with
both FFE and XTC. (b) Measured eye diagram of 25 Gb/s single-ended TX
output with both FFE and XTC.
DDJ is reduced by 7.2 ps because of the proposed XTC. On this
occasion, T 3 : 0 = 1000 and X1 : 0 = 01.
The measured 22 Gb/s eye diagrams are presented in
Fig. 28(a) and (b). When the VB of V/I is 500 mV [Fig. 28(a)],
the TJ is 31.3 ps with 1.57 ps of duty cycle distortion (DCD).
Then VB is calibrated to 600 mV (Fig. 28(b)), the DCD is
decreased to only 40 fs and the TJ is also improved by 0.8 ps.
Actually, this TX is able to operate up to 25 Gb/s. Fig. 29(a)
and (b) exhibit the eye diagrams at 24 Gb/s and 25 Gb/s,
respectively. Due to the single-ended output structure and more
serious channel loss and crosstalk, both the time margin perfor-
mance and the voltage margin performance are not very ideal
even though the measured bit-error-rate (BER) is still smaller
than 1e-12. If adopting the differential output structure with less
severe channel, the eye diagram at 25 Gb/s will be obviously
improved.
B. Receiver Chip
Fig. 30 shows the RX die micrograph, which measures
1.512 mm × 1.276 mm including all the test circuits, de-
coupling MOS capacitors and I/O pads. The active area is
0.52 mm × 0.35 mm. Fig. 31 is the simulated power breakdown
when the RX operates at 25 Gb/s. The total power consumption
is 48 mW, among which the low-power DFE draws only 6 mW,
thus the power efficiency of the DFE is 0.24 mW/Gb/s. A
Keysight E5071C ENA network analyzer is used to measure the
channel loss, and a Tektronix BSA286C 28.6 Gb/s BERTScope
is used to test the BER performance.
As presented in Fig. 32, the test channel including the
bonding wire, PCB trace, SMA connector, and cable has a loss
of 33.8 dB at the Nyquist frequency (12.5 GHz). The eye of the
received 25 Gb/s PRBS-7 data after this channel is completely
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
YUAN et al.: A 70 mW 25 Gb/s QUARTER-RATE SerDes TRANSMITTER AND RECEIVER CHIPSET WITH 40 dB OF EQUALIZATION
Fig. 30. RX die micrograph.
Fig. 31. RX power breakdown.
Fig. 32. Measured channel loss and eye diagram of received 25 Gb/s data after
the channel.
closed. Fig. 33 shows the eye diagrams of the 3.125 GHz
recovered clock and the 6.25 Gb/s dumuxed data. The measure
TJ of the recovered clock is 23 ps, with a random RMS jitter of
1 ps. The TJ of the 6.25 Gb/s dumuxed data is 52 ps.
The RX performance is also demonstrated by the jitter tol-
erance test at 25 Gb/s as shown in Fig. 34, along with the
CEI-25G/28G JTOL mask [21]. Measured at the BER threshold
of 1e-9, the out-of-band jitter tolerance at 100 MHz is 0.22 UI.
The BER bathtub curves are measured after turning off the CDR
logic. As indicated in Fig. 35, at first the DFE is disabled and the
CTLE is maximally opened (VG = 400 mV). The measured
BER is above 1e-8. Then the adaptive DFE is active so that the
eye opening reaches 0.42 UI for BER = 1e − 12.
9
Fig. 33. (a) Measured eye diagram of the recovered clock at 3.125 GHz.
(b) Measured eye diagram of the demuxed data at 6.25 Gb/s.
Fig. 34. Measured jitter tolerance result.
Fig. 35. Measured BER bathtub curve.
C. Performance Comparison
Table III summarizes the measured performance of the TX
described in this paper, in comparison to some recently pub-
lished similar designs [5]–[8]. The one-channel power con-
sumption of the TX working at 25 Gb/s is 21.8 mW, and the
power efficiency is reduced by at least 17% compared with
the other state-of-the-art designs. Additionally, the FFE and
XTC are merged together with the SST driver in this work
to compensate for both the ISI and FEXT. Table IV is the
RX performance summary and comparison with other similar
designs [14]–[16], [20], [22], which indicates that the RX
implemented in this paper can compensate for the most serious
channel loss. The eye opening and the DFE power efficiency
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
10
TABLE III
TX P ERFORMANCE S UMMARY AND C OMPARISON
TABLE IV
RX P ERFORMANCE S UMMARY AND C OMPARISON
are also comparable to the others. The power efficiency of the
entire RX is 1.92 mW/Gb/s, which is improved by at least 47%
compared with the other state-of-the-art designs.
V. C ONCLUSION
In this paper, we have demonstrated a 25 Gb/s quarter-rate
SerDes transmitter and receiver chipset fabricated in a 65 nm
CMOS technology. Some novel structures and clock schemes
are developed for the purpose of low power and intensive
equalization ability. The total power consumption of the TX
and RX chipset is approximately 70 mW (TX: 21.8 mW, RX:
48 mW) at 25 Gb/s, which compensates for more than 40 dB
channel loss (TX: 8.9 dB, RX: 33.8 dB). The power efficiency
and equalization performance are better than the reported state-
of-the-art works.
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Shuai Yuan (S’15) was born in Jilin, China. He
received the B.S. degree from the Department
of Electronic Engineering, Tsinghua University,
Beijing, China, in 2011. He is now working toward
the Ph.D. degree at the Institute of Microelectron-
ics, Tsinghua University, China. His research inter-
ests include high-speed wireline transceiver and low
power equalizer.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
YUAN et al.: A 70 mW 25 Gb/s QUARTER-RATE SerDes TRANSMITTER AND RECEIVER CHIPSET WITH 40 dB OF EQUALIZATION
Liji Wu (M’95) received the B.S., M.S., and Ph.D.
degrees in electronic engineering from Tsinghua
University, Beijing, China, in 1988, 1991, and 1997,
respectively.
From April 1997 to May 2000, he worked in the
Center for Advanced Technology in Telecommunica-
tions, Polytechnic Institute of New York University
(NYU-Poly), Brooklyn, NY, USA, as a Postdoctoral
Fellow, worked on design and implementation of
high-speed control circuits and systems utilized in
WDM ATM Multicast optical switching systems
sponsored by DARPA. Then he worked in high-tech industry in the U.S. for
more than 4 years, including TyCom Laboratories (former AT&T Bell Labs on
Undersea Optical Fiber Communications), Eatontown, NJ, USA, as a Senior
Member of Technical Staff. He received Tsinghua University Outstanding
Graduate Award and Medal in 1988. He joined Tsinghua University as a Full-
Time Faculty since 2005. He is a Board Member of Shanghai Pudong Science
& Technology Association, Shanghai, China since 2006.
Ziqiang Wang was born in 1975 in Beijing, China.
He received the B.S. and Ph.D. degrees from the
Department of Electronic Engineering, Tsinghua
University, Beijing, China, in 1999 and 2006, respec-
tively. He works as a Research Assistant in the Insti-
tute of Microelectronics, Tsinghua University, after
Doctor graduation. From 2015, he is an Associate
Professor of the Institute of Microelectronics. His
research interest is analog circuit design.
Xuqiang Zheng received the B.S. and M.S. degrees
from Central South University, Hunan, China. He is
now working as an engineer in Tsinghua University,
China. His research interest is high-speed SerDes
design and analog to digital converter.
11
Chun Zhang was born in 1972 in Jilin province,
China. He received the B.S. and Ph.D. degrees from
the Department of Electronic Engineering, Tsinghua
University, Beijing, China, in 1995 and 2000, re-
spectively. He works in Tsinghua University since
2000 till now. He worked in the Department of Elec-
tronic Engineering from 2000 to 2004. From 2005,
he is an Associate Professor of the Institute of Micro-
electronics. His research interests include mixed
signal integrated circuits and systems, embedded
microprocessor design, digital signal processing, and
radio frequency identification.
Zhihua Wang (M’99–SM’04) received the B.S.,
M.S., and Ph.D. degrees in electronic engineering
from Tsinghua University, Beijing, China, in 1983,
1985, and 1990, respectively.
In 1983, he joined the faculty at Tsinghua Uni-
versity, where he is a full Professor since 1997 and
Deputy Director of Institute of Microelectronics
since 2000. From 1992 to 1993, he was a visiting
scholar at Carnegie Mellon University. From 1993 to
1994, he was a Visiting Researcher at KU Leuven,
Belgium. His current research mainly focuses on
CMOS RF IC and biomedical applications. His ongoing work includes RFID,
PLL, low-power wireless transceivers, and smart clinic equipment with combi-
nation of leading edge CMOS RFIC and digital imaging processing techniques.
Prof. Wang has served as Deputy Chairman of Beijing Semiconductor
Industries Association and ASIC Society of Chinese Institute of Communi-
cation, as well as Deputy Secretary General of Integrated Circuit Society in
China Semiconductor Industries Association. He had been one of the chief
scientists of the China Ministry of Science and Technology serves on the
expert committee of the National High Technology Research and Development
Program of China (863 Program) in the area of information science and
technologies from 2007 to 2011. He had been an official member of China
Committee for the Union Radio-Scientifique Internationale (URSI) during 2000
to 2010. He was the chairman of IEEE Solid-State Circuit Society Beijing
Chapter during 1999–2009. He has been a Technologies Program Committee
member of ISSCC (International Solid-State Circuit Conference) during 2005
to 2011. He is an Associate Editor for IEEE T RANSACTIONS ON B IOMEDICAL
C IRCUITS AND S YSTEMS and IEEE T RANSACTIONS ON C IRCUITS AND
S YSTEMS —PART II: E XPRESS B RIEFS .