Dept of ECE VLSI Design [18EC72]

Module - 1

Introduction

Syllabus:
Introduction: A Brief History, MOS Transistors, CMOS Logic (1.1 to 1.4 of TEXT2)
MOS Transistor Theory: Introduction, Long-channel I-V Characteristics, Non-ideal I-V
Effects, DC Transfer Characteristics (2.1, 2.2, 2.4 and 2.5 of TEXT2).

Textbooks:
1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf
Leblebici, Third Edition, Tata McGraw-Hill.
2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste and
David Money Harris, 4th Edition, Pearson Education.

A Brief History:
 In 1958, Jack Kilby built the first integrated circuit flip-flop with two transistors at Texas
Instruments. In 2008, Intel’s Itanium microprocessor contained more than 2 billion
transistors and a 16 Gb Flash memory contained more than 4 billion transistors.
 This corresponds to a compound annual growth rate of 53% over 50 years. No other
technology in history has sustained such a high growth rate lasting for so long.
 This incredible growth has come from steady miniaturization of transistors and
improvements in manufacturing processes.
 Most other fields of engineering involve tradeoffs between performance, power, and
price. However, as transistors become smaller, they also become faster, dissipate less
power, and are cheaper to manufacture. This synergy has not only revolutionized
electronics, but also society at large.

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 During the first half of the twentieth century, electronic circuits used large, expensive,
power-hungry, and unreliable vacuum tubes. In 1947, John Bardeen and Walter Brattain
built the first functioning point contact transistor at Bell Laboratories.
 It is called as Transistor, T-R-A-N-S-I-S-T-O-R, because it is a resistor or semiconductor
device which can amplify electrical signals as they are transferred through it from input
to output terminals.
 Ten years later, Jack Kilby at Texas Instruments realized the potential for miniaturization
if multiple transistors could be built on one piece of silicon.
 Figure 1.2(b) shows his first prototype of an integrated circuit, constructed from a
germanium slice and gold wires.
 Transistors can be viewed as electrically controlled switches with a control terminal and
two other terminals that are connected or disconnected depending on the voltage or
current applied to the control.
 Soon after inventing the point contact transistor, Bell Labs developed the bipolar junction
transistor.
 Bipolar transistors were more reliable, less noisy, and more power-efficient. Early
integrated circuits primarily used bipolar transistors.
 Bipolar transistors require a small current into the control (base) terminal to switch much
larger currents between the other two (emitter and collector) terminals.
 The quiescent power dissipated by these base currents, drawn even when the circuit is not
switching, limits the maximum number of transistors that can be integrated onto a single
die.
 By the 1960s, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) began to
enter production. MOSFETs offer the compelling advantage that they draw almost zero
control current while idle.
 They come in two flavors: nMOS and pMOS, using n-type and p-type silicon,
respectively.
 In 1963, Frank Wanlass at Fairchild described the first logic gates using MOSFETs.
Fairchild’s gates used both nMOS and pMOS transistors, earning the name
Complementary Metal Oxide Semiconductor, or CMOS. The circuits used discrete

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transistors but consumed only nanowatts of power, six orders of magnitude less than their
bipolar counterparts.
 With the development of the silicon planar process, MOS integrated circuits became
attractive for their low cost because each transistor occupied less area and the fabrication
process was simpler.
 Early commercial processes used only pMOS transistors and suffered from poor
performance, yield, and reliability.
 Processes using nMOS transistors became common in the 1970s. Intel pioneered nMOS
technology with its 1101 256-bit static random access memory and 4004 4-bit
microprocessor.
 While the nMOS process was less expensive than CMOS, nMOS logic gates still
consumed power while idle.
 Power consumption became a major issue in the 1980s as hundreds of thousands of
transistors were integrated onto a single die.
 CMOS processes were widely adopted and have essentially replaced nMOS and bipolar
processes for nearly all digital logic applications.
 In 1965, Gordon Moore observed that plotting the number of transistors that can be most
economically manufactured on a chip gives a straight line on a semilogarithmic scale.
 At the time, he found transistor count doubling every 18 months. This observation has
been called Moore’s Law and has become a self-fulfilling prophecy.
 Fig.1.1 shows that the number of transistors in Intel microprocessors has doubled every
26 months since the invention of the 4004.
 Moore’s Law is driven primarily by scaling down the size of transistors and, to a minor
extent, by building larger chips.
 The level of integration of chips has been classified as small-scale, medium-scale, large-
scale, and very largescale.
 Small-scale integration (SSI) circuits, such as the 7404 inverter, have fewer than 10 gates,
with roughly half a dozen transistors per gate.
 Medium-scale integration (MSI) circuits, such as the 74161 counter, have up to 1000
gates.

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 Large-scale integration (LSI) circuits, such as simple 8-bit microprocessors, have up to

10,000 gates.
 Very-Large-scale integration (VLSI) circuits, have up to 1,00,000 gates.
 Ultra-Large-scale integration (ULSI) circuits, have more 1,00,000 gates.

Fig.1.1: Transistors in Intel microprocessors

 The feature size of a CMOS manufacturing process refers to the minimum dimension of a
transistor that can be reliably built.
 The 4004 had a feature size of 10µm in 1971. The Core 2 Duo had a feature size of 45
nm in 2008.
 Manufacturers introduce a new process generation (also called a technology node) every
2–3 years with a 30% smaller feature size to pack twice as many transistors in the same
area.
 Fig.1.6 shows the progression of process generations. Feature sizes down to 0.25µm are
generally specified in microns (10 – 6 m), while smaller feature sizes are expressed in
nanometers (10–9 m).

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 Effects that were relatively minor in micron processes, such as transistor leakage,
variations in characteristics of adjacent transistors, and wire resistance, are of great
significance in nanometer processes.

Fig.1.2: MOS transistor Process generations

 In the early 1990s, experts agreed that scaling would continue for at least a decade but
that beyond that point the future was murky. In 2009, we still believe that Moore’s Law
will continue for at least another decade.

MOS Transistors
 Silicon (Si) forms the basic starting material for most integrated circuits. Silicon is a
group IV element of the periodic table, so it forms covalent bonds with four adjacent
atoms, as shown in Fig.1.3 (a).
 Valence electrons of silicon are involved in chemical bonds; pure silicon is a poor
conductor.

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Fig.1.3: Silicon and dopant atoms

 The conductivity can be raised by introducing small amounts of impurities, called
dopants, into the silicon lattice.
 A dopant from Group V of the periodic table, such as arsenic, has five valence electrons.
It replaces a silicon atom in the lattice and still bonds to four neighbors, so the fifth
valence electron is loosely bound to the arsenic atom, as shown in fig.1.3 (b).
 Thermal vibration of the lattice at room temperature is enough to set the electron free to
move, leaving a positively charged As+ ion and a free electron.
 The free electron can carry current so the conductivity is higher. We call this an n-type
semiconductor because the free carriers are negatively charged electrons.
 Similarly, a dopant from Group III of the periodic table, such as boron, has three valence
electrons, as shown in fig.1.3 (c). The dopant atom can borrow an electron from a
neighboring silicon atom, which in turn becomes short by one electron. That atom in turn
can borrow an electron, and so forth, so the missing electron, or hole, can propagate
about the lattice. The hole acts as a positive carrier so we call this a p-type
semiconductor.
 A Metal-Oxide-Semiconductor (MOS) structure is created by superimposing several
layers of conducting and insulating materials to form a sandwich-like structure.
 These structures are manufactured using a series of chemical processing steps involving
oxidation of the silicon, selective introduction of dopants, and deposition and etching of
metal wires and contacts.
 CMOS technology provides two types of transistors (also called devices): an n-type
transistor (nMOS) and a p-type transistor (pMOS) as shown in fig.1.4.
 Transistor operation is controlled by electric fields so the devices are also called Metal
Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply FETs.

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Fig.1.4: MOSFET
 The n+ and p+ regions in fig.1.4 indicate heavily doped n- type or p-type silicon.
 Each transistor consists of a stack of the conducting gate, an insulating layer of silicon
dioxide (SiO2), and the silicon wafer, also called the substrate or body or bulk.
 Gates of early transistors were built from metal, so the stack was called metal-oxide-
semiconductor, or MOS. Since the 1970s, the gate has been formed from polycrystalline
silicon (known as polysilicon).
 An nMOS transistor is built with a p-type body and has regions of n-type semiconductor
adjacent to the gate called the source and drain.
 A pMOS transistor is just the opposite, consisting of p-type source and drain regions with
an n-type body.
 The gate is a control input: It affects the flow of electrical current between the source and
drain. The body is generally grounded so the pn junctions of the source and drain to body
are reverse-biased.
 If the gate is also grounded, no current flows through the reverse-biased junctions. Hence,
we say the transistor is OFF.
 If the gate voltage is raised, it creates an electric field that starts to attract free electrons to
the underside of the Si–SiO2 interface. If the voltage is raised enough, the electrons
outnumber the holes and a thin region under the gate called the channel is inverted to act
as an n-type semiconductor. Hence, a conducting path of electron carriers is formed from
source to drain and current can flow. Now the transistor is ON.
 For a pMOS transistor, the situation is again reversed. The body is held at a positive
voltage. When the gate is also at a positive voltage, the source and drain junctions are
reverse-biased and no current flows, so the transistor is OFF.

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 When the gate voltage is lowered, positive charges are attracted to the underside of the Si
–SiO2 interface.
 A sufficiently low gate voltage inverts the channel and a conducting path of positive
carriers is formed from source to drain, so the transistor is ON.

MOS Transistor theory:

Structure of MOS layer

 Metal Oxide Semiconductor comprises of three layers as shown in the fig.1.5.
 The top layer of the structure is a good conductor called the gate. Early transistors used
metal gates, now polysilicon, i.e., silicon formed from many small crystals
 The middle layer is a very thin insulating film of SiO2 called the gate oxide.
 The bottom layer is the doped silicon body. The fig.1.5 shows a p-type body in which the
carriers are holes.

Metal

Oxide

p - Semiconductor

Fig.1.5: MOS layer

 The MOS transistor is a majority-carrier device in which the current in a conducting
channel between the source and drain is controlled by a voltage applied to the gate.
 In an nMOS transistor, the majority carriers are electrons; in a pMOS transistor, the
majority carriers are holes.
 The behavior of MOS transistors can be understood by first examining an isolated MOS
structure with a gate and body but no source or drain.
 The body is grounded and a voltage is applied to the gate. The gate oxide is a good
insulator, so almost zero current flows from the gate to the body.

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 A negative voltage is applied to the gate, so there is negative charge on the gate. The
positively charged holes are attracted to the region beneath the gate. This is called the
accumulation mode as shown in fig.1.6 (a).
 In fig.1.6 (b), a small positive voltage is applied to the gate, resulting in some positive
charge on the gate. The holes in the body are repelled from the region directly beneath
the gate, resulting in a depletion region forming below the gate.
 In fig.1.6 (c), a higher positive potential exceeding a critical threshold voltage Vt is
applied, attracting more positive charge to the gate. The holes are repelled further and
some free electrons in the body are attracted to the region beneath the gate. This
conductive layer of electrons in the p-type body is called the inversion layer.

Fig.1.6: MOS structure demonstrating (a) accumulation, (b) depletion, and (c) inversion
 The threshold voltage depends on the number of dopants in the body and the thickness
tox of the oxide.

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Structure of nMOS transistor

 nMOS enhancement transistor as shown in the fig.1.7 consists of lightly doped p-
substrate.
 Two highly doped n-type regions are formed in the p-substrate by diffusing n-impurities.
These regions forms the source and drain terminal of the transistor.
 A thin layer of silicon dioxide (SiO2) is grown on the surface of the substrate which acts
as an excellent insulator.
 A polysilicon gate is deposited above the substrate and is separated from the substrate by
an oxide layer.
 Metal contacts are made for gate (G), source (S), drain (D) and substrate (B) regions.
 Substrate (also known as body) region forms pn junctions with source and drain region
and these pn junctions are reverse biased.

Gate

Source Drain
Polysilicon

n+ n+ Diffusion Region
Depletion Region

Oxide
p-substrate layer

Metal

Body
Fig.1.7: Structure of nMOS enhancement transistor

Operation of nMOS transistor

 For transistor operation a channel should be established between source and drain for the
conduction of the majority carries.
 To form a channel a positive gate voltage should be applied with respect to source (i.e.
gate to source voltage Vgs).

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 When a positive gate voltage (Vgs) is applied, an electric field is established between the
gate and the substrate which helps for the inversion of the charges at the gate-substrate
interface.
 The holes repel from the interface of gate-substrate region and the electrons from the n+
source and n+ drain region gets attracted towards the interface of gate-substrate region.
 When sufficient number of electrons accumulates in interface of gate-substrate region, an
n-region will be formed between n+ source and n+ drain which acts as a channel for the
current conduction between drain and source.
 The channel is created by inverting the interface of gate-substrate region from p-type to
n-type. Hence this induced channel is also called as an inversion layer.
 The amount of gate voltage which is required to create a conducting channel between n+
source and n+ drain is called threshold voltage (Vt).

S D

n+ n+

p-substrate

Vgs < Vt
Fig.1.8: Cutoff region of nMOS transistor
 Hence the region of operation in which the gate to source voltage (Vgs) is less than
threshold voltage (Vt) is known as cutoff region as shown in fig.1.8 where the MOS
transistor is in off state.
 Now keep the gate to source voltage (Vgs) constant and apply a small amount of positive
voltage to drain with respect source (Vds). An electric field is established between the
drain and the source, acting towards source terminal which supplies energy to the
electrons present at the source.

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 The electrons move towards drain, which causes a small amount of current Id to flow in
the channel.
 The current Id will flow from drain to source which is opposite to the flow of electrons.
 The magnitude of current Id depends on the density of electrons in the channel which in
turn depends on the magnitude of Vgs.
 The current Id will increase if magnitude of Vgs is increased above Vt, This voltage is
called as excess gate voltage (Vgs - Vt) also called as overdrive voltage (VOV).
 The voltage Vds appears as a voltage drop across the length of the channel. The voltage
between the gate and the points along the channel decreases from Vgs at the source end to
Vgs – Vds at the drain end.
 Since the channel depth depends on this voltage, we find that the channel is no longer of
uniform depth; rather, the channel will take the tapered form.
 As Vds is increased further, the channel becomes more tapered and its resistance increases
correspondingly.

G G

S D S D

n+ n+ n+ n+

p-substrate p-substrate

B B

Vgs ≥ Vt; Vds = 0 Vgs ≥ Vt; Vds < Vgs - Vt

Fig.1.9: Linear region of nMOS transistor
 Thus the Id - Vds curve does not continue as a straight line but bends eventually as shown
in fig.1.11.

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G G

S D S D

n+ n+ n+ n+

p-substrate p-substrate

B B

Vgs ≥ Vt; Vds = Vgs - Vt Vgs ≥ Vt; Vds > Vgs - Vt

Fig.1.10: Saturation region of nMOS transistor

Fig.1.11: Id - Vds characteristics of nMOS with regions of operations

 When Vds is increased further it reduces the voltage between gate and channel at the drain
end to Vt, i.e, Vgd = Vt, or Vgs – Vds = Vt or Vds = Vgs - Vt, the channel depth at the drain
end decreases to almost zero, and the channel is now said to be pinched off.
 Increasing Vds further shifts the pinch-off point towards the source region, and the current
through the channel remains constant at the value obtained for Vds = Vgs - Vt.
 The drain current thus saturates at this value, and the MOSFET is said to have entered the
saturation region of operation.
 The voltage Vds at which saturation occurs is denoted Vdssat and Vdssat = Vgs - Vt.

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 The device operates in the saturation region if Vds ≥ Vdssat as shown in the fig1.10 and
the device operates in linear region (triode region) if Vds < Vdssat as shown in the
fig1.9.

Structure of pMOS transistor

 pMOS enhancement transistor is as shown in the fig.1.12 which consists of lightly doped
n-substrate.
 Two highly doped p-type regions are formed in the n-substrate by diffusing p-impurities.
These regions forms the source and drain terminal of the transistor.
 A thin layer of silicon dioxide (SiO2) is grown on the surface of the substrate which acts
as an excellent insulator.
 A polysilicon gate is deposited above the substrate and is separated from the substrate by
an oxide layer.
 Metal contacts are made for gate (G), source (S), drain (D) and substrate (B) regions.
 Substrate (also known as body) region forms pn junctions with source and drain region
and these pn junctions are reverse biased.

Gate

Source Drain
Polysilicon

p+ p+ Diffusion Region
Depletion Region

Oxide
n-substrate layer

Metal

Body
Fig.1.12: Structure of pMOS enhancement transistor

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Operation of pMOS transistor

 For an enhancement mode operation, the majority carries should be enhanced first for the
conduction to take place.
 A channel should be established between source and drain for the conduction to take
place.
 To form a channel a negative gate voltage should be applied with respect to source (i.e.
gate to source voltage Vgs).
 When a negative gate voltage (Vgs) with source connected to ground is applied, an
electric field is established between the gate and the substrate. The vertical component of
the electric field helps for the inversion of the charges at the gate-substrate interface.
 The electrons repel from the interface of gate-substrate region and the holes from the p+
source and p+ drain region gets attracted towards the interface of gate-substrate region.
 When sufficient number of holes accumulates at the interface of gate-substrate region, a
p-region will be formed between p+ source and p+ drain which acts as a channel for the
current conduction from drain to source.
 The channel is created by inverting the interface of gate-substrate region from n-type to
p-type. Hence this induced channel is also called as an inversion layer.
 The amount of gate voltage which is required to create a conducting channel between p+
source and p+ drain is called threshold voltage (Vt).

S D

p+ p+

n-substrate

Vgs > Vt
Fig.1.13: Cutoff region of pMOS transistor

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 Hence the region of operation in which the gate to source voltage (Vgs) is greater
than threshold voltage (Vt) is known as cutoff region as shown in fig1.13 where the
MOS transistor is in off state.
 Now keep the gate to source voltage (Vgs) constant and apply a small amount of negative
voltage to drain with respect source (Vds). An electric field is established between the
drain and the source, acting towards source terminal which supplies energy to the holes
present in the source.
 The holes move towards drain, which causes a small amount of current Id to flow in the
channel.
 The current Id will flow from source to drain which is opposite to the flow of electrons.
 The magnitude of current Id depends on the density of electrons in the channel which in
turn depends on the magnitude of Vgs.
 The current Id will decrease if magnitude of Vgs is decreased below Vt, This voltage is
called as excess gate voltage (Vgs - Vt), also called as overdrive voltage (Vov).
 When Vgs is decreased below Vt, it enhances the channel, hence it is called as
enhancement mode transistor. The conductance of the channel is proportional to the
excess gate voltage (Vgs - Vt).
 The voltage Vds appears as a voltage drop across the length of the channel. The voltage
between the gate and the points along the channel increases from Vgs at the source end to
Vgs - Vds at the drain end.
 Since the channel depth depends on this voltage, we find that the channel is no longer of
uniform depth; rather, the channel will take the tapered form.
 As Vds is decreased further, the channel becomes more tapered and its resistance
increases correspondingly.
 Thus the Id - Vds curve does not continue as a straight line but bends eventually as shown
in fig.1.16, when Vds is decreased to the value which reduces the voltage between gate
and channel at the drain end to Vt, i.e, Vgd = Vt, or Vgs - Vds = Vt or Vds = Vgs - Vt
 The channel depth at the drain end decreases to almost zero, and the channel is said to be
pinched off.
 Decreasing Vds further shifts the pinch-off point towards the source region, and the
current through the channel remains constant at the value obtained for Vds = Vgs - Vt.

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G G

S D S D

p+ p+ p+ p+

n-substrate n-substrate

B B

Vgs ≤ Vt; Vds = 0 Vgs ≤ Vt; Vds > Vgs - Vt

Fig.1.14: Linear region of pMOS transistor
 The drain current thus saturates at this value, and the MOSFET is said to have entered the
saturation region of operation.
 The voltage Vds at which saturation occurs is denoted Vdssat and Vdssat = Vgs - Vt.
 The device operates in the saturation region if Vds ≤ Vdssat as shown in the fig1.15 and
it operates in linear region (triode region) if Vds > Vdssat as shown in the fig1.14.

G G

S D S D

p+ p+ p+ p+

n-substrate n-substrate

B B

Vgs ≤ Vt; Vds = Vgs - Vt Vgs ≤ Vt; Vds < Vgs - Vt

Fig.1.15: Saturation region of pMOS transistor

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Fig.1.16: Id – Vds characteristics of pMOS with regions of operations

Symbol of nMOS transistor

D D D D

G G G B G B

S S S S

Fig.1.17: Symbol of nMOS transistor

Symbol of pMOS transistor

S S S S

G G G B G B

D D D D

Fig.1.18: Symbol of pMOS transistor

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Long-Channel I-V Characteristics:

 MOS transistors have three regions of operation:
i. Cutoff or subthreshold region
ii. Linear region
iii. Saturation region
 Long-channel, ideal, first-order, or Shockley model relates current and voltage (I-V) for
an nMOS transistor in each of these regions. The model assumes that the channel length
is long enough that the lateral electric field (the field between source and drain) is
relatively low.
 The long-channel model assumes that the current through an OFF transistor is 0. When a
transistor turns ON (Vgs > Vt), the gate attracts carriers (electrons) to form a channel.
 The electrons drift from source to drain at a rate proportional to the electric field between
these regions.
 The gate and the channel region form a parallel plate capacitor for which the oxide layer
serves as a dielectric. The charge on each plate of a capacitor is Q = CV. Thus, the charge
in the channel Qchannel is
𝐐𝐂𝐡𝐚𝐧𝐧𝐞𝐥 = 𝐂𝐠 (𝐕𝐠𝐜 − 𝐕𝐭 ) 𝟏. 𝟏
where Cg is the capacitance of the gate to the channel and Vgc - Vt is the amount
of voltage attracting charge to the channel.
 The gate voltage is referenced to the channel, which is not grounded. If the source is at Vs
and the drain is at Vd, then average channel voltage is
(𝐕𝐬 + 𝐕𝐝 )
𝐕𝐂 =
𝟐
(𝐕𝐬 + 𝐕𝐬 − 𝐕𝐬 + 𝐕𝐝 )
𝐕𝐂 =
𝟐
(𝟐𝐕𝐬 + 𝐕𝐝 − 𝐕𝐬 )
𝐕𝐂 =
𝟐
𝐕
𝐕𝐂 = 𝐕𝐬 + 𝐝𝐬⁄𝟐
 The gate to channel potential is given by
𝐕𝐠𝐜 = 𝐕𝐠 − 𝐕𝐜
 On substituting average channel voltage,

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𝐕𝐝𝐬⁄
𝐕𝐠𝐜 = 𝐕𝐠 − (𝐕𝐬 + 𝟐)
Vds⁄
Vgc = Vgs − 2

 If the gate has length L and width W and the oxide thickness is tox, the capacitance is
∈𝐨𝐱 𝐖𝐋
𝐂𝐠 = = 𝐂𝐨𝐱 𝐖𝐋 𝟏. 𝟐
𝐭 𝐨𝐱
where εox is the permittivity of the silicon oxide,
εox = 3.9ε0 = 3.9*8.854*10-12 = 3.45*10-11F/m
 Each carrier in the channel is accelerated with an average velocity, v, proportional to the
lateral electric field, i.e., the field between source and drain. The constant of
proportionality µ is called the mobility.
v = µE 1.3
 A typical value of µ for electrons in an nMOS transistor with low electric fields is 500-
700 cm2/V·s.
 The electric field E is the voltage difference between drain and source Vds divided by the
channel length
𝐕𝐝𝐬
𝐄= 𝟏. 𝟒
𝐋
 The time required for carriers to cross the channel is the channel length divided by the
carrier velocity: L/v. Therefore, the current between source and drain is the total amount
of charge in the channel divided by the time required to cross
𝐐𝐜𝐡𝐚𝐧𝐧𝐞𝐥
𝐈𝐝𝐬 = 𝟏. 𝟓
𝐋⁄
𝐯
 On substituting

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𝐖 𝟏
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 [ (𝐕𝐠𝐬 − 𝐕𝐭 )𝐕𝐝𝐬 − 𝐕𝐝𝐬 𝟐 ] 𝟏. 𝟔
𝐋 𝟐
 μn Cox is a constant determined by the process technology used to fabricate the n-channel
MOSFET. It is known as the process transconductance parameter, also denoted by
k′n , and has the dimensions of A/V2
𝐤′𝐧 = 𝛍𝐧 𝐂𝐨𝐱 𝟏. 𝟕

 The value of the current at the edge of the triode region or at the beginning of the
saturation region can be obtained by substituting Vds = Vgs – Vt in equation1.6
𝐖 𝟏 𝟐
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 [ (𝐕𝐠𝐬 − 𝐕𝐭 )(𝐕𝐠𝐬 − 𝐕𝐭 ) − (𝐕𝐠𝐬 − 𝐕𝐭 ) ]
𝐋 𝟐
𝟏 𝐖 𝟐
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 ) 𝟏. 𝟖
𝟐 𝐋
 The linear region and saturation region current can also be expressed as
𝟏
𝐈𝐝𝐬 = 𝛃 [ (𝐕𝐠𝐬 − 𝐕𝐭 )𝐕𝐝𝐬 − 𝐕𝐝𝐬 𝟐 ] 𝟏. 𝟗
𝟐
𝟐
(𝐕𝐠𝐬 − 𝐕𝐭 )
𝐈𝐝𝐬 =𝛃 𝟏. 𝟏𝟎
𝟐
𝐖
where, 𝛃 = 𝛍𝐧 𝐂𝐨𝐱 𝐋

Non-Ideal IV Effects:
 The Shockley transistor model or Long channel model or ideal model derived a current-
voltage expression for an ideal transistor (assuming a certain number of ideal conditions)
and failed to consider many prominent non-ideal characteristics such as
i. Mobility degradation and Velocity Saturation
ii. Channel length modulation
iii. Body effect
iv. Leakage current
v. Geometry Dependence
Velocity saturation and Mobility degradation:
 The saturation current increases less than quadratically with increasing Vgs. This is
caused by two effects:

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i. Velocity saturation
ii. Mobility degradation
Velocity saturation:
 At high lateral field strengths (Vds/L), carrier velocity ceases to increase linearly with
field strength
 It result in lower Ids than expected at high Vds
Mobility degradation:
 Practically, the electrons traveling from the source to drain in an nMOS don’t follow a
straight path.
 At high vertical field strengths (Vgs/tox), the carriers scatter more often and leads to less
current than expected at high Vgs
Channel Length Modulation:
 Ideally, Ids is independent of Vds for a transistor in saturation, making the transistor a
perfect current source.
𝟏 𝐖 𝟐
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 )
𝟐 𝐋
 As Vds increases in saturation region, the depletion region effectively shortens the
channel. This phenomenon is called Channel Length Modulation.
 Thus the effective channel length can be expressed as
𝐋𝐞𝐟𝐟 = 𝐋 − 𝐋𝐝

Fig.1.19: Effective channel length

 Ids can be expressed as
𝟏 𝐖 𝟐
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 )
𝟐 𝐋𝐞𝐟𝐟
𝟏 𝐖 𝟐 𝟏
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 )
𝟐 𝐋 𝐋
𝟏 − 𝐋𝐝

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 Ld/L << 1 then

𝟏 𝐖 𝟐 𝐋𝐝
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 ) (𝟏 + )
𝟐 𝐋 𝐋
𝟏 𝐖 𝟐
𝐈𝐝𝐬 = 𝛍𝐧 𝐂𝐨𝐱 (𝐕𝐠𝐬 − 𝐕𝐭 ) (𝟏 + 𝛌𝐕𝐝𝐬 )
𝟐 𝐋
 The parameter λ is an empirical channel length modulation factor.
 As channel length gets shorter, the effect of the channel length modulation becomes
relatively more important and is inversely dependent on channel length.
 Channel length modulation is very important to analog designers because it reduces the
gain of amplifiers. It is generally unimportant for qualitatively understanding the
behavior of digital circuits
Body Effect:
 For nMOS transistor source and body terminals are both connected together and into
ground.
 When two nMOS transistor are connected in series then source of one transistor is not
connected to ground (for example NAND gate).
 If the body and the source are connected to a different potential, then this changes the
threshold voltage. This effect is known as body effect.
 Therefore, the threshold voltage is given by
𝑉𝑡 = 𝑉𝑡0 + 𝛾( √𝛷𝑠 + 𝑉𝑠𝑏 – √𝛷𝑠 )
where Vt0 is the threshold voltage when Vsb = 0,
γ is the body effect coefficient
Φs is the surface potential at threshold
 The threshold voltage increases with source voltage and decreases with body voltage.
Leakage Current:
 The p-n junctions between diffusion and the substrate or well form diodes.
 The p-type and n-type substrates are tied to GND or VDD to ensure these diodes remain
reverse-biased.
 However, reverse-biased diodes still conduct a small amount of current IL.
 Leakage currents include subthreshold conduction between source and drain, gate
leakage from the gate to body, and junction leakage from source to body and drain to
body as shown in the fig.

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 Subthreshold conduction is caused by thermal emission of carriers over the potential

barrier set by the threshold. Gate leakage is a quantum-mechanical effect caused by
tunneling through the extremely thin gate dielectric. Junction leakage is caused by current
through the p-n junction between the source/drain diffusions and the body.

Fig.1.20: Leakage currents

 In modern transistors with low threshold voltages, subthreshold conduction far exceeds
junction leakage.
Geometry Dependence:
 The layout designer draws transistors with width and length Wdraw and Ldraw. The actual
gate dimensions may differ by some factors XW and XL.
 For example, the manufacturer may create masks with narrower polysilicon or may
overetch the polysilicon to provide shorter channels (negative XL)
 Moreover, the source and drain tend to diffuse laterally under the gate by LD, producing a
shorter effective channel length that the carriers must traverse between source and drain.
 Similarly, diffusion of the bulk by WD decreases the effective channel width.
 Therefore, the actually effective channel length and width can be expressed as
Leff = Ldraw + X L − 2LD
Weff = Wdraw + X W − 2WD

CMOS Inverter DC Characteristics:

 For the static CMOS inverter shown in fig.1.21, Vtn is the threshold voltage of the n-
channel device, and Vtp is the threshold voltage of the p-channel device. Note that Vtn is
positive and Vtp is negative.

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Fig.1.21: CMOS inverter

 The source of the nMOS transistor is grounded, hence Vgsn = Vin and Vdsn = Vout.
 The source of the pMOS transistor is tied to VDD, hence Vgsp = Vin – VDD and Vdsp = Vout
– VDD.
 The operating conditions of CMOS inverter in three regions is given by the following
expressions

Cutoff Linear Saturation

Vgsn ≥ Vtn Vgsn ≥ Vtn
Vgsn < Vtn Vin ≥ Vtn Vin ≥ Vtn
nMOS
Vin < Vtn Vdsn < Vgsn - Vtn Vdsn ≥ Vgsn - Vtn
Vout < Vin - Vtn Vout ≥Vin - Vtn
Vgsp ≤ Vtp Vgsp ≤ Vtp
Vgsp > Vtp Vin ≤ Vtp + VDD Vin ≤ Vtp + VDD
pMOS
Vin > Vtp + VDD Vdsp > Vgsp - Vtp Vdsp ≤ Vgsp - Vtp
Vout > Vin - Vtp Vout ≤ Vin - Vtp

Graphical derivation of CMOS inverter characteristics

 First the characteristics of pMOS and nMOS are plotted for different values of Vgs and
Vds as shown in the fig.1.22.

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Fig.1.22: Id - Vds characteristics of pMOS and nMOS

 nMOS curve is plotted on 1st quadrant and pMOS curve is plotted on 3rd quadrant.
 Absolute value of drain current for pMOS transistor is obtained, which inverts the
characteristics to 2nd quadrant (i.e. characteristics is reflected over the horizontal axis) as
shown in the fig.1.23. Vgs of pMOS transistor is balance by adding VDD to Vgs (because
for pMOS in CMOS inverter Vgs is given by, Vgsp = Vin – VDD. Therefore, Vin = Vgsp +
VDD).

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Fig.1.23: Characteristics of pMOS is reflected over the horizontal axis

 The characteristics of pMOS are now superimposed on the characteristics of nMOS as
shown in the fig.1.24. Vds of pMOS transistor is balance by adding VDD to Vds (because
for pMOS in CMOS inverter Vdss is given by, Vdsp = Vout – VDD. Therefore, Vout = Vdsp +
VDD).

Fig.1.24: Superimposition of pMOS and nMOS characteristics

 The transfer curve of CMOS inverter is now determined by the taking common Vgs
intersection points from fig.1.24 as shown in the fig.1.25.

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Fig.1.25: CMOS inverter characteristics

 The CMOS inverter characteristic is obtained and the operation of CMOS inverter can be
divided into five regions as shown in the fig.1.26.

Fig.1.26: CMOS inverter characteristics with different regions of operation

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CMOS inverter operation can be summarized as follows

Region Condition pMOS nMOS Output

A 0 ≤ Vin < Vtn Linear Cutoff Vout = VDD
Decrease in output but greater
B Vtn ≤ Vin < VDD /2 Linear Saturation
than VDD /2
C Vin = VDD /2 Saturation Saturation Output drops sharply
Decrease in output but lesser
D VDD /2 < Vin ≤ VDD + Vtp Saturation Linear
than VDD /2
E VDD + Vtp < Vin ≤ VDD Cutoff Linear Vout = 0

βn/βp Ratio
 When beta ratio changes, the switching threshold also changes. If βp = βn, the switching
threshold voltage Vinv is VDD/2.
 Inverters with different beta ratios βp / βn are called skewed inverters and its
characteristics are shown in fig.1.27.

Fig.1.27: CMOS inverter with different βn/βp ratio

 If βp / βn > 1, the inverter is HI-skewed.
 If βp / βn < 1, the inverter is LO-skewed.
 If βp / βn = 1, the inverter has normal skew or is unskewed.
 A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is VDD /2, the
output will be greater than VDD/2. In other words, the input threshold must be higher for
an unskewed inverter.

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 A LO-skew inverter has a weaker pMOS transistor. Therefore, if the input is VDD /2, the
output will be lesser than VDD/2. In other words, the input threshold must be lower for
an unskewed inverter.

Noise Margin
 Noise margin allow us to determine the allowable noise voltage on the input of the gate
so that the output will not be corrupted.
 Noise margin is determined by two parameters
1. Low Noise Margin NML
2. High Noise Margin NMH
 Noise margin is determined as shown in the fig.1.28.
 Low Noise Margin is defined as the difference in maximum LOW input voltage
recognized by the receiving gate and the maximum LOW output voltage produced by the
driving gate.
NML = VIL – VOL

Fig.1.28: Noise Margin of a CMOS gate

 High Noise Margin is defined as the difference between the minimum HIGH output
voltage of the driving gate and the minimum HIGH input voltage recognized by the
receiving gate.
NMH = VOH – VIH

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where,
VIH = minimum HIGH input voltage
VIL = maximum LOW input voltage
VOH = minimum HIGH output voltage
VOL = maximum LOW output voltage
 For calculating noise margins from the transfer characteristic of the inverter the different
voltage levels VIL, VOL, VIH, and VOH are as shown in fig. 1.29. These logic levels are
defined at the unity gain point where the slope is –1.

Fig.1.29: CMOS inverter noise margins

CMOS Logic:
 CMOS gate consists of pull-up network connected between VDD and output and pull-
down network connected between output and GND as shown in fig.1.30.
 Pull-up network consists of pMOS transistor and pull-down network consists of nMOS
transistor.
 Pull-up network is responsible to connect the output node to VDD, and pull-down network
is responsible to connect the output node to GND.
 The networks are arranged such that one is ON and the other OFF for any input pattern.
 If a CMOS gate has one input, then it requires one pMOS transistor and one nMOS
transistor. Similarly, for an n-input CMOS gate it requires n pMOS transistors and n
nMOS transistors.

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Fig.1.30: General logic gate using pull-up and pull-down networks

 For an n-input CMOS gate, transistors are connected depending on the logic function
between inputs.
Logic function pMOS connection nMOS connection
● Parallel Series
+ Series Parallel
 The source terminals of pMOS transistor should be facing towards (connected to) VDD
supply and the source terminals of nMOS transistor should be facing towards (connected
to) GND supply.
 The drain terminals of pMOS and nMOS transistors should be facing towards (connected
to) output.
 The gate terminal is the input terminal.
Inverter

Fig.1.31: CMOS Inverter Schematic

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 Fig.1.31 shows the schematic for a CMOS inverter or NOT gate. It has one input, so it
requires one nMOS transistor and one pMOS transistor.
 When the input A is 0, the nMOS transistor is OFF and the pMOS transistor is ON. Thus,
the output Y is pulled up to 1 because it is connected to VDD.
 When the input A is 1, the nMOS transistor is ON, the pMOS transistor is OFF, and Y is
pulled down to ‘0’ because it is connected to GND.

A Y
0 1
1 0

NAND GATE

Fig.1.32: CMOS NAND gate Schematic

 Fig.1.32 shows the schematic of a 2-input CMOS NAND gate. It consists of two pMOS
transistors connected in parallel between Z and VDD and two nMOS transistors between
Y and GND.
 If either input A or B is 0, at least one of the nMOS transistors will be OFF, breaking the
path from Z to GND. But at least one of the pMOS transistors will be ON, creating a path
from VDD to Z Hence, the output Z will be 1.

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 If both inputs are 1, both of the nMOS transistors will be ON and both of the pMOS
transistors will be OFF. Hence, the output will be 0. The truth table is given below.
Pull down Pull up
A B Z
Network Network
0 0 OFF ON 1
0 1 OFF ON 1
1 0 OFF ON 1
1 1 ON OFF 0

NOR GATE

Fig.1.33: CMOS NOR symbol and Schematic

 Fig.1.33 shows the symbol and schematic of a 2-input CMOS NOR gate. It consists of
two pMOS transistors connected in series between VDD and Z and two nMOS transistors
connected in parallel between Z and GND.
 If either input A or B is 1, at least one of the pMOS transistors will be OFF, breaking the
path from VDD to Z. But at least one of the nMOS transistors will be ON, creating a path
from Z to GND. Hence, the output Z will be 0.
 If both inputs are 0, both of the pMOS transistors will be ON, creating a path from VDD to
Z and both of the nMOS transistors will be OFF. Hence, the output will be 1. The truth
table is given below.

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Pull down Pull up

A B Z
Network Network
0 0 OFF ON 1
0 1 ON OFF 0
1 0 ON OFF 0
1 1 ON OFF 0

Design of Complex gates

̅𝐁
1. 𝐙 = 𝐀 ̅ + 𝐀𝐁

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̅̅̅̅̅̅̅̅̅̅̅̅
2. 𝐙 = 𝐀(𝐁 + 𝐂)

3. 𝐙 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐏𝐐 + 𝐗 + 𝐘

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The Transmission Gate

 CMOS transmission gate consists of an nMOS transistor and pMOS transistor with
separate gate connections and common source and drain connections as shown in the
fig.1.34.

Fig.1.34: CMOS transmission gate

 A control signal is applied to the gate of the nMOS transistor and its compliment is
applied to the gate of pMOS transistor.
 To study the operation of transmission gate, a load capacitance is considered and it’s
charging and discharging is controlled by transmission gate.
 Consider the nMOS transistor and pMOS transistor separately as a pass transistor and the
current flow direction is controlled by transmission gate.
Operation of nMOS pass transistor
 nMOS pass transistor is turned on by applying the gate voltage higher than the either
terminal voltage by the threshold voltage and is turned off by applying the gate voltage
lower than the either terminal voltage by the threshold voltage.

Fig.1.35: nMOS pass transistor

 To turn on Vg > Vin + Vt or Vg > Vout + Vt (i.e. Vgs > Vt)
 To turn off Vg < Vin + Vt or Vg < Vout + Vt (i.e. Vgs < Vt)
 To analyze the operation, consider three cases

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Case 1: Vg = 0V (or S = 0V); Vin = 0V or 5V; Vout = 0V or 5V

 Since Vg is less than the either terminal voltage the transistor is in cutoff state and the
capacitor will hold its charge.
Case 2: Vg = 5V; Vin = 5V; Vout = 0V (initially)
 Since Vg is greater than Vout by the threshold voltage the transistor conducts and
capacitor charges.
 Since Vin is at higher potential than Vout the current flows through the device from left to
right (i.e. from Vin to Vout).
 When the output voltage becomes 5V - Vtn the nMOS transistor enters into cutoff region,
hence the output remains at 5V - Vtn.
 Therefore, the transmission of logic one is degraded.
Case 3: Vg = 5V; Vin = 0V; Vout = 5V - Vt (initially)
 Since Vg is greater than Vin by the threshold voltage the transistor conducts and capacitor
discharges.
 Since Vin is at lower potential than Vout the current flows through the device from right to
left (i.e. from Vout to Vin).
 The nMOS transistor discharges the output to VSS and the transmission of logic zero is
not degraded.
 Since Vg > Vin + Vt always, the output voltage of the nMOS transistor will discharge
completely to zero.
Operation of pMOS pass transistor
 pMOS pass transistor is turned on by applying the gate voltage lower than the either
terminal voltage by the threshold voltage and is turned off by applying the gate voltage
higher than the either terminal voltage by the threshold voltage.

Fig.1.36: pMOS pass transistor

 To turn on Vg < Vin + Vt or Vg < Vout + Vt (i.e. Vgs < Vt)
 To turn off Vg > Vin + Vt or Vg > Vout + Vt (i.e. Vgs > Vt)

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 To analyze the operation consider three cases

Case 1: Vg = 5V (or S = 5V); Vin = 0V or 5V; Vout = 0V or 5V
 Since Vg is greater than the either terminal voltage the transistor is in cutoff state and the
capacitor will hold its charge.
Case 2: Vg = 0V; Vin = 5V; Vout = 0V (initially)
 Since Vg is lesser than Vin by the threshold voltage the transistor conducts and capacitor
charges.
 Since Vin is at higher potential than Vout the current flows through the device from left to
right (i.e. from Vin to Vout).
 The pMOS transistor charges the output to 5V and the transmission of logic one is not
degraded.
 Since Vg < Vout + Vt always, the output voltage of the pMOS transistor will charge
completely to 5V.
Case 3: Vg = 0V; Vin = 0V; Vout = 5V (initially)
 Since Vg is less than Vout by the threshold voltage the transistor conducts and capacitor
discharges.
 Since Vin is at lower potential than Vout the current flows through the device from right to
left (i.e. from Vout to Vin).
 When the output voltages reaches Vout = Vt the pMOS transistor enters into cutoff region,
hence the output remains at Vt.
 Therefore the transmission of logic zero is degraded.
The operation of pass transistor can be summarized as

Device Transmission of ‘1’ Transmission of ‘0’

n Poor Good
p Good Poor

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The operation of transmission gate can be summarized as

 When nMOS pass transistor are connected in series with VDD as input then at the nth stage
output will be VDD - Vtn as shown in the fig.1.37.

Fig.1.37: Voltage degradation of pass transistor when connected in series

 When nMOS pass transistor is driving an nMOS pass transistor with VDD as input then at
the nth stage output will be VDD - nVtn. For two stage output will be VDD - 2Vtn as shown
in the fig.1.38.

Fig.1.38: Voltage degradation of pass transistor when output is driving next stage

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Pass Transistor Logic

 The general structure of Pass Transistor logic is as shown in the fig.1.39.

Fig.1.39: General structure of Pass Transistor logic

 It consists of pass inputs and control inputs. Depending on the state of control input, pass
input is connected to output.
Drawback
 Output is degraded by a threshold value
 Instead of pass transistor transmission gate can be used to overcome the drawback of pass
transistor logic.
 Control input is applied to the gate of the nMOS transistor and its compliment is applied
to the gate of the pMOS transistor.

Realization of INVERTER using Pass transistor logic

INVERTER Truth Table

A Z
0 1
1 0

̅ (i.e. 1).
 When A = 0  Z = A
̅ (i.e. 0).
 When A = 1  Z = A
̅ as pass inputs as shown
 To realize the pass transistor logic, take A as control input and 𝐀
below.

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Realization of NAND gate using Pass transistor logic

NAND Truth Table

A B Z
0 0 1
0 1 1
1 0 1
1 1 0

 Two input NAND gate has A and B as inputs. Now take A as control input and B as pass
input.
 When A = 0  Z = 1
̅
 When A = 1  Z = 𝐁
̅ , 1 (VDD) as pass inputs
 To realize the pass transistor logic take A as control input and 𝐁
as shown below.

Realization of NOR gate using Pass transistor logic

NOR Truth Table

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A B Z
0 0 1
0 1 0
1 0 0
1 1 0

 Two input NOR gate has A and B as inputs. Now take A as control input and B as pass
input.
̅
 When A = 0  Z = 𝐁
 When A = 1  Z = 0
̅ , 0 (GND) as pass inputs
 To realize the pass transistor logic take A as control input and 𝐁
as shown below.

Realization of 2:1 MUX using Pass transistor logic

2:1 MUX Truth Table

S Z
0 A
1 B

 Let A and B are the inputs, S is the select line and Z is the output.
 When S = 0  Z = A
 When S = 1  Z = B
 Output expression is given by Z = AS̅ + BS
 To realize the 2:1 MUX take S as control input, A, B as pass inputs as shown below.

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̅ 𝐂̅ + 𝐀𝐁
Realize the expression 𝐙 = 𝐀𝐁 + 𝐀 ̅ 𝐂 using pass transistor logic

Transmission Gate logic

 Replace the nMOS pass transistor by transmission gate in the pass transistor logic for
transmission gate realization.
 Control input of the pass transmission logic should be applied to the gate of the nMOS
transistor of the transmission gate and its compliment to the gate of pMOS transistor.

Realization of INVERTER using Transmission Gate logic

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Realization of NAND gate using Transmission Gate logic

Realization of NOR gate using Transmission Gate logic

Realization of 2:1MUX using Transmission Gate logic

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̅ 𝐂̅ + 𝐀𝐁
Realize the expression 𝐙 = 𝐀𝐁 + 𝐀 ̅ 𝐂 using transmission gate logic

Tristates
Tristate buffer:
 Tristate buffer has three terminal – input, enable, and output.
 When the enable input (E) is 1, the output (Y) is equal to the input (A).
 When the enable input (E) is 1, the output (Y) is left floating ('Z' value).

E A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
̅) as
 The enable signal can be in un-complemented signal (E) or complemented signal (E
shown in the fig.1.40.

Fig.1.40: Tristate buffer

 Tristates were once commonly used to allow multiple units to drive a common bus, as
long as exactly one unit is enabled at a time. If multiple units drive the bus, contention

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occurs and power is wasted. If no units drive the bus, it can float to an invalid logic level
that causes the receivers to waste power.
Tristate inverter:
 Tristate inverter is designed by cascading a transmission gate with an inverter as shown
in the fig.1.41. The output is actively driven from VDD or GND, so it is a restoring logic
gate.

Fig.1.41: Tristate inverter

̅ = 1 the output Y is in tristate since the transmission gate is off.
 When E = 0 and E
̅ = 0 the output Y is equal to the compliment of A since the
 When E = 1 and E
transmission gate is on.

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