Memory applications from 2D materials

Cite as: Appl. Phys. Rev. 8, 021306 (2021); https://doi.org/10.1063/5.0038013

Submitted: 17 November 2020 . Accepted: 04 March 2021 . Published Online: 09 April 2021

Chin-Cheng Chiang, Vaibhav Ostwal, Peng Wu, Chin-Sheng Pang, Feng Zhang, Zhihong Chen, and
Joerg Appenzeller

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 Applied Physics Reviews REVIEW scitation.org/journal/are

Memory applications from 2D materials

Cite as: Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013
Submitted: 17 November 2020 . Accepted: 4 March 2021 .
Published Online: 9 April 2021

Chin-Cheng Chiang,1,2 Vaibhav Ostwal,1,2 Peng Wu,1,2 Chin-Sheng Pang,1,2 Feng Zhang,1,2,3
1,2 1,2,a)
Zhihong Chen, and Joerg Appenzeller

AFFILIATIONS
1
Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, USA
2
Department of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907, USA
3
Intel Corporation, Santa Clara, California 95054, USA

a)
Author to whom all correspondence should be addressed: appenzeller@purdue.edu

ABSTRACT
As existing silicon-based memory technologies are reaching their fundamental limit, emerging memory alternatives, such as resistive
random-access memories (RRAMs), magnetic random-access memories, and ferroelectric random-access memories, are intensively
investigated with the aim of improving capacity, write/read speed, efficiency, and implementing unconventional computing for data-centric
applications. Recent studies have exploited the nature of 2-dimensional layered materials (2DLMs) to integrate highly disparate
materials with unique physical and chemical properties without the constraint of lattice matching and have demonstrated novel memory
devices (such as resistive and magnetic) with unprecedented characteristics or unique functionalities desired in emerging memory technolo-
gies. This article primarily provides an overview of the progress made, advantages, and challenges toward practical application of 2DLM-
based memory units. In this regard, novel electronic properties of these 2DLMs allow designing not only the memory unit but also selectors
and CMOS components essential for RRAM technology. Here, we also experimentally demonstrate a proof-of-concept heterostructure con-
sisting of 2DLMs that fulfill the function of a memory unit (using MoTe2) and selector (using WSe2) with desired characteristics for RRAM
integration. This demonstration underscores the potential of 2DLMs and their heterostructure toward the realization of future memory
technologies.
Published under license by AIP Publishing. https://doi.org/10.1063/5.0038013

TABLE OF CONTENTS
I. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
II. MEMORY ELEMENTS USING 2DLMS . . . . . . . . . . . . . .
A. DRAMs and SRAMs . . . . . . . . . . . . . . . . . . . . . . . . .
B. FeRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C. MRAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D. RRAMs and PCRAMs . . . . . . . . . . . . . . . . . . . . . . . .
III. 2DLM-BASED DEVICES FOR RRAM
TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IV. DISCUSSION AND OUTLOOK . . . . . . . . . . . . . . . . . . . .
AUTHORS’ CONTRIBUTIONS . . . . . . . . . . . . . . . . . . . . . . . .
I. INTRODUCTION
For the last few decades, scaling of CMOS technology has been
the driving force behind improving the performance of modern com-
puters with the von Neumann architecture, consisting of separate logic
and memory building blocks. In recent years, CMOS scaling has been
slowing down due to fundamental limitations associated with the
1 physics of conventional silicon (Si) field-effect transistors (FETs).1 On
3 the other hand, transistors employing 2-dimensional layered materials
3 (2DLMs), such as transition metal dichalcogenides (TMDs)2 or black
5 phosphorous (BPs)3 as semiconducting channels, are considered
7 potential alternatives and/or performance enhancers at advanced tech-
9 nology nodes. This is due to more achievable electrostatic gate control
inherent to the ultra-thin body of 2DLMs, while exhibiting mobilities
10 comparable to silicon. According to some researchers, the integration
17 of such low-dimensional materials may extend scaling of CMOS FETs
17 down to 1 nm channel lengths.4 However, CMOS scaling alone may
not be sufficient to meet the challenges of modern data-intensive
computing.
Traditional “binary” memory technologies consisting of SRAM
(Static Random-Access Memory), DRAM (Dynamic RAM), and flash
are used at various levels in the memory hierarchy of today’s
computers.5 In recent years, scaling down these charge/transistor-
based technologies has faced challenges6 in terms of power dissipation,
reliability, performance degradation, and so on, similar to CMOS

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-1

Published under license by AIP Publishing
 Applied Physics Reviews
technology. Hence, alternative memory ideas are being explored to
complement or replace traditional memory technologies. Among
those being investigated, Magnetic RAM (MRAM), Resistive RAM
(RRAM), Phase-Change RAM (PCRAM), and Ferroelectric Field-
Effect Transistors (Fe-FETs) have emerged as primary candidates for
nonvolatile memory (NVM) technologies, each one with advantages
and limitations, and are expected to find their own unique application
space. For example, recent commercial products (by Everspin and
IBM/Global-Foundries)7 have demonstrated Spin Transfer Torque
(STT)-MRAM as a discrete and embedded NVM alternative to
DRAM, while 3D-Xpoint (developed by Intel and Micron)8 is
expected to add another tier level in the memory hierarchy. Naturally,
research on emerging technologies in this application space is focused
on improving scalability, power efficiency, speed, reliability, and so
forth to provide advantages over conventional memory technologies
they are trying to replace, which will be discussed further in Secs.
II A–II D.
However, unique properties of these emerging memory technolo-
gies are also being explored for implementation of unconventional,
often “analog,” computing systems. Frequent data transfer between
physically separated logic and memory blocks during data-intensive
computing results in large energy and delay costs. Although the cur-
rent von Neumann architecture is unlikely to be abandoned in the
foreseeable future, the growing trend toward computing with a data-
centric approach such as machine learning and deep learning
demands more specialized non-von Neumann platforms, where com-
putational tasks and data storage are both performed in place in the
memory itself, offering better performance9 for data-intensive comput-
ing tasks such as pattern recognition and big-data analysis.10 In-
memory computing11 and neuromorphic computing12 are examples
of such schemes that require logic and memory blocks in close vicinity.
backend-of-the-line (BEOL) compatibility of emerging NVM technol-
ogies allows such 3D monolithic integration of memory units and logic
units (CMOS technology).13 Furthermore, devices used in many
emerging NVM technologies show memristive behavior (continuous/
analog change of resistance when subjected to electrical inputs) ana-
logues to biological synapses.14 Large arrays of such memristive devi-
ces especially in crossbar architecture allow efficient vector-matrix
multiplication, consisting of multiplications and additions operations.
In such arrays, for a given operating voltage, conductance of a memris-
tor acts as a multiplication operation by Ohm’s law, while current
summation occurs along columns of memristors due to Kirchhoff’s
current law.15 Massive computational parallelism in such arrays can be
used to accelerate neural networks or other unconventional computing
systems. However, accuracy of such systems is adversely affected by
non-idealities in memristors such as linearity of synaptic behavior,
device-to-device variations, cycle-to-cycle variations, finite on/off con-
ductance ratio resulting in a stringent technology requirement com-
pared to traditional memory applications.16
Hence, further research is warranted for commercialization of
emerging NVM technologies either as “binary” memory units in con-
ventional computing or implementation of unconventional computing
systems based on “analog” switching. With the ever-increasing impor-
tance of emerging NVM technologies along with exciting discoveries
of intrinsic properties essential for NVM devices in 2DLMs, significant
research is now focusing on the implementation of both types of
memory devices using 2DLMs.
Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013
Published under license by AIP Publishing
REVIEW scitation.org/journal/are
Nearly a decade after the first demonstration of an FET from a
2DLM semiconductor,2 researchers have by now successfully fabri-
cated various logic components such as logic-gates,17 ring oscillators,18
and amplifiers.19 On the other hand, less research has been focusing
on 2D-based memory applications. For conventional memory tech-
nologies such as SRAM,20 DRAM,21 and flash,22 2DLMs are utilized as
FETs, following the argument of the first paragraph in this introduc-
tion. However, emerging NVM technologies would benefit from mate-
rials with the ability to store information using intrinsic material
properties such as magnetic moments or electric dipoles. While these
properties are not observed in most common 2DLMs like TMDs or
BP, recent experiments on new 2DLMs have revealed ferromagne-
tism23,24 and ferroelectricity.25 Figure 1 summarizes recent results that
show how 2DLMs can be used as critical building blocks for conven-
tional and emerging NVM elements.
For example, 2DLMs such as MoTe2 are stable in multiple crys-
talline phases, and electric fields can induce a transition from one state
to another, which can be used to store information in a nonvolatile
fashion similar to PCRAM, but with better device performance in
terms of switching speeds and operating voltages.26
2DLMs such as Cr2Ge2Te6 (CGT)23 and CrI324 are ferromagnetic
even at the monolayer limit, and magnetic moments in such 2DLMs
can be manipulated using electric fields or charge currents, as desired
for MRAM. The perfect crystalline nature and potentially clean inter-
faces in magnetic tunneling junction (MTJ) type 2D-heterostructures
may provide opportunities to achieve high tunneling magnetoresis-
tance (TMR) values compared to conventional CoFeB-MgO-based
MTJs.27 Furthermore, electrostatic control of the Curie temperature
and inter-layer coupling in 2D-ferromagnets (2D-FMs) can be
exploited to achieve energy-efficient voltage-controlled spin devices.28
While conventional 3D ferroelectric materials employed in Fe-
FETs are insulating, ferroelectricity has been observed not only in insu-
lating25 but also in semiconducting29 and metallic 2DLMs.30 These
diverse electronic properties in 2D-ferroelectrics are essential for imple-
menting novel ferroelectric memory devices, such as FeS-FETs.29
Moreover, supplementary device-components with functionali-
ties necessary for memory devices, such as selectors for crossbar
RRAM,31,32 tunnel barriers for MRAM,33 or access transistors,34 can
also be implemented using 2DLMs. Due to the ability of 2DLMs to
form heterostructures without the need of matching the crystal-lattice,
one can assemble technology-relevant memory devices by combining
2DLMs with different functionalities. Furthermore, with recent pro-
gress in the growth of 2DLMs at BEOL-compatible temperatures, they
can be ideal candidates for integration of logic and memory units on a
monolithic 3D chip.34,35
With research on 2DLM devices progressing at a rapid pace, this
article will review fundamental discoveries in 2DLMs that are deemed
important for emerging NVM technologies and discuss experimental
demonstrations reported up until now as well as those desired in the
future to implement emerging devices in memory applications. The
review will highlight advantages offered by 2DLMs over conventional
materials due to their ultra-thin body, superior material properties,
and their ability to form van der Waals (vdW) heterostructures, which
has the potential to solve key challenges of emerging memory technol-
ogies. Toward this goal, we will put a particular emphasis on MoTe2
RRAM devices. The underlying physics and device performance will
be summarized, and new results of vdW heterostructures consisting of
8, 021306-2
 Applied Physics Reviews REVIEW scitation.org/journal/are

(a) SRAM / DRAM / FLASH (b) FeRAM / FeFET

500
MoS2 180

PFM amplitude (pm)

S D 400

PFM phase (°)

90
SWCNT (G)
300
ZrO2 0
200
SiO2 –90
100
n+ Si (B) –180
4 0
–8 –4 0 4 8
VBS = 5 V
DC bias (V)
VDS = 1 V
10–6 Fer
VDS = 50 mV roel
ect
rici
ID (A/μm)

10–8 ty

65 mV/decade Ult
10–10 ch ra-thi
an
ne n
IG, IB lF
E T
10–12
–3 –2 –1 0 1
Ph
VGS (V) a
Film se ch
ent ang
for e
ma /
tion
Fe
rrom
ag
ne
tism

(c) MRAM / spin-transistor (d) PCRAM / RRAM

2H 1T′
Side view
Kerr rotation (mrad)

Z Z′
20
0
–H +H Y Y′
–20
–1.0 –0.5 0.0 0.5 1.0
Magnetic field (T)

FIG. 1. 2DLM properties for memory application: (a) Semiconducting channel for conventional SRAM, RRAM, and Flash. Reproduced with permission from S. B. Desai, S. R.
Madhvapathy, A. B. Sachid, J. P. Llinas, Q. Wang, G. H. Ahn, G. Pitner, M. J. Kim, J. Bokor, C. Hu, H. S. P. Wong, and A. Javey, Science 354, 99 (2016). AAAS4 (b)
Ferroelectricity for Fe-FET, FeS-FET, and FeRAM. Adapted from F. Liu, L. You, K. L. Seyler, X. Li, P. Yu, J. Lin, X. Wang, J. Zhou, H. Wang, H. He, S. T. Pantelides, W. Zhou,
P. Sharma, X. Xu, P. M. Ajayan, J. Wang, and Z. Liu, Nat. Commun. 7, 12357 (2016) under the terms of the Creative Commons CC BY license.25 (c) Ferromagnetism for
MRAM, spin-transistors. Adapted with permission from B. Huang, G. Clark, E. Navarro-Moratalla, D. R. Klein, R. Cheng, K. L. Seyler, Di. Zhong, E. Schmidgall, M. A.
McGuire, D. H. Cobden, W. Yao, D. Xiao, P. Jarillo-Herrero, and X. Xu, Nature 546, 270 (2017). Copyright 2017 Springer Nature. (d) Phase change and conductive filament for-
mation for PCRAM/RRAM. Adapted with permission from Y. Wang, J. Xiao, H. Zhu, Y. Li, Y. Alsaid, K. Y. Fong, Y. Zhou, S. Wang, W. Shi, Y. Wang, A. Zettl, E. J. Reed, and X.
Zhang, Nature 550, 487 (2017). Copyright 2017 Springer Nature.101

an MoTe2 RRAM and a TMD-based selector to enable a crossbar conventional silicon devices. 2DLMs with their inherent layered-
architecture of 2DLMs memory devices will be presented. structure down to sub-1-nm body thickness for monolayers provide in
this context a promising path for the implementation of ultra-scaled
II. MEMORY ELEMENTS USING 2DLMS
FETs with good electrostatic integrity. While some research focuses on
A. DRAMs and SRAMs evaluation of 2DLM-based ultra-scaled FETs,36,37 demonstrations of
With continuous scaling of the footprint of FETs, it is a challenging 2DLM-based SRAM cells so far have been limited to long channel FETs
endeavor to avoid the occurrence of short channel effects (SCEs) in to simplify the fabrication process.

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-3

Published under license by AIP Publishing
 Applied Physics Reviews REVIEW scitation.org/journal/are

Pang et al.20 demonstrated the first WSe2-based CMOS SRAM between the E- and D-mode transistors. Vout with respective to Vin for
by implementing p-FETs through O2-plasma-induced chemical dop- an “n-FET only” flip-flop memory cell (building block of SRAM but
ing and n-FETs through electrostatic doping. As shown in Fig. 2(a), without access transistors) is shown in Fig. 2(f) with the correct logic
the two side gates (VTGN) in a tri-gate device can modulate the contact states being demonstrated. Since in this work an “n-FET only” cir-
injection and carrier concentration, allowing optimal biasing to cuitry was used, an incomplete voltage swing is observed, i.e., Vout is
achieve the desired read/write (R/W) noise margin (NM) as shown in not reaching 0 V and VDD as evident from Fig. 2(f), which would lead
Fig. 2(b), where the R/W NM was modulated by changing VTGN. The to additional power consumption.
NM was further improved by incorporating some well-known R/W For a 1-transistor-1-capacitor (1T/1C) DRAM cell, the key goal
assist techniques38 [negative bit-line voltage in Fig. 2(b) and virtual for the access transistor is to achieve minimum leakage currents (Imin),
ground in Fig. 2(c)], leading to WSe2-based SRAM operation at a since the power consumption of DRAM is dominated by the refresh
scaled VDD of 0.8 V as shown in Fig. 2(c) without R/W errors. process, which is proportional to Imin.39 As shown in Fig. 2(g) where
Wang et al.18 investigated SRAM cells based on bilayer MoS2, the electron effective mass (m) is plotted vs the bandgap (Eg) for vari-
which behaves like an n-type semiconductor due to contact Fermi- ous 2DLMs and conventional 3D materials,40 2DLMs with larger
level pinning close to the conduction band. Metal gate work function bandgap and effective mass compared with silicon may be suitable for
engineering was employed to realize both enhancement- and access transistor implementation. For example, monolayer MoS2 with
depletion-mode (E- and D-mode) MoS2 FETs [see schematic in Eg of 1.8 eV and m of 0.5m0 compares favorably to Si (Eg of
Fig. 2(d)]. Electrical transfer characteristics shown in Fig. 2(e) indicate 1.12 eV and m of 0.2m0) in suppressing gate-induced drain leak-
that a substantial threshold voltage difference has been achieved age (GIDL) and band-to-band tunneling (BTBT) currents, therefore

(a) VTGN VTG VTGN (d) E-mode D-mode

Pd AI
Vs VD
Ti/Au HfO2 Ti/Au HfO2 Ti/Au
Side Gate Side
MoS2 285 nm SiO2
Gate Gate
S Oxide
WSe2
D
Si substrate
Substrate
Vdd
0.6 0.4 102
Noise Margin (V)

Noise Margin (V)

0.5
Read (b) (c) 101 (e) 2 (f) V V
Write
Current Ids (μA/μm)

in out

0.3 100 1.8

0.4 Ion/Ioff = 107 1.6
Write 10–1
1.4
SS=88 mV/dec SRAM
10–2
Vout (V)
0.3 0.2 1.2 In: 1 In: Open In: 0 In: Open
10–3 D E 1 Out: 0 Out: 0 Out: 1 Out: 1
0.2 VBL = 0 to –0.2V Read Vds =2.0 V 0.8
0.1 10–4 Vds =1.5 V
0.6
0.1 Vds =1.0 V
Solid : Virtual GND= –0.1V 10–5 Vds =0.5 V
0.4
Hollow : Virtual GND= –0.2V Vds =0.1 V 0.2 SRAM
0.0 0.0 10–6 0
1.0 1.1 1.2 1.3 1.4 1.5 0.8 0.9 1.0 1.1 1.2 1.3 –1 –0.5 0 0.5 1 1.5 2 0 20 40 60 80 100 120
VTGN (Volts) VDD (Volts) Top-gate Voltage Vtg (V) Time (s)
1.0
Convetional 10–5 30
0.9
(g) 3D Materials
Leakage Current (A/μm)

VHold=–0.7V (j)
Electron Effective Mass

0.8 10–6 (h) WL Storage

III-V compounds (i)
Si, Ge node 20
Charge (pC)

0.7 10–7
GaN
0.6 MoTe2 0.739 BL
MoSe2 10–8
2D Materials T1
0.5 MoS2 10
Mo-bases TMDs 10–9 1T/1C cell C1
0.4 1.11
WSe2 W-bases TMDs
1.48 10–10
0.3 WTe2 Germanane 0
Si
WS2 R1
0.2 Phosphorene 10–11
3
Ge Graphane VHold=–1.5V
0.1 5 10–12 –10
10 2p+1 ac GNRs –1.5 –1.2 –0.9 –0.6 101 102 103 104 105 106
0.0
0 1 2 3 4 Hold Voltage (V) Hold Time (μs)
Bandgap (eV)

FIG. 2. (a) Schematic of a WSe2-based tri-gate device. (b) Modulation of read/write noise margin (with negative bit-line voltage as a write-assisted technique) through
electrostatic-gating (VTGN) tunability. (c) Read/write noise margin at various VDD. Scaled VDD operation at 0.8 V is achieved through VTGN modulation and virtual ground as a
read assisted technique. Reprinted with permission from C. S. Pang, N. Thakuria, S. K. Gupta, and Z. Chen, IEDM, 22–2 (2018).20 (d) Schematic of MoS2 SB-FETs with differ-
ent metal gate work functions. (e) Transfer characteristics of an enhancement- and depletion-mode transistor, revealing a noticeable threshold voltage difference. (f) Vout of the
flip-flop memory cell with different Vin. Reprinted with permission from H. Wang, L. Yu, Y. H. Lee, Y. Shi, A. Hsu, M. L. Chin, L. J. Li, M. Dubey, J. Kong, and T. Palacios, Nano
Lett. 12, 4674–4680 (2012). Copyright 2012 American Chemical Society.18 (g) Electron effective mass of 2D and conventional 3D semiconductors vs bandgap. III–V com-
pounds (black solid circles), from left to right: InSb, InAs, In0.53Ga0.47 As, InP, GaAs, Al0.3Ga0.7 As. Reprinted with permission from F. Schwierz, J. Pezoldt, and R. Granzner,
Nanoscale 7, 8261–8283 (2015). Published by The Royal Society of Chemistry.40 (h) Estimated leakage current as a function of VHold. (i) Circuit schematic of a 1T/1C cell. (j)
Calculated retained charge as a function of hold time for different VHold from –1.5 V to –0.7 V (–0.2 V per step). Reprinted with permission from C. U. Kshirsagar, W. Xu, Y. Su,
M. C. Robbins, C. H. Kim, and S. J. Koester, ACS Nano 10, 8457–8464 (2016). Copyright 2016 American Chemical Society.21

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-4

Published under license by AIP Publishing
 Applied Physics Reviews
reaching lower Imin values. Kshirsagar et al.21 investigated MoS2-based
FETs as access transistors for a DRAM cell with pico-ampere leakage
current per micrometer width being estimated as shown in Fig. 2(h),
where the hold voltage (VHold) is the voltage at the word line (WL) of
the transistor T1 shown in the 1T/1C circuitry in Fig. 2(i). The calcu-
lated retained charge as a function of hold time for various VHold in
Fig. 2(j) supports the finding of longer retention times being achieved
(when the charge reaches 0) if the access transistor can be further
“turned off” with more negative VHold, as expected.
In the context of this section that builds on the opportunities for
2DLM-based FET applications, it should be noted that despite the tre-
mendous progress this field has made, major obstacles still need to be
addressed by the scientific community. Too large contact resistance
values still pose a significant bottleneck for FETs to achieve their theo-
retically predicted performance. Further studies on the topics of reli-
able doping schemes,41–44 phase change contacts,45,46 and contact
Fermi-level de-pinning47–49 are required to further lower the contact
resistance and facilitate the integration of 2DLM-based CMOS for a
beyond-Si era.
B. FeRAMs
In ferroelectric memories, the information is stored by the polari-
zation direction in a ferroelectric layer, which enables nonvolatile
memory devices. In recent years, 2DLMs have been introduced to fer-
roelectric memory devices to improve device performance and enable
new applications. Liu et al.25 reported room-temperature ferroelectric-
ity in a layered 2D insulator, CuInP2S6 (CIPS). Using piezo-response
force microscopy (PFM), ferroelectric polarization switching is
observed in a 4-nm-thick CIPS sample, and ferroelectric memory devi-
ces with excellent performance have been achieved. Wu et al.50 dem-
onstrated a 2D ferroelectric tunnel junction (FTJ) based on a vdW
heterojunction with CIPS as the tunneling barrier and graphene and
Cr as asymmetric electrodes [Fig. 3(a)], which exhibits a large tunnel-
ing electro-resistance (TER) of over 107, the best reported to date
[Fig. 3(b)]. The origin of the large TER is mainly attributed to the
modulation of the barrier height between graphene and CIPS when
the ferroelectric polarization reversal induces charges at the CIPS/gra-
phene interface and causes a Fermi-level shift in graphene [Fig. 3(c)].
Due to the low density of states in graphene near its Dirac point, the
Fermi-level shift can be as large as 1 eV, which is confirmed by Raman
spectroscopy and Kelvin probe force microscopy (KPFM). Furthermore,
the large out-of-plane effective mass of CuInP2S6 (1.3 m0) due to weak
vdW bonding in the vertical direction also contributes to the large TER
ratio. The 2D FTJ also exhibits excellent data retention, retaining a TER
ratio above 107 after more than 8 h and extrapolated retention time
above 10 yr [Fig. 3(d)]. The good retention performance of FTJs made
from metal-ferroelectric-metal (MFM) stacks using 2D ferroelectric
material is the result of the elimination of depolarization fields with a
complete charge compensation from the metal electrodes, as pointed out
in previous studies.51 By contrast, in FTJs with conventional ferroelectric
materials such as HZO, an additional dielectric layer such as aluminum
oxide is often inserted as a tunneling barrier, resulting in a metal-ferro-
electric-insulator-metal (MFIM) stack,52 in which the depolarization
field would show up again without the complete charge compensation,
and cause a degradation of retention time.
Apart from improving the performance of 2D ferroelectric insu-
lator devices, new device concepts have been developed employing
Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013
Published under license by AIP Publishing
REVIEW scitation.org/journal/are
ferroelectric semiconductors. Si et al.29 investigated a novel device
structure, ferroelectric semiconductor FET (FeS-FET), using a-In2Se3,
a 2D ferroelectric semiconductor. Different from conventional ferro-
electric FETs (Fe-FETs), in which the gate insulator is ferroelectric,
FeS-FETs use a ferroelectric semiconductor as channel material and a
high-quality amorphous oxide as the gate insulator [Fig. 3(d)].
Therefore, the charge trapping and leakage current in conventional
Fe-FETs can be eliminated, resolving the issue of short retention times.
The working mechanism of a FeS-FET is illustrated in Fig. 3(e).
Assuming a full polarization switching in the ferroelectric semicon-
ductor, in the polarization down-state, there are no mobile charges in
the channel so that the channel resistance is high, while in the polari-
zation up-state, electrons can accumulate at the top surface of the
channel and the channel resistance is low. Therefore, a counterclock-
wise hysteresis loop is expected. Figure 3(f) shows the transfer charac-
teristics of an a-In2Se3 FeS-FET with Atomic Layer Deposition (ALD)
passivation and 15-nm HfO2 as the gate insulator. A counterclockwise
hysteresis loop is observed, in accordance with the analysis of a full
polarization switching, and a high on/off ratio of >108 is achieved.
While performance metrics such as retention time, endurance, and
switching speed have not yet been characterized for the FeS-FET, the
unique operating mechanism may enable the possibility to outperform
conventional Fe-FETs.
While 2D ferroelectric materials have shown the potential of
boosting the performance of existing ferroelectric memories and
enabling new devices such as FeS-FET, large-area growth of 2D ferro-
electric materials remains a challenge and the demonstration of mem-
ory arrays using 2D ferroelectric materials is still lacking. Moreover,
although 2D ferroelectric materials such as CIPS have demonstrated
robust ferroelectricity when their thickness is scaled down to a few
nanometers,13 further studies are needed on the lateral scaling limit,
which will affect the density of ferroelectric memories.
In addition to 2D ferroelectric layered materials, memory devices
combining conventional ferroelectric materials and non-ferroelectric
2DLMs, such as MoS2, as channel materials have also been stud-
ied,53–56 in which the ultra-thin body of a 2DLM channel enables the
scaling of Fe-FETs for high-density memory arrays. Zhang et al.53
demonstrated an Fe-FET with MoS2 channel on a 2-nm Al2O3/6-nm
HZO/pþ Si substrate [Fig. 3(h)]. The Al2O3/HZO stack was deposited
using CMOS-compatible ALD process and exhibits polarization-
voltage (P-V) hysteresis loops, as shown in Fig. 3(i). The Fe-FET
shows a high on-off current ratio of more than 107, as shown in
Fig. 3(j), and a counterclockwise memory window of 0.1 V under a
low working voltage of 63 V is achieved, thanks to the thin ferroelec-
tric layer of 6-nm HZO. Furthermore, the data retention performance
is characterized, as shown in Fig. 3(k), showing negligible degradation
of memory window up to 104 s and retention time over 10 yr from
extrapolation.
For FeRAM applications, 2DLMs with a strong intralayer chemi-
cal bonding but a weak interlayer van der Waals interaction typically
exhibit a breaking of symmetry that goes beyond the limitations of 3D
materials. The breaking of symmetry has been reported including, but
not limited to, 2DLMs with odd-layered numbers,57 1T-MoS2 with
different charge density induced by Mo displacement,58 and in
1T-2DLMs with distorted octahedral coordinated structure.59 While
conventional FeRAMs will experience unstable operations at room
temperature with a channel thickness being merely a few unit cells, a
8, 021306-5
 Applied Physics Reviews REVIEW scitation.org/journal/are

Vacuum Vacuum
(a) (b) (c)
A 10–5 Φm = 4.5 eV Φm = 4.5 eV3.7 eV 5.2 eV
3.7 eV 4.22 eV Tunnelling
Tunnelling
Au/Cr 10–7 current
current

Current (A)
Solid: experiment On
10–9 Dashed: simulation Off
CIPS
EF EF
10–11
G
10–13 Cr CIPS Graphene Cr CIPS Graphene
4 nm CIPS
On Off
–1.0 –0.5 0 0.5 1.0
Voltage (V)
10 nm AI2O3
(e) (g)
Au Au
(d)
1012 Source Drain Source Drain Ti Ti
α-In2Se3
Semiconductor Ferroelectric Semiconductor
1011 15 nm HfO2 or 90 nm SiO2
Ferroelectric insulator Conventional insulator
1010 p+Si
Vread = 0.4 V 1 year Gate Gate
Resistance (Ω)

109 Fe-FET FeS-FET 10 –3

10 years (f) 10–4 Lch = 1 μm

108 Off
10–5
On P down
107 P up 10–6

ID (A/μm–1)
10–7
106 ID,LE
10–8
105 Insulating 10–9
10–10
4
10 VDS = 0.05 V
10–11
100 101 102 103 104 105 106 107 108 109 10–12 VDS = 0.5 V
Time (s) P up P down 10–13
VGS VDS = 1 V
10–14
10–15
Conducting
–6 –4 –2 0 2 4
MoS2 Gate Oxide Semiconductor VGS (V)
(h) Ti/Au Ti/Au
(s) (D)
2 nm AI2O3
6 nm HZO (j) (k)
1000 0.6
p+ Si (G) ± 6.5 V Program/Erase
Drain Current IDS (μA/μm)

100
Memory Window (V)

10 ±6V 5.5 V/–5.5 V, 10 ms

(i) 2 VDS = 0.5 V
±2V 1
±3V 0.4
Polarization P (μC/cm2)

0.1
1 ±4V
0.01
1E–3
0 Ti/Au 0.2
Al2/O3 1E–4
VDS = 0.5 V
HZO 1E–5
p+ Si
–1 1E–6 LG = 2 μm
6 nm HZO/2 nm AI2O3 1E–7 0.0
f = 1 kHz –6 –4 –2 0 2 4 6 10–1 101 103 105 107 109
–2 Gate Voltage VGS (V) Times (S)
–8 –6 –4 –2 0 2 4 6 8
Voltage V (V)

FIG. 3. Ferroelectric memories with 2DLMs. (a) Schematic of a Cr/CIPS/graphene FTJ on the SiO2/Si substrate. (b) I-V characteristics of the vdW FTJ with 4-nm CIPS and
monolayer graphene contact, showing TER above 107 between the on and off states. (c) Band diagrams for the on and off states of the vdW FTJ operation. (d) Data retention
characteristics of the FTJ, showing an extrapolated retention time beyond 10-yr mark. Adapted with permission from J. Wu, H. Y. Chen, N. Yang, J. Cao, X. Yan, F. Liu, Q.
Sun, X. Ling, J. Guo, and H. Wang, Nat. Electron 3, 466–472 (2020). Copyright 2020 Springer Nature.50 (e) Schematic of a Fe-FET and a FeS-FET. (f) Band diagram of a
FeS-FET in polarization (P) up and down states and the corresponding ID-VGS characteristics. A counterclockwise hysteresis is expected for full polarization switching. (g) ID-
VGS characteristics of a representative a-In2Se3 FeS-FET with 15-nm HfO2 as dielectric and ALD passivation. Inset: schematic of the experimental a-In2Se3 FeS-FET. Adapted
with permission from M. Si, A. K. Saha, S. Gao, G. Qiu, J. Qin, Y. Duan, J. Jian, C. Niu, H. Wang, W. Wu, S. K. Gupta, and P. D. Ye, Nat. Electron 2, 580–586 (2019).
Copyright 2019 Springer Nature.29 (h) Device structure of the MoS2/HZO Fe-FET. (i) P-V hysteresis loops for the Al2O3/HZO capacitor. (j) DC transfer characteristics of the
MoS2/HZO Fe-FET, showing counterclockwise hysteresis. (k) Data retention characteristics of the MoS2/HZO Fe-FET. Adapted from S. Zhang, Y. Liu, J. Zhou, M. Ma, A. Gao,
B. Zheng, L. Li, X. Su, G. Han, J. Zhang, Y. Shi, X. Wang, and Y. Hao, Nanoscale Res. Lett. 15, 157 (2020) under the terms of the Creative Commons Attribution 4.0
International License.53

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-6

Published under license by AIP Publishing
 Applied Physics Reviews
2DLM-based ferroelectric fabric has the potential for a nondestructive
and more reproducible performance. One of the main challenges of its
development is that most of the explorations of new 2D ferroelectric
materials is still based on simulations and theoretical predictions with
just a few experimental demonstrations. This prevents unambiguously
revealing the true ferroelectric mechanisms due to abundant possibili-
ties that may lead to ferroelectric properties in 2DLMs. Another chal-
lenge that is worth pointing out is that multiple techniques for proving
2D ferroelectricity have been recommended. For example, although it
is a common standard to use piezoresponse force microscopy (PFM)
to characterize ferroelectric properties, which is an easy-to-handle and
nondestructive tool to map out the domain structure, ferroelectric-like
hysteresis loops may still exist in non-ferroelectric materials, which are
attributed to an electrochemical response,60,61 a static electric effect,62
the environmental influence,63 and charge injection.64 In light of this,
scanning tunneling microscope (STM), which provides direct observa-
tions of the local electronic structure; scanning tunneling spectroscopy
(STS), which offers information on the electronic density of states of
materials; and transmission electron microscopy (TEM), which reveals
the crystal structure/atom displacement with high spatial resolution,
should be employed to justify the evidence of ferroelectricity and to
further understand the main mechanism being responsible for the
observed phenomenon.
C. MRAMs
The discovery of the giant magnetoresistance (GMR)65 and the
proposal of the Datta-Das spin-transistor66 started a new era of spin-
tronics research utilizing the electron spin as a means of performing
logic or memory functions. In general, the working principle of spin-
tronic devices involves manipulation and reading of magnetic
moments in ferromagnets by electrical means. Nano-scale MTJ used
in STT-MRAM technology consists of two ferromagnetic (FM) layers
(free and fixed) separated by a tunnel barrier. In MTJs, the relative
magnetic moments of two FMs result in two distinguished resistance
states (low and high, respectively) providing electrical means to read
the magnetic state, i.e., read the stored memory bit. On the other
hand, a charge current flowing through the MTJ can generate suffi-
cient spin-torque to switch the free FM, i.e., write the desired memory
bit. Furthermore, perpendicular magnetic anisotropy (PMA) in ferro-
magnets has enabled scaling of MTJs down to a few tens of nano-
meters in diameter.67 While MTJ technology offers unique advantages
including BEOL compatibility (processing temperature < 400  C),
non-volatility (retention 10 yrs), high endurance (unlimited), and
speed (10 ns), improvements are desired to achieve even higher
switching speeds that could rival DRAM (10 ns) or even SRAM
(< 1 ns). Moreover, there is the need for improvements regarding the
energy consumption (related to critical current densities) and read
margin for wide commercialization of STT-MRAM technology.
Hence, novel device concepts have been proposed with alternative
write units such as spin–orbit torque (SOT),68 voltage-controlled mag-
netism,69 and read units using inverse Spin Hall effect,70 and SOT-
FET,71 which will also require novel material systems.
In 2018, researchers showed that exfoliated 2D flakes of VSe2,72
CGT,73 and CrI324 retain their magnetism even in the monolayer limit.
After these initial findings, the list of ferromagnetic 2D materials has
expanded to include Fe3GeTe2 (FGT),74 CrX3 (X ¼ Br, I),75 and
CrSiTe3.76 These 2D ferromagnetic materials offer diverse electrical
Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013
Published under license by AIP Publishing
REVIEW scitation.org/journal/are
properties, e.g., metallic FGT and semiconducting CGT, and cover a
wide range of magnetic properties including in-plane (VSe2) and per-
pendicular magnetic anisotropy (CGT) with ferromagnetic (CGT) and
antiferromagnetic interlayer coupling (CrI3). Such rich electronic and
magnetic properties found in 2D-FMs along with their ability to form
heterostructures, spin-torque control of magnetism, and the electro-
static control of magnetic properties provide unique opportunities to
realize not only conventional devices such as MTJs but also novel
memory device concepts, as mentioned in the previous paragraph.
Assembling a heterostructure consisting of 2DLM-FMs similar to
MTJs with good tunneling magnetoresistance (TMR) ratio is essential
to implement technology-relevant memory devices. This was recently
demonstrated using a vdW heterostructure consisting of a FGT/hBN/
FGT stack [Fig. 4(a)] with FGT as the FM layers and hBN as the tun-
nel barrier.33 Wang et al.33 reported a TMR (measured with magnetic
field) ratio up to 160% (though at low temperature) as shown in Fig.
4(b), which is comparable to traditional CoFeB/MgO/CoFeB-based
MTJs. Theoretically, these vdW heterostructures are expected to
exhibit much larger TMR ratios (up to 6250%)77 compared to the
maximum theoretical prediction of 1000% in conventional material
systems. Experiments by Song et al.27 have shown that TMR ratios in
few-layer CrI3, where a vdW air-gap acts as a tunnel barrier between
each of the FM monolayers, can reach as high as 19 000%, which is
much larger than the experimentally observed 600%78 for in-plane
MTJs that are limited mostly by imperfections of the lattice and inter-
faces. Note that the much higher TMR discovered in 2DLMs is a result
of the fundamentally different physics that is expected to mediate the
resistance contrast. While in conventional MTJs the MgO tunnel bar-
rier is crucial as a spin filter and interface effects have a large impact
on the device performance, interfacial effects are expected to be less
relevant for 2D-based MTJs, and spin dependent electronic properties
of the FM will determine the TMR.
While STT-switching of 2DLM-FMs has yet to be demonstrated,
spin–orbit torque (SOT) switching has been reported for multiple
2DLM-FMs. SOT offers an alternative to STT with higher switching
speeds, being more energy efficient and providing better endurance
performance specs. While materials with large spin Hall angle, e.g.,
topological insulators (TI), are desired for efficient SOT switching, the
high resistivity of these materials relative to the metallic FM layer in
contact (e.g., CoFeB) is a major roadblock. The problem arises due to
current shunting through the metallic layer, which makes the SOT
switching of conventional FMs less efficient. On the other hand, semi-
metallic and semi-insulating 2DLM-FMs can provide a path to inte-
grate with highly resistive spin Hall materials to form more effective
SOT devices. Researchers have used the spin Hall effect (SHE) of
heavy metals (HMs) (Pt, Ta) to switch the magnetization of both
metallic79 and semiconducting80 2DLM-FMs. In an article from
Alghamdi et al.,79 field-assisted SOT switching of metallic FGT by Pt
was reported at current densities of 2.5  107 A/cm2 [Fig. 4(c)].
Much lower current densities of 5  105 A/cm2 were reported for
SOT switching of semiconducting FM-CGT.80 As shown in Fig. 4(d),
switching current densities required for 2DLM-FMs are the lowest
among different material systems and are expected to be reduced fur-
ther when combined with large SHE materials such as TI.
Furthermore, the implementation of 2DLMs with strong spin-orbit
coupling (SOC), e.g., WTe281 or layered TIs82 e.g., Bi2Te2Se or Bi2Te3,
provides opportunities to assemble vdW-heterostructure-based SOT
8, 021306-7
 Applied Physics Reviews REVIEW scitation.org/journal/are

1 +3 kOe
(a) hBN (c) +6 kOe
(e)

RH /RHo
+9 kOe
0
z M Vtg Graphite Graphite
VH HDL hBN hBN
A 2L Graphite 2L Graphite
H0 –1
FGT FGT Jx X 0 2 4 6
SiO2 Pt Jx (1011 A/m2)
1
Si 2L Graphite 2L Graphite
T

RH /RHo
hBN hBN
FG Graphite Graphite
0
FGT: Fe3 GeTe2 –3 kOe
(b) –6 kOe
–9 kOe
(f)
–1
0 2 4 6
50 160 (d) Jx (1011 A/m2)
TMR (%)
R (kΩ)

103 1.0

G (μS)
19 0 TI/MnGa
102 (150 K) Pt/FGT

d
ire
0.5
Hx (mT)

–1.50 –0.75 0.00 0.75 1.50 (150 K)

es
D
B (T)
101 Ta/CGT
(10 K) W/TMIG Ta/CoFeB 0.0
(300 K) (300 K)

100 –10 0 10
105 106 107 Gate voltage (V)
Current Densities (A/cm2)

FIG. 4. (a) vdW heterostructure (FGT/hBN/FGT) for a 2DLM-based MTJ-type device. (b) TMR of 160% observed in the vdW heterostructure. Adapted with permission from
Z. Wang, D. Sapkota, T. Taniguchi, K. Watanabe, D. Mandrus, and A. F. Morpurgo, Nano Lett. 18, 4303 (2018). Copyright 2018 American Chemical Society.33 (c) Device struc-
ture and experimental demonstration of field-assisted SOT switching of FGT using SHE in Pt. Current densities required are similar to SOT switching of conventional FMs such
as CoFeB. Adapted with permission from M. Alghamdi, M. Lohmann, J. Li, P. R. Jothi, Q. Shao, M. Aldosary, T. Su, B. P. T. Fokwa, and J. Shi, Nano Lett. 19, 4400 (2019).
Copyright 2019 American Chemical Society.79 (d) Current densities for field-assisted SOT switching across various material systems, including semiconducting 2DLM-CGT,
offering the lowest switching current densities of 5  105 A/cm2. Adapted with permission from V. Ostwal, T. Shen, and J. Appenzeller, Adv. Mater. 32, 1 (2020) under the terms
of the Creative Commons CC BY license.80 (e) vdW heterostructure used for the demonstration of a spin-transistor using gate-controlled interlayer magnetic coupling in CrI3.
(f) Gate voltage–controlled tunnel conductance of CrI3 as a function of gate voltage showing a similar behavior if compared to “transfer curves” in CMOS transistors, with the
additional benefit of non-volatility. Adapted with permission from S. Jiang, L. Li, Z. Wang, J. Shan, and K. F. Mak, Nat. Electron. 2, 159 (2019). Copyright 2019 Springer
Nature.28

devices. Having experimentally demonstrated an individual write unit
(SOT controlled FGT) and a read unit (FGT/HBN/FGT MTJ), inte-
gration of these units into a single SOT-MRAM type device is a natu-
ral step to further prove the viability of 2D-FM-based MRAM devices.
Beyond current control of magnetism using STT or SOT, volt-
age control of magnetism using either voltage controlled magnetic
anisotropy (VCMA), voltage-controlled exchange coupling
(VCEC), or the magnetoelectric effect (ME) are being extensively
explored for future energy-efficient spintronic devices.
Electrostatic gate control of magnetic properties in semiconducting
2DML-FMs offers attractive opportunities to implement such
spin-devices. In the experiments performed by Verzhbitskiy
et al.,83 ionic gating/doping of CGT was able to manipulate the
magnetic anisotropy (resulting in a transition from PMA to in-
plane anisotropy) and increased the Curie temperature from 70 K
to 200 K for undoped few-layer CGT. It has also been shown that
electrostatic gating can affect the saturation magnetization, coer-
civity and Curie temperature for monolayer CrI3 and the interlayer
magnetic coupling in bilayer CrI3.84 Jiang et al.28 have used a gate
voltage to switch the magnetic ordering of a bilayer CrI3 between
the ferromagnetic and anti-ferromagnetic states, and utilized such
gate-controlled interlayer-coupling as a write unit. Such change in
magnetic order can result in a large TMR when a current is passed
in the vertical direction through the bilayer CrI3 in a vdW hetero-
structure, as shown in Fig. 4(e), which acts as a read unit. Using
these write and read units, Jiang et al. have successfully demon-
strated a nonvolatile spin-transistor, i.e., gate-controlled tunnel
conductance [Fig. 4(f)],28 similar to the Datta-Das transistor,
which has been a holy grail of spintronics research since its pro-
posal in 1989.
While ferromagnetic 2DLMs have enabled researchers to fabri-
cate vdW heterostructures to implement not only MTJ-type conven-
tional memory devices but also novel device concepts such as
spin-transistors, progress toward improving Curie temperatures by
material engineering,39,40 doping effects,83 or strain engineering,86 and
growth of wafer-scale films87 is essential for the wide integration of
2DLM-FMs in future spintronic technologies.
For MRAM applications, the uniqueness and most promising
advantage of 2DLMs lie in a precise control of the ultimate thickness
(to avoid thickness-variation-induced device variability) and sharp
interfaces (for better heterogeneous integrations). Several applicable
fields of 2DLMs in MRAM were brought up in the manuscript with
their advantages, including the tunnel barrier and 2D ferromagnetics
with high TMR ratios and SOT with high spin Hall angle to achieve
more efficient switching, compared to existing incumbents. On the
other hand, these research efforts are still in their infancy and need

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-8

Published under license by AIP Publishing
 Applied Physics Reviews REVIEW scitation.org/journal/are

more understanding in order to overcome some major challenges. movement and (ii) metallic ions diffusion. However, the biggest
In addition to the low Curie temperatures of emerging 2D ferromag- challenge for conventional RRAM arises from the fact that it
netics mentioned in our manuscript, the oxidation or contamination relies on top-down lithographic patterning that has limited the
during the integration processes will unavoidably lead to inferior scalability, control, and tunability of device functionality due to
device performances compared to the theoretically predicted values. It the strong dependence of surface effects including surface rough-
takes 2–3 decades of research and developments for STT-MRAM to ness, defects, and dangling bonds. Similar to filamentary RRAM
be commercialized; we believe time-to-maturity will be greatly reduced devices, some insulating and semiconducting 2DLMs sand-
for these emerging 2DLMs once it can be well synthesized with high wiched between metal electrodes show resistive switching behav-
uniformity, leading to more statistically uniform MRAM device ior due to conductive filament formation driven by ion/vacancy
performances. migration. Puglisi et al.94 was the first to demonstrate such an
RRAM device using electric-field-induced diffusion of Boron in
D. RRAMs and PCRAMs a few-layer hBN. These devices offered low set/reset voltages
(0.5 V) and on/off current ratios of 10 to 100. One of the
In RRAM and PCRAM technologies, two resistance states,
important characteristics of RRAM is its on/off ratio, which can
namely a high resistance state (RHRS) and a low resistance state (RLRS)
be as high as 109 for 2DLM RRAM devices,95 surpassing their
of a two-terminal cell can be switched by utilizing electrical stimuli—
conventional RRAM counterparts, which typically exhibit ratios
such as an electric field—and are used to store information in bit
of 106.96 Further research from Ge et al.97 showed that RRAM
format—either 0 (RHRS) or 1 (RLRS). In the case of RRAM devices, a
behavior is also present in semiconducting 2DLMs, such as
resistance change is generally a result of changes in a conductive
monolayer MoS2, offering low operating voltages and forming-
filament formed within a metal-insulator-metal structure, when sub-
free switching. However, more research is required to under-
jected to an electric field. In contrast, in PCRAM, the resistance change
stand the underlying mechanism behind such resistive switching
occurs due to phase change between the crystalline and amorphous
in monolayer 2DLMs.
phase. Two-terminal RRAM/PCRAM cells along with selector devices
2. Grain boundaries: Sangwan et al.98 reported that an ionic move-
allow the implementation of crossbar architectures, which provide
ment of sulfur vacancies at the grain boundaries of MoS2 can be
higher storage densities compared to SRAM or DRAM but offer lower
used in a lateral transistor device to generate resistive switching.
endurance cycles and switching speeds.
While the on/off ratio of the device depends on the position of
On the other hand, 3D RRAM/PCRAM are expected to provide
the grain boundaries, the best performing devices showed an on/
similar storage densities compared to 3D NAND Flash technology at
off ratio of 103. Furthermore, the unique functionality of a gate-
higher speed and endurance88,89 in the binary (or few states) NVM
tunable Vset, RLRS, RHRS, and on/off ratio offered by these devices
application space. Hence, they are considered candidates for storage-
is useful for improving device-to-device variations and for the
class memory technology as a new tier in the memory hierarchy.89
implementation of continuous synaptic weights for neuromor-
Furthermore, BEOL compatibility, non-volatility, and synaptic behav-
phic computing.
ior (continuous change of resistance when subjected to electrical
3. Atomic switches: In lateral devices consisting of a graphene
inputs) of these memory cells make them potential candidates for
channel, electric fields can drive the motion of carbon atomic
“analog” in-memory computing90 and neuromorphic computing.91
chains forming and subsequently breaking by Joule heating.99
However, non-linearities and asymmetry switching in the synaptic
This results in voltage-controlled high and low resistance states
behavior, stochasticity (device-to-device variations, cycle-to-cycle
in lateral graphene device. However, such devices showed limited
variations), and low on/off ratio are major challenges to large neural
on/off ratio (50100), and slow switching speeds (100 ms).
networks based on RRAM devices. While research has been focusing
Repeated switching over 500 cycles was reported, but the endur-
on improving the feature size (< 5 nm), operating voltages (< 1 V),
ance of these devices still needs to be explored.
switching speeds < 1 ns), endurance (1011 cycles), read current
4. Charge density wave function: In TaS2, a nonvolatile resistance
(100 pA), and write energy (0.1 fJ/bit) of conventional RRAM/
change was reported by Vaskivskyi et al.100 due to the transition
PCRAM devices according to the IRDS,92 recent experiments have
of an ordered polaronic Mott insulating state to a metallic elec-
shown that resistive switching in 2DLMs may offer opportunities to
tronic state within textured domain walls when subjected to a
address the above challenges more readily.
charge pulse. The switching speed of such devices can reach up
In this article, we will mostly focus on resistive switching behav-
to 30 ps, which is faster than any other reported nonvolatile
ior in clean 2DLM, even though RRAM behavior has been observed in
memory. Even though the reported on/off ratio of 10 was
partially oxidized89 or solution processed93 2DLMs. Using the diverse
observed at low temperatures (150 K), room temperature oper-
electronic and chemical properties of 2DLMs, researchers have dem-
ation may be achievable in an alternative charge density wave
onstrated nonvolatile resistive switching based on various underlying
system.
mechanisms as listed below and shown in Fig. 5, which offer unique
5. Phase change memory: Some TMDs exist in various crystalline
advantages over their conventional counterparts:
phases with varying electrical properties. Researchers have
1. Ion/vacancy migration: Today’s filamentary RRAMs from a exploited such polymorphism to show electrically driven resistive
metal/insulator/metal structure that shows a high reliability are switching in TMDs, especially in MoTe2, which exhibits a low
based on insulating transition metal oxides such as Al2O3, HfOx, energy difference between the semiconducting 2H and the metal-
TaOx, and TiO2. The switching occurring in the insulating layer lic 1T’ phase. Wang et al.101 optically detected (using Raman
can be classified into two major mechanisms of (i) vacancies spectra) such a phase transition with a finite memory window

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-9

Published under license by AIP Publishing
 Applied Physics Reviews REVIEW scitation.org/journal/are

Ions or vacancies

(e) (a)

Monolayer MoS2
Ta (d) (b)
S
Au

SiO2
(c) Si

Grain boundary

Graph
ene
Graph
ene

FIG. 5. Various physical mechanisms underlying resistive switching in 2DLMs. (a) Ion/vacancy migration-conductive filament formation. (b) Grain boundary movement in MoS2
lateral devices. Adapted with permission from V. K. Sangwan, D. Jariwala, I. S. Kim, K. S. Chen, T. J. Marks, L. J. Lauhon, and M. C. Hersam, Nat. Nanotechnol. 10, 403
(2015). Copyright 2015 Springer Nature.98 (c) Atomic switching due to the atom chain formation in graphene nanogaps. Adapted with permission from L. Cai, C. J. McClellan,
A. L. Koh, H. Li, E. Yalon, E. Pop, and X. Zheng, Nano Lett. 17, 3854 (2017). Copyright 2017 American Chemical Society.42 (d) Charge density wave function in TaS2. Adapted
with permission from M. Yoshida, R. Suzuki, Y. Zhang, M. Nakano, and Y. Iwasa, Sci. Adv. 1, 1500606 (2015) under the terms of the Creative Commons CC BY license.111
(e) Phase transition in MoTe2.

when MoTe2 flakes were subjected to electrostatic doping, i.e.,
gate voltages. The first RRAM/PCRAM 2-terminal device dem-
onstrated by Zhang et al.26 consisted of a semiconducting few-
layer 2H-MoTe2 flake sandwiched between metallic or graphene
electrodes. In such a device, the electric-field-induced resistance
switching was observed concurrent with a phase transition
between 2H and 1T’ or 2Hd, which is a newly discovered dis-
torted phase. This finding was confirmed by high-angle annular
dark-field scanning transmission electron microscopy (HAADF-
STEM) imaging. These devices showed thickness-dependent set
voltages and on/off ratios of 50. Furthermore, fast switching of
< 10 ns and a large on/off ratio of 106 using a MoTe2/Al2O3 het-
erostructure were reported. Subsequent studies have reported
multi-level resistive switching in such vertical devices as desired
for implementation of synaptic devices102 and phase-change
resistive switching, even in lateral MoTe2 devices.103
2DLMs can be used to not only realize active memory layers as
discussed in the previous paragraphs but also serve as channel materi-
als for access transistors or selector devices that are necessary for
RRAM/PCRAM technology. Sivan et al.34 used a WSe2 transistor and
oxidized top layers (converting WSe2 into WO3) to achieve RRAM
behavior, for the demonstration of a 1T1R (1-transistor 1-resistor)
memory cell, a proof-of-concept integration of “logic” and “memory”
units for a monolithic 3D chip. Later in this article, we will discuss
vdW heterostructures consisting of MoTe2 RRAM- and TMD-based
selector devices104 to enable a crossbar architecture of 2DLMs memory
devices. While wafer-scale growth of 2DLMs and fabrication of large-
scale memory devices with low variability remain major challenges,
these exploratory devices have collectively shown that resistive switch-
ing in 2DLMs can achieve fast switching speeds, low set voltages, large
on/off ratios, and on-chip integration of “logic” and “memory” units.
III. 2DLM-BASED DEVICES FOR RRAM TECHNOLOGY
2D MoTe2-based RRAM is an entirely new vdW phase change
device concept. A uniform switching in MoTe2 takes place under an
electric field different from conventional RRAM, where the filament
formation occurs arbitrarily and only over a very small radius.
Figure 6 shows optical and SEM images and displays schematically the
layout of a vertical MoTe2 device. A bottom electrode Ti/Au (10 nm/
25 nm) was deposited onto a Si/SiO2 substrate. Next, 2H phase

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-10

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 Applied Physics Reviews
(a) 500 nm SiO2
Top electrode
TMD
Bottom electrode
(b)
Top e
le ctrod
e
SiO2
TMD
Bottom electrode
FIG. 6. (a) Optical and SEM images. (b) 3D cartoon of MoTe2 vertical device.
Adapted with permission from F. Zhang, H. Zhang, S. Krylyuk, C. A. Milligan, Y.
Zhu, D. Y. Zemlyanov, L. A. Bendersky, B. P. Burton, A. V. Davydov, and J.
Appenzeller, Nat. Mater. 18, 55–61 (2019). Copyright 2019 Springer Nature.26
semiconducting few-layer MoTe2 flakes were exfoliated onto the bot-
tom electrode using standard scotch tape techniques, followed by ther-
mal evaporation of a 55-nm-thick SiO2 insulating layer covering the
entire bottom electrode except a hole on the flake with the desired
diameter. The device fabrication was completed by the deposition of a
Ti/Ni (35 nm/50 nm) top electrode. The SiO2 insulating layer’s pur-
pose is to ensure that only vertical transport across the MoTe2 layers
occurs between the two electrodes and that there is no lateral transport
contribution.
To understand the filament formation mechanism in MoTe2
RRAM devices, a careful study was performed not only on MoTe2 but
also Mo1–xWxTe2 for various x between 0.03 and 0.09. All devices in
this x-range showed the same behavior, and we will not distinguish in
the following between x ¼ 0 and finite x-values up and including
0.09.26 Figure 7(a) shows a cross section STEM image of an RRAM
device. The Mo0.96W0.04Te2 RRAM structure is clearly visible from the
HAADF contrast image in Fig. 7(a), displaying the Mo0.96W0.04Te2
layers both in the active region and non-active region under the SiO2
isolation layer where the electric field is too small to switch the TMD’s
phase. In the active region, the zoom-in HAADF image of the red-
marked box in Fig. 7(b), two structurally distinct domains can be
clearly recognized, namely an intrinsic 2H phase and a distorted 2Hd
phase. As Fig. 7(b) shows, in the low resistive state, a distorted 2Hd
state was identified in the active region extending vertically throughout
the Mo0.96W0.04Te2 thickness. The rather uniform diameter of the 2Hd
phase is 80 nm. The diffraction patterns of 2Hd in Fig. 7(e) are very
similar to the corresponding pattern from 2H, which is surprising,
Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013
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REVIEW scitation.org/journal/are
considering the clear differences in the atomic images of these two
regions, Figs. 7(c) and 7(d). Most of the devices studied in the way
described above exhibited similar behavior: 2H structure in the matrix
and 2Hd structure in the filament as shown in Fig. 7(f). However, one
device as shown in Fig. 7(g) displayed a filament consisting of the 2H
phase together with the orthorhombic Td phase. This was an unex-
pected finding since 1T’ MoTe2 should be more stable than the Td
phase at room temperature and above. This observation is a clear indi-
cation that the Td phase can be stabilized in a heterostructure due to
the particular boundary conditions. Preliminary DFT calculations
show that the 2Hd structure is a distorted modification of the 2H
structure—a transient state with atoms displaced to the sites of lower
symmetry, but still within atomic arrangements of the 2H structure,
which is induced by an electric field. The slightly different atomic posi-
tion change causes the change of the conductivity, while both are crys-
talline structures. This intrinsic material property gives rise to the fast
switching speed in these RRAM devices, which will be discussed later.
Figure 8(a) displays I-V curves of a MoTe2-based RRAM device
before and after forming and successive cycling through its high resis-
tive state (HRS) and low resistive state (LRS). For all measurements,
the bottom electrode was grounded. When the device reaches the
forming voltage, there is an abrupt current increase to the current
compliance. The device is in its LRS, which is the 2Hd state, and a reset
voltage of opposite polarity is needed to bring the device back to its
HRS, which microscopically means that part of the 2Hd filament is
converted back to the 2H phase. LRS and HRS are enabled by the set
and reset voltage. Stable and reproducible bipolar RRAM behavior was
observed. Figure 8(b) summarizes how the set voltages scale with the
MoTe2 layer thickness. For flake thicknesses below 10 nm, set voltages
lower than 1 V can be achieved. The dependence of the LRS current at
a bias of 0.3 V as a function of the area of the RRAM device is shown
in Fig. 8(c), where the color represents the MoTe2 flake thickness. As
the device area decreases, while being still larger than about
80 nm80 nm ¼ 6400 nm2, the current remains constant. Devices that
exhibit smaller areas show a monotonic, in fact, linear decrease of the
LRS current with the device area. The observed trend is independent
of the TMD thickness. Interestingly, the linear decrease in current
occurs when the dimensions of the device become smaller than the
previously observed size of the 2Hd filament [see Figure 7(b)]. This
observation is consistent with the notion that the entire device area is
converted into the 2Hd phase once the device dimensions are smaller
than the achievable filament size, which is about 80 nm80 nm.
Compared with conventional RRAM devices whose operation rely on
the random formation of a filament, MoTe2-based RRAM devices
allow for a completely uniform filament under the electrodes, and thus
the current scales with the device area. This property in MoTe2 makes
the filament formation more controllable and offers the opportunity to
address reliability issues in conventional RRAM devices.
Compared with phase change memory PCM-based devices that
operate based on a change between an amorphous and a crystalline
structure, one can expect that MoTe2-based RRAM should exhibit
faster switching. Figure 9(a) shows the experimental measurement
setup for the switching speed testing of MoTe2 RRAM devices. By
varying the input pulse width and amplitude, the oscilloscope moni-
tored the current through the device simultaneously. When a full
width at half max (FWHM) of 5 ns voltage pulse was applied, there is
a clear resistance change in Fig. 9(b), proving that the switching speed
8, 021306-11
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1.0 a.u.
a f
Ni Carbon-deposition
2H_[110]

Color Bar
Ti
Active region
Non-active region SiO2
TMD
Au
Ti
100 nm 2Hd
SiO2 0.0

b
80 nm

2Hd 2H 1 nm
2H

g
10 nm 002
000 200
c 2H d 2Hd e 2Hd [110]2H

002 Td_[010]
110

5Å 1 nm 2H_[120]
5Å

FIG. 7. (a) HAADF-STEM image showing a cross section of the Mo0.96W0.04Te2 device.26 (Mo0.96W0.04Te2 shows the same RRAM behavior as MoTe2. (b) Higher magnification
HAADF image from the region defined by a red box in (a) and showing coexistence of a distorted structure (2Hd) with 2H taken along the [110]2H zone-axis. (c, d)
Corresponding nano-beam diffraction pattern taken from the intrinsic 2H and the distorted 2Hd areas. (e) Nano-beam diffraction pattern taken from the distorted 2Hd area,
which is still indexed as the 2H structure. (f) Atomic-resolution HAADF image taken along [110]2H zone-axis from the filament area, showing coexistence of 2Hd and 2H in a
MoTe2 device. (g) Atomic-resolution HAADF image taken along [120]2H zone-axis—an orthorhombic Td phase is clearly observed together with the 2H phase. Inset in the right
top corner is the corresponding FFT image. Adapted with permission from F. Zhang, H. Zhang, S. Krylyuk, C. A. Milligan, Y. Zhu, D. Y. Zemlyanov, L. A. Bendersky, B. P.
Burton, A. V. Davydov, and J. Appenzeller, Nat. Mater. 18, 55–61 (2019).26 Copyright 2019 Springer Nature, and with permission from IEDM 22.7.1–22.7.4 (2018).

in MoTe2-based RRAM is less than 5 ns. Aside from/In addition to the switch between the LRS and HRS by applying 80-ls set/reset pulses.
switching speed, the other key metrics to evaluate this novel RRAM During these hundreds of cycles, the LRS and HRS currents remain
device are endurance and retention. Figure 9(c) illustrates the pulse stable, and the on/off resistance ratio does not get degraded.
switching behavior in MoTe2-based RRAM devices. The device can Figure 9(d) shows a retention measurement at room temperature. The

(a) (b) (c)

3.5
10–3 Set Voltage 3.0 MoTe2
LRS
Set voltage (V)

Current (µA)

2.5 thickness
Current (A)

10–5 Forming (nm)

Reset Voltage 2.0 102
Voltage
5–9
10–7 1.5 10–17
1.0 slope = 1 18–27
10–9 Pristine
Forming 24 nm MoTe2 0.5
Successive cycles
10–11 0.0 101
–3 –2 –1 0 1 2 3 0 10 20 30 102 103 104 105 106
Voltage (V) MoTe2 thickness (nm) Area (nm²)

FIG. 8. (a) I-V curves of a 24-nm MoTe2 device with an active area of 330 nm  500 nm. Forty cycles are shown in the gray line curves. Current compliance is set to 400 lA.
Reprinted with permission from F. Zhang, S. Krylyuk, H. Zhang, C. A. Milligan, D. Y. Zemlyanov, L. A. Bendersky, A. V. Davydov, and J. Appenzeller, 2018 IEDM, 22.7.1–22.7.4.102
(b) Set voltage values scale with the flake thickness of MoTe2. (c) LRS current at 0.3 V as a function of the contact area. For all devices, the current compliance was set to 400 lA
except for the device with a 27-nm MoTe2 flake (red data point with the dashed border) where it was set to 250 lA.

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-12

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(a) (b) 1.5 4 (c)

Read@0.3V
Input 250 LRS
Voltage
Pulse monitor 3
1.0 200

Current (mA)

Current (mA)
Voltage (V)
Osc.
50 Ω Top FWHM = 5 ns 2
150
Bottom
0.5 HRS
t < 5 ns 1 100
Measurement 50 Ω
Setup
0.0 50
–5 0 5 10 15 0 200 400 600
Time (ns) Cycles

Read@0.5V Depression
(d) (e) 5000 –1.2V
–1.2V

10–3 10–3

Resistance (Ω)
Current (mA)

LRS 4000
IRead (A)

10–5

10–7
Synapse
HRS 3000
–2 –1 0 1 2 1.1V
Voltage (V) 1.1V
10–4
2000
Potentitation
100 101 102 103 104 105 0 200 400 600 800
Time (s) Pulse Number

FIG. 9. (a) Experimental setup for the pulse measurement. (b) I/V vs time plot showing switching of the device within a 5-ns voltage pulse. (c) Current vs cycle in the LRS and
HRS at a read voltage of 0.3 V. Current compliance is set to 400 lA. (d) Retention of the HRS and LRS for a 15-nm thick MoTe2 RRAM device. Current compliance is set to
1.2 mA. (e) Synaptic device from an MoTe2 RRAM. Reprinted with permission from F. Zhang, S. Krylyuk, H. Zhang, C. A. Milligan, D. Y. Zemlyanov, L. A. Bendersky, A. V.
Davydov, and J. Appenzeller, 2018 IEDM, 22.7.1–22.7.4.102

device states are stable and do not show any obvious current drift dur-
ing the 28-h measurement period. All performance studies indicate
stable and reproducible RRAM behavior. Figure 9(e) shows the grad-
ual resistance changes by a series of positive pulses (1.1 V, 80 ls) fol-
lowed by a series of negative voltage pulses (–1.2 V, 80 ls), which is
similar to the potentiation and depression of biological synapses.
Based on previous studies,105,106 nonvolatile memories exhibiting large
and granular conductance changes, low pulse-to-pulse and device-to-
device variability, fast switching speeds, and low operation voltage are
needed for potentially accelerating deep neural network (DNN) training.
Fast switching speeds (< 5 ns) and low required operation voltages are
demonstrated advantages of MoTe2-based RRAM devices. Moreover,
MoTe2 RRAM offers intrinsically better reliability and control, far beyond
conventional devices that are based on the migration of ions during the
filament formation. It is expected that the demonstrated 2D-based
RRAM can greatly reduce device-to-device and pulse-to-pulse variations.
Last, it should be noted that indeed very low currents in the low resistive
state of MoTe2-based RRAM devices as desirable for DNNs have been
demonstrated in a stacked structure involving Al2O3.26
While all the above results are encouraging, the resistance
ratio between the LRS and HRS is rather small. Moreover, most of
the MoTe2 RRAM devices show almost an Ohmic behavior in both
the LRS and HRS. For those reasons, one expects that a large num-
ber of sneak paths would exist in a crossbar structure, which would
significantly degrade the reading signal and writing conditions. In
order for a large memory array to function properly, it is crucial to
add selector devices in series to suppress the sneak-path from other
unselected devices, as illustrated in Fig. 10. Ideal selectors can be
viewed as 2-terminal voltage-controlled switches in series with the
active RRAM device (1S1R array). Below a voltage threshold, the
selector is in its off-state, providing a very large resistance to
suppress sneak currents through unselected cells. While at high
voltages, the selector is in its on-state, posing a very low resistance
and allowing currents to pass through the selected cells. The gen-
eral requirements107 for a selector include but are not limited to
having a high nonlinearity (> 106), allowing for a high on-current
(> 10 MA/cm2), being BEOL compatible, operating bidirectional,
enabling a minimal footprint 4F2 (F: feature size), and showing
long endurance and fast switching speeds.
In our previous work, we have experimentally demonstrated
novel two-terminal vertical transition metal dichalcogenide (TMD)
based memory selectors from various TMD materials spanning a wide
range of thicknesses, as presented in Fig. 11. All I-V characteristics are
rather symmetric and bidirectional, and it is apparent that MoS2 devi-
ces naturally exhibit high current densities (106A/cm2 at 3 V for a
13-nm-thick flake), while WSe2 stacks allow achieving large nonlinear-
ities (1000 for a 9-nm-thick flake), which is defined as the ratio of
the current at a certain voltage to the current at half of the voltage.
Schottky barriers between electrodes and TMD and flake thickness are
the key factors to achieve decent nonlinearity and on-current. This
indicates that a proper choice of TMD-based selector devices should
be able to fulfill both of the above requirements simultaneously.
To identify the most desirable selector material (or combination
of materials), the current through a vertical TMD device is modeled

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-13

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1S1R array
1R array V RRAM
V
V/2
V/2 Selected RRAM

Selector

Current
V/2 0 V/2 0 Sneak current

FIG. 10. Sneak current path in the cross-point 1R array and 1S1R array.

adopting the method described in Ref. 108 with a band structure as transport mechanisms can be described, namely, thermionic emission,
depicted in Fig. 12. For this scenario, the current can be expressed as FN-tunneling, and direct tunneling. For E > Un, electrons travel from
ðð one contact electrode to the other by means of thermionic emission
2q
I¼ D2D T1D ðf1  f2 ÞdEx dEk ; (1) over the barrier between the Au electrode and the TMD. For lower
h
energies, Un – qV < E < Un, Fowler-Nordheim (FN) tunneling occurs
m0
where D2D ¼ p h2
is the 2D density of state of the yz-plane inside the through a triangular barrier. Finally, direct tunneling takes place for
metal contact, Ek and Ex are the corresponding energies in the yz- E < Un – qV. The thermionic emission, FN tunneling current and
plane and x-direction, and f1 and f2 are the Fermi distribution func- direct tunneling components for WSe2 devices based on our simula-
tions inside the two metal contacts. Both integrals in Eq. (1) occur tions, are shown in Fig. 12. Note that this model has been vetted previ-
from minus infinity to infinity, neglecting pcontributions from holes ously to quantitatively describe the vertical transport in MoS2 and
Ð ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
ffi
2m ðEc ðxÞEÞ WSe2 flakes.108 The total current is dominated by direct tunneling in
2 dx
through the valence band. T1D ¼ e h
 is the one- the thinner flake, making its nonlinearity quite low. When the flake is
dimensional transmission probability in the x-direction by employing thicker, FN-tunneling occurs at higher applied bias, yielding higher
WKB approximation. The Fermi level on the left-hand side is set to nonlinearity. When the flake becomes too thick, the on-current
zero since the Au electrode is grounded in this case. Un denotes the decreases due to the lack of tunneling currents, and hence, the nonlin-
barrier for electron injection. The constant electric field in the selector earity decreases.
implies that we assumed that no charge accumulation is occurring in Figure 13 is a summary benchmarking chart of simulated and
the TMD. Based on different energy windows, three distinct current experimental results for vertical 2DLM-based devices with different
flake thicknesses, including an imaginary material with a large
Schottky barrier and a simulated heterojunction of a 1S1R stack for
comparison. The respective numerical parameters used for the simula-
106 tions are presented in Table I. The solid lines are simulations with dif-
ferent flake thicknesses as denoted by the numbers in the plot,
whereas dots are extracted from experimental results with the flake
103 thicknesses confirmed by AFM and color-coded into four categories.
Current (A/cm2)

Note the non-monotonic trend of the non-linearity as a function of

on-current. As discussed in the context of Fig. 12, thinner flakes give
NL1/2 = IV/IV/2 13 nm MoS2
rise to higher current levels, but only those flakes that are dominated
100
24.3 nm MoS2 by FN tunneling show the highest linearity. Considering the non-ideal
interfaces and, in particular, the impact of oxidation, the simulation
9 nm WSe2 captures the overarching trends for WSe2 and MoS2 devices in an
10–3 10 nm WSe2
acceptable fashion. It is worth noticing that while the trends in Fig. 13
13 nm WSe2
are describing the situation in a 2DLM selector in general, the actual
V V/2
7 nm MoTe2 value of the nonlinearity depends on the choice of voltages and thus
10–6 the desired memory application. Also note the trend between MoS2,
–3 –2 –1 0 1 2 3 WSe2, and the “imaginary material” with an even larger Schottky bar-
V(V) rier for charge injection. The higher the injection barrier, the higher
the achievable nonlinearity, however, at the price of a lower on-
FIG. 11. I-V characteristics for various TMD materials with different flake thick- current for a given 2DLM thickness.
nesses. Reprinted with permission from F. Zhang, Y. Zhu, and J. Appenzeller, 2017 With this calibration in place, next we will turn our attention to a
DRC, 1–2.104
hypothetical 1S1R stack using WSe2 as the selector and MoTe2 as the

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-14

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band diagram
thermionic
Ec 1010
Φn FN-tunneling
EF
0 direct tunneling 106

I (A/cm²)
–qV 2 nm
26 nm WSe2
102 50 nm

10–2
z
0 1 2 3
V (V)
x
y

FIG. 12. Simulated I-V characteristics for WSe2 with different flake thicknesses with the simulation parameters of m ¼ 0.14m0, Un ¼ 0.567 eV. Only electron injection is
considered.

Simulation
1010
4 WSe2-Sim
MoS2-Sim
Imageary material
MoTe2 RRAM
108 with large bandgap
2D selector
Nonlinearity I3v / I1.5v

Experimental FIG. 13. Benchmark of nonlinearity vs on-

TMD thickness (nm) current for WSe2, MoS2, an imaginary
106 20
<10 material, and a heterojunction of LRS
10-15 MoTe2 and a 6-eV bandgap material with
16-20 a 3-eV Schottky barrier. Lines were simu-
>20 lated from the model whereas dots were
104
26 extracted from experimental results with
different flake thicknesses denoted on the
1
WSe2 plot.
2
102 60 MoS2
32 2

2
100 0 2 4 6 8
10 10 10 10 10 1010
On-current I3v (A/cm2)

TABLE I. Numerical parameters used for the simulation.

Schottky barrier (eV)

Materials Au Ti Effective mass Out-of-plane dielectric constant

LRS MoTe2 UMoTe2-Au ¼ 0.07 0.3m0 10.4

WSe2 UWSe2-Au ¼ 0.567 UWSe2-Ti ¼ 0.65 0.14m0 7.8
MoS2 UMoS2-Au ¼ 0.4 0.18m0 6.9
Imagery material 1 0.14m0
Large bandgap 2D selector 3 0.3m0

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-15

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band diagram I-V curves

108
0.56
0.07
Au

(A/cm²)
MoTe2

II (A/cm²)
104 FIG. 14. Comparison of I-V characteristics
WSe2
0.65 for 10-nm WSe2 and a heterostructure of
18-nm LRS MoTe2 in conjunction with 10-
Ti nm WSe2 with the simulation parameters
100 of WSe2 (m ¼ 0.14m0, Un ¼ 0.567 eV)
10 nm WSe2
18 nm MoTe2+10 nm WSe2 and MoTe2 (m ¼ 0.3m0, Un ¼ 0.07 eV).
0.567 0 1 2 3
V (V)
Au WSe2
0.65

Ti

active RRAM device. Figure 14 compares a 10-nm WSe2 device with a
heterostructure consisting of a series arrangement of 10-nm WSe2 and
18-nm MoTe2. Interestingly, the calculated I-V characteristics show a
higher on-current that is achieved at lower bias values for the
much thicker stacked heterostructure. This behavior is a result of
the fact that (i) a small Schottky barrier of 70 meV exists between
the gold metal electrode and MoTe2 in its LRS,102 (ii) a fix
conduction band discontinuity of 0.56 eV (UWSe2-Au – UMoTe2-Au)
was assumed,108 (iii) there exists a Schottky barrier of
UWSe2-Ti ¼ 0.65 eV,109 (iv) no charge accumulation in any of the
layers occurs, and (v) the simulated out-of-plane dielectric
constant values for WSe2 and MoTe2 are 7.8 and 10.4, respec-
tively.110 In this case, the applied positive voltage between the gold
and the titanium electrode effectively lowers the barrier posed by
the WSe2 film due to the electric field in the MoTe2. This, in turn,
gives rise to a faster increase in the on-current and larger
nonlinearity.
The above finding is also critical for the observed simulation
trend in a hypothetical heterostructure from a 6-eV bandgap material
with a 3-eV Schottky barrier and a thickness ranging from 1 to 4 nm
in series with an active layer of 18-nm MoTe2 as shown in green in
Fig. 13. This heterostructure promises high nonlinearities without too

(a) Nonlinearity (I1v/I0.5v) (b) On-current (I1.0v)

log (A/cm2)
3600
50 21 50 109 215 430 50 –0.2 0.5 1.2 1.8 2.4
7.5
46 27 68 132 276 585 46 0 0.8 1.5 2.1 2.7

37 102 236 497 932 3000 0.3 1.1 1.8 2.5 3

42 42
54 138 332 690 1345 0.6 1.4 2.2 2.8 3.4 6.0
38 38
34 76 199 578 1131 2018 2400 34 0.9 1.8 2.6 3.3 3.8
WSe2 (nm)

WSe2 (nm)

30 116 380 847 1982 3004 30 1.3 2.3 3.1 3.8 4.3 4.5
26 233 751 1614 2484 2790 1800 26 1.9 2.9 3.7 4.2 4.6

22 493 1280 2566 2793 3109 22 2.5 3.5 4.3 4.7 5

3.0
18 980 2476 3096 3031 2006 1200 18 3.3 4.3 4.8 5.2 5.3

14 2068 2929 2790 1634 760 14 4.2 5 5.4 5.6 5.5

10 2543 2205 1150 455 188 10 5.3 5.8 5.9 5.8 5.7 1.5
600
6 1197 524 195 81 43 6 6.4 6.4 6.3 6.1 5.9

2 61 39 24 16 12 2 7.2 6.8 6.6 6.3 6.1

0 0.0
8 12 16 20 24 8 12 16 20 24
MoTe2 (nm) MoTe2 (nm)

FIG. 15. Simulated dependence of (a) nonlinearity and (b) on-current on various thicknesses of MoTe2 and WSe2.

Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013 8, 021306-16

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10–6
10–8
I (A)
10–10
Cycle
10–12
Intrinsic
Forming
More cycles
10–14
–10 –5 0 5 10 15
V (V)
FIG. 16. Multiple I-V measurements on a vertical MoTe2/WSe2 RRAM device with
thicknesses of 24 nm for MoTe2 and 40 nm for WSe2. The active area is
200 nm  200 nm.
much sacrifice to the on-state performance. As before, the stacking
and fixed conduction band discontinuity are responsible for this rather
unexpected behavior, and structures of this type deserve more explora-
tion for optimizing the 1S1R stacks.
Coming back to the WSe2/MoTe2 heterostructure, next we
have evaluated the impact of thickness of the two 2DLMs in terms
of nonlinearity and on-current. The nonlinearity and on-current
for a heterostructure of MoTe2 (source) and WSe2 (drain) were
numerically calculated for MoTe2 thicknesses ranging from 8 to
24 nm and WSe2 thicknesses from 2 to 50 nm, respectively. One
distinct band (dark red) occurs in the parameter space, corre-
sponding to a high nonlinearity [Fig. 15(a)]. As the total thickness
increases, the on-current expectedly drops, as shown in Fig. 15(b).
Considering a proper balance between nonlinearity and on-
current, we have identified an MoTe2 film in the range of
10–20 nm and a WSe2 thickness in the range of 6–16 nm to form
the most desirable 1S1R stack, at which the nonlinearity is
expected to be more than three orders of magnitude, while an on-
current at a relatively high value of about 1 MA/cm2 is maintained.
To experimentally confirm our findings from simulations, we
have fabricated various MoTe2/WSe2 RRAM devices following the
methods described in Sec. III. Figure 16 shows multiple I-V
measurements on a representative MoTe2(24 nm)/WSe2(40 nm)
1S1R device, indicating a stable and reproducible memristive
switching of the device. The device exhibits an on-current of about
103 A/cm2 at high bias values. Our experimental nonlinearity value
and on-current levels are both smaller than expected from the sim-
ulation [see marked black star data points in Figs. 15(a) and
15(b)]. This discrepancy might stem from the fact that the top
WSe2 layer has been oxidized after exposure to air. Another con-
tributing factor could be that interface charges exist between the
two distinct TMDs. Moreover, the extraction of 103 A/cm2 at high
voltages is not really appropriate, since our simulations are per-
formed at 1 V. Since the compliance value has a strong impact on
the LRS in particular at a low voltage of 1 V and will also
Appl. Phys. Rev. 8, 021306 (2021); doi: 10.1063/5.0038013
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potentially impact the size of the filament, a detailed quantitative
comparison of the current levels is not meaningful at this time.
However, even considering these discrepancies, our experimental
findings are first-time evidence for the opportunities that properly
designed 1S1R heterostructures can offer for future memory
applications.
Notice that the current compliance for the heterostructure of the
MoTe2/WSe2 1S1R RRAM stack is rather low (< 1 lA) compared to
the one for the bare MoTe2 devices (400 lA), providing again evidence
that the phase transition occurring in MoTe2 is induced by the electri-
cal field instead of being current induced. Moreover, the selector is
responsible for most of the voltage drop based on our simulations.
Hence, only a small portion of the write voltage is sufficient to trigger
the phase transition of MoTe2 RRAM, consistent with our findings
from Fig. 8(b).
IV. DISCUSSION AND OUTLOOK
In conclusion, many promising 2DLM-based memory applica-
tions have been recently uncovered that deserve further exploration.
In particular, we have highlighted in this article novel MoTe2-based
RRAM devices. The operation of those devices relies on the electric
field–induced uniform structural transition between two crystal
phases, different from the random filament formation in conventional
devices. These devices offer intrinsically better reliability and control,
far beyond those based on the migration of ions in conventional
RRAM structures. In comparison to PCM-based devices that rely on a
phase transition between an amorphous and a crystalline structure,
MoTe2-based RRAM devices discussed above transition between two
crystalline states, which allows for faster switching. Moreover, the utili-
zation of atomically thin 2D materials allows for aggressive scaling and
an extended application space in high-performance flexible
electronics.
In this work, we have also proposed 1S1R heterostructure devices
that hold the promise for achieving the desired performance specs in
terms of nonlinearity and on-current, while further experiments are
certainly needed to confirm our simulation findings. We conclude that
the heterogeneous 1S1R architecture discussed in the last section rep-
resents a crucial step toward the realization of future dense memory
applications.
AUTHORS’ CONTRIBUTIONS
All authors have contributed equally to this manuscript. All
authors have reviewed this final manuscript.
DATA AVAILABILITY
The data that support the findings of this study are available
from the corresponding author upon reasonable request.
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