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Kosaraju 2001
Kosaraju 2001
[Extended Abstract]
S. Rao Kosaraju
Department of Computer Science
The Johns Hopkins University
Baltimore, MD 21218
Given a series-parallel graph, we consider the problem of is drawn by locating each i +1 above i and by placing
G j G j
drawing its layout in the plane (and the planar dual of the the merged and on the left and on the right, respectively.
s t
layout) such that the euler count of the layout is minimized. Note that each of the series and the parallel constructs per-
This problem is of considerable importance to the design of mits ! di erent permutations in the drawing.
m
CMOS circuits. Even though it was believed that there can- For any SP graph layout, the dual is de ned as for planar
not exist a polynomial time algorithm for this problem, we graphs. A typical SP graph layout and its dual are shown
have been able to design a polynomial time algorithm. The in Figure ??. Note that the labels of the edges get mapped
degree of the polynomial is unrealistically large. The main as labels of edges in the dual layout in an obvious way.
interest is in the existence of a polynomial time algorithm Let and d be an SP graph layout and its dual, respec-
H H
for the problem. We are not aware of any natural problem tively. Let = 1 2 n be any string of labels such that
x e e e
for which a natural dynamic programming based algorithm each edge label of appears once in the string. (Denote
H
has such a large degree. such an as a label string of .) Break (greedily from left
x H x
A series-parallel graph (SP graph) is an undirected graph x (with respect to and ). Let the length j 1 2 i j
H H x x x
dual.) The break positions are 3 and 5. The euler count for
by merging all 0i into a single vertex and all 0i into a
s s s t s
a layout is the minimum euler count, minimized over all the
single vertex are SP graphs. The series and the paral-
t
possible label strings. For example, for the above layout,
lel constructs are designated as Series( 1 2 m ) and G ;G ; ;G
the euler count is 2, and it is realized by the label string
Parallel( 1 2 m ), respectively. We are interested in
G ;G ; ;G
(= ). Denote a label string that realizes
SP graphs in which the edges are labeled with distinct sym- abedcf gh abedc f gh
count.
There is a linear time algorithm for the rst problem [?].
Even for the general class of planar graph layouts, there is
a linear time algorithm [?] for problem 1.
As explained by Nyland & Reif in [?], the second problem
Permission to make digital or hard copies of all or part of this work for
personal or classroom use is granted without fee provided that copies are
not made or distributed for profit or commercial advantage and that copies for SP graphs is of great practical signi cance. Each edge
bear this notice and the full citation on the first page. To copy otherwise, to corresponds to a transistor, and the sequence of edges that
republish, to post on servers or to redistribute to lists, requires prior specific form euler paths in the graph and its dual can be laid out
permission and/or a fee.
compactly such that adjacent transistors share a common
STOC’01, July 6-8, 2001, Hersonissos, Crete, Greece.
Copyright 2001 ACM 1-58113-349-9/01/0007 ... 5.00. $ di usion layer. Consequently, transforming the graph into
237
g h
f
c d
e e h
s a b t s f
d b t
g
c
DUAL
Figure 1: A Planar Layout and Its Dual
an equivalent form that reduces the euler count is highly X and have labels 1 2 k , in order as shown in
Y u ;u ; ;u
desirable. This problem is considerably harder. There is no the gure. In the dual layout, these edges will be in series,
known polynomial time algorithm for it. It was implicitly and hence 2 k 1 cannot have a continuous transition
u ; ;u
assumed in [?] that there cannot exist a polynomial time al- with edges of . Hence there can be at most 2 continuous
X
gorithm: \In attempting to nd the smallest set of paths that transitions in this case.
traverse both graphs, one must avoid the manipulation of a A general case is shown in Figure ??. In this case, is X
parallel-series graph into equivalent graphs. ... Since there in parallel with one layout above ( 3 ) and another below
Y
are n! di erent orderings of n elements, the exploration of ( 4 ), and this parallel layout is in series with one layout to
Y
all parallel-series graphs to achieve an optimal layout could the left ( 1 ) and another to the right ( 2 ). By a simple
Y Y
be extremely time-consuming and is therefore unacceptable." extension of the argument of the above simple case, we can
Maziasz and Hayes [?, ?] develop an exponential time al- show that each i , 1 4, can provide at most 2 continu-
Y i
gorithm for this problem. In [?], a linear time algorithm ous transitions. Hence there can exist at most 8 continuous
is developed for testing whether the euler count of a given transitions for . The case in which is in series with two
X X
SP graph is 1. In this paper, we develop a polynomial time layouts, one on each side, and this series layout is in parallel
algorithm for problem 2; i.e. for the problem of computing with two layouts, one on each side, can he handled in an
the euler count for a given SP graph. In this preliminary analogous way. 2
version, to simplify the presentation, we will not present the This lemma can be strengthened into the following form.
fastest algorithm. Even our fastest algorithm has a speed The proof involves consideration of several cases of compos-
that is a very large degree polynomial. ing series and parallel constructs.
Extensive literature exists for drawing xed graphs [?]. Lemma 2: For any SP graph layout and d, any
But none of them deals with drawing a graph when the graph d
sub-layout and , and any label string of , there
H H
must be proper SP graph layouts and they should not leave Proof: Let be any worst-case label string for . Break
x H
any \holes" in the plane.) An example of a sub-layout and x into substrings, = 1 2 3 such that either the odd
x x x x
its dual for the layout of Figure ?? is shown in Figure ??. indexed substrings 1 3 or the even-indexed substrings
x ;x ;
Let = 1 2 n be any label string of . In , position 2 4 are in the sub-layout . Without loss of general-
x ;x ; X
x e e e H
transition if there is no break between i and i+1 for contributes 2 to the euler count of and can be moved to any
x
sub-layout of Figure ??, if the label string is then the euler count. Consequently we can move the even indexed
the transition positions are 1,5 and 7 (
abdef ghc
) in which substrings around such that the resulting string will have at
a bdef gh c
transition positions 1 and 5 are continuous. most 4 substrings from without increasing the euler count
X
238
f
c d
e e
b f
d b
DUAL
Figure 2: A Sub-layout and Its Dual
u1
Y u2 X
u
k
Y3
Y1 X Y2
Y4
239
We can assume that = 1 2 k , where 9 and
x x x the degree of the polynomial is too large for the algorithm
x k
in which either the even- or the odd-indexed substrings are to be of any practical value.
from . If we x the sub-layout and vary the rest of
X X
Clearly, we have been very lax in our time estimates.
the layout , worst-case label string for and its number
H
Tightening H
the analysis, we can get a much smaller value
of substrings in also vary. However, independent of the
X
for the degree; but it will still be a large value. In the com-
rest of , the contribution of , for any particular , can be
H X
plete version we will discuss many such improvements.
H
end of every substring. Thus there are at most p=1 22p , 3. REFERENCES
which is less than 29 , di erent possible ways can con- [1] B.S. Carlson, C.Y.R. Chen and D.S. Meliksetian: Dual
X
of those. For each of the 29 possible conditions, di erent IEEE Foundations of Computer Science, 1999, 319-329.
layouts of X contribute di erent euler counts to . For
G
[3] G. Di Battista, P. Eades, R. Tamassia and I.G. Tollis:
H
each condition we specify the minimum possible euler count Graph Drawing; Algorithms for the Visualization of
(minimized over the layouts for X ). It is also easy to prove
G
Graphs, Prentice Hall, New Jersey, 1999.
that there exists a constant such that for Xcand for any [4] T.-Y. Ho, T.-Y Sung, L.-H. Hsu, C.-H. Tsai and J.-Y.
G
two of the 29 di erent conditions, the corresponding euler Hwang: The Recognition of Double Euler Trails in
counts cannot di er by more than . Hence we can express c
Series-Parallel Networks, J. Algorithms, 1998, 216-257.
each euler count as a xed value, and an o9 set value taken [5] R.L. Maziasz and J.P. Hayes: Layout Optimization of
from f0 1 g. Thus we specify X by 2 di erent values
; ; c G
Static CMOS Functional Cells, Proc. 24th ACM/IEEE
where each value is taken from f0 1 2 g, and a xed ; ;
Design Automation Conf., 1987, 544-551.
; ;c
. For simplicity, let us assume that = 0 and ignore [6] R.L. Maziasz and J.P. Hayes: Layout Optimization of
it. (It is quite easy to incorporate the exact value into9 the Static CMOS Functional Cells, IEEE Trans. on
discussion.) Thus X can be characterized by one of 2 (=
G
Computer-Aided Design, 1990, 708-719.
c
d ) di erent possible values. Let us denote the corresponding [7] R. Muller and T. Lengauer: Linear Algorithms for Two
value of X as its characteristic value.
G
CMOS Layout Problems, In Proc. of Aegean Workshop
Now we develop a polynomial time algorithm for comput- on Computing VLSI Algorithms and Architectures,
ing the euler count of a given SP graph of size n. Springer Lecture Notes in Computer Science 227, 1985,
G
Algorithm 121-132.
Without loss of generality, we can assume that is spec- [8] L.S. Nyland and J.H. Reif: Algebraic Technique for
i ed with alternating series and parallel constructs. (If, for Generating Optimal CMOS Circuitry in Linear Time,
G
and let us assume that we have already computed the char- Computers , 1981, 305-312.
acteristic values for the i 's. Now for each value we count
U j
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