RESUME

Kirankumar.R.Udnur
#4, 4th c cross, Vinayaknagar,

Kamakshipalya, Bangalore-560079

Email: kiran.udnur100@gmail.com, kirankumar.udnur@gmail.com

Linkden Profile: https://in.linkedin.com/in/kiran-udnur-5540376a

Ph: 9632939024, 9902674354(mother)

Objectives:
To work in an organization that will utilize and enhance my skill sets in the field of, CMOS IC Circuit
design, Physical Design, Layout and ASIC / FPGA design / Verification and applications .

Experience:
 Presently Perusing ‘Physical Design Engineering’ course as an Intern at Kanada Technologies,
Blore from 6 months.
 Design of 9-track Tap less Library of Inverter, Boolean Expression, D-Latch and Memory Layout of
SRAM in 45nm Technology and good exposure in fixing DRC and LVS.
 Working on Complete Physical Design of Open MSP-430 and completed Synthesis using RC- Compiler,
Floor Planning, Power Planning, Placement and Clock tree Synthesis (CTS) using Cadence-Encounter
till date.
 Comprehensive knowledge of Physical design implementation, Physical design strategies, and Static
Timing analysis.
 Presently working as a Design Verification Engineer at ‘Schneider Electric R & D’, Bangalore from June
2015.

Technical Skills:
 Complete Power Planning of Open MSP430 ie calculation of width of Power Rails and all metal rails.
 Linux Operating System, Tcl and Perl Programming & VI and Text Editor
 Basics of Advanced Scripting Languages : PERL, TCL
 Good understanding of ASIC Design & Physical Design Flow.

 Basic understanding of Electrostatic Discharge (ESD), latch up and signal integrity issues.

 Ability to interpret different types of DRC and LVS, ERC errors like shorts, opens, bad devices, property
error, connectivity error, device mismatch.

 Good working knowledge of EDA tools such as Cadence Virtuoso, Encounter, Assura, Spectre)

 Worked on 180nm, 90nm and 45nm technology.

 Good knowledge of Digital Design Concepts.

 Good understanding of fundamentals of Transistors and circuit theory.

Area of Interests
  Backend VLSI Design like Physical Design Engineering and Front end Verification.
 Analog Design, Custom Layout Designing and verification, CMOS IC designing.
Projects:
 Planar Robot (Automation) – Engineering project
 Complete Physical Design of Open MSP430 (Ongoing).

Tools Known:
Operating System : Windows, Linux, Unix.
EDA Tools : Cadence (Assura, Spectra, Virtuoso, Encounter)
Software : Basics of Shell and Perl scripting, C, Embedded Software Coding, Verilog, VHDL coding.
Achievements:
 1st Prize in Kannada debate & 2nd Prize in English debate in MEI Polytechnic in Diploma.
 Participated in ‘Electronic Circuit Design Challenge’ at IISc Bangalore.
 Participated in ‘Kludge’ a 24 hour Electronic Design Challenge to develop a project prototype.

Educational qualification:
 Graduated from ‘PESIT-BSC’ as Bachelor of Engineering in Electronics and Communication Engineering -
2015 batch with aggregate of 55%.
 Diploma in Electronics and Communication Engineering, 2008-2011 in MEI Polytechnic with 73.19%.
 SSLC: 2004-2005 in Pavan Eng Medium School, Dharwad with 86.08%.
 PUC: 2005-2007 in Karnataka Science College, Dharwad with 1 st class.

Personal Skills:
 Willingness to accept Challenges.
 Hard Working and Quick Learner with Positive attitude.
 Good communication skills
Personal Profile:
Name: Kirankumar Udnur
DOB: 12-03-1990
Father Name: Ravindra Udnur
Sex: Male
Marital Status: Unmarried
Languages Known : English, Kannada, and Hindi

Declaration:
My Resume might have made you familiar about me. I hereby declare that all information above
furnished is true to the best of my knowledge.

Place: Bangalore (Kirankumar Udnur)