SHAIK AYESHA PARVEEN

Mobile no :7013616157
Email: Shaikayesha4909@gmail.com

CAREER OBJECTIVE:
Aiming to use acquitted academic knowledge and proven communication,
multitasking, and persuasion skills to successfully fill the given role at your company.
Frequently praised as adaptable by my peers, I can be relied upon to help your company
achieve its goals.

TECHNICAL SKILLS:
 MANUAL TESTING:
1. Well versed with SDLC.
2. Good understanding of STLC and DLC.
3. Good knowledge in functional, integration and system testing.
4. Good knowledge on smoke testing, accessibility testing and
acceptance testing.
5. Good knowledge on compatibility testing, regression testing,
re-testing and exploratory testing.
6. Knowledge on White Box and BlackBox testing Techniques.

 SQL:
1. Practiced on Oracle Data base.
2. Good knowledge on DDL, DML, DCL.
3. Good knowledge on RDBMS concepts.
4. Ability to write queries using SUBSTRING and INSTRING.
5. Exposure to CONSTRAINTS like primary key, foregin key, unique.

 JAVA:
1. Good Knowledge on Looping statements.
2. Good knowledge on Conditional Statements.
3. Good knowledge on OOPS Concepts.

CERTIFICATION:

Certified from Software Testing Training Center “ Qspider ”.

 Manual Testing
 Selenium Tool
 Agile Methodology
 Core Java
 SQL
 EDUCATION:

2017-21 Bachelor of Technology , JNTU-Kakinada

Eswar College of Engineering , (E.C.E) - 68%.

2016-17 Intermediate , Board of Intermediate AP

Vagdevi Juniour College , (M.P.C) – 55.5%.

2014-15 S.S.C , Board of Secondary School Education AP

Z P High School – 70%.

PROJECT DETAILS:
 Project Title : Design RCA Using Domino Logic
 Language of implementation : VLSI
 Description : This paper new design a Proposed Logic
design targeting at full-custom highspeed applications. The constant delay characteristic of
this logic style regardless of the logic expression makes it suitable in implementing
complicated logic expression such as addition. This feature enables performance advantage
over static and dynamic, CD logic styles in a single cycle, multi- stage circuit block. Several
design considerations including appropriate timing window width adjustment to reduce
power consumption and maintain sufficient noise margin to ensurero bust operations are
discussed and analyzed. Using 50nm general purpose CMOS technology, the proposed logic
style high performance compare to Static, dynamic & CD logic respectively. This circuits
design DSCH Tool, Micro wind Tool.

STRENGHTS:

 Ability to do any kind of work under any situation.

 Works better under high pressure.

 Excellent Communication & Presentation Skills.

 Ability to work as an individual as well as in a group.

 Easy adaptation of any new environment.

 Leadership.

 Having a good communication ability.

PERSONAL DETAILS:
NAME : SK. AYESHA PARVEEN
FATHER’S NAME : SK. SUBHANI
Date Of Birth : 22-04-2000
Gender : Female
Marital Status : Un-Married
Religion : Muslim
Languages : Telugu, Hindi, English
Address : D-no : 3-101, Behind Majid, Satuluru, Guntur dist, AP

DECLARATION:
I Here by declare that the above written particulars are true to the best of my life.

(SK. AYESHA PARVEEN)

Place:
Date: