DATASHEET

VC Verification IP, Test Suites & Subsystems

Automotive, Cloud/Networking, Display, Memory, Mobility, Storage, & More

Protocol, Bus & Interface VIP Overview

• Native SystemVerilog/UVM
• UVM Source code test suite (Optional)
• Verification plan and coverage
• Built-in protocol checks
• Verdi® protocol aware debug
Synopsys VC Verification IP (VIP), source code Test Suite and Verification
Subsystem Solutions provide access to 90+ industry protocols, interfaces,
memories, and subsystems required to verify IP, subsystem and SoC designs.
Automotive Cloud/Networking Display

• Extensive error injection Memory Mobility Storage

DDR/ HBM/ SD/eMMC SPI/QSPI UFS/ ONFI/ PCIe/ SATA/

Memory VIP
Ethernet AVB TSN
LPDDR HMC UHS OSPI UniPro Toggle NAND NVMe SAS

• Runtime JEDEC/vendor part selection AMBA CHI, ACE, AXI, AHB

• Overriding timing parameters AMBA APB

HDMI/
DBI/DPI CSI/DSI DigRF RFFE Soundwire SLIMbus
DP/eDP
• Backdoor memory access
I2C/I3C UART

• Bypass/fast initialization
Subsystems CCIX USB Type-C
• Configurable refresh rates
• Delay modeling
Figure 1: Complete VIP, Test Suite and Subsystem Solutions

Verification Subsystems
• Multiple protocols
enabled and expandable
• Automated Testbench
generation/configuration
• IP-XACT signal connectivity
• Subsystem level and performance UVM
source code Test Suites (optional)
• Port and system level coverage and
verification plans
• System Monitor and
subsystem level checks
• Verdi Performance Analyzer with
pre-defined performance metrics
VIP, Test Suites and Subsystems provide a comprehensive set of protocol,
methodology, verification, and productivity features, enabling users to achieve
accelerated verification closure of IP, subsystems and SoC designs. Synopsys
VIP solutions are based on next generation architecture and implemented in
native System Verilog/UVM, which eliminates the need for language translation
wrappers that affect performance and ease-of-use. The VIP solutions can be
integrated, configured, and customized with minimal effort, enabling designers
to easily expand usage and meet organizations requirements.
Verification Subsystem solutions provide automated test bench generation and
configuration to jump start verification across multiple protocols. Verification
is further accelerated with built-in verification plans and functional coverage
at both protocol and subsystem levels. VIP is natively integrated with Verdi®
Protocol Analyzer, which provides a protocol-centric debug environment with
a graphical view of VIP operations, transactions, and memory content for easy
and fast debug, as well as quick resolution of performance bottlenecks.

synopsys.com/VIP
 Verticals Performance and Debug
Automotive
Cloud/
Networking
Display
Memory
(DRAM/Flash)
Mobility

Storage

Test Suite and Coverage Domain Knowledge

Verification
Plan

Simulator

Test
Suite
DUT VIP

Performance Protocol Coverage

Analysis Analyzer Collection

Figure 2: Protocol verification challenges

Growing Verification Challenges

Next generation SoCs are targeting functionality convergence, higher performance, and lower power with faster time to market and
lower cost. As a result, engineers face the challenge of verifying highly complex and large gate-count SoC with multiple discrete
functions — each incorporating many industry-standard interface and memory protocols connecting SoC to the outside world.
Verification engineers are looking for ease-of-integration, re-usable and efficient standard architectures, faster development of test
benches, effective debug and coverage solutions, higher performance and reduced regression time. (See Figure 1).

Resolve the Verification Challenges

Synopsys VC VIP streamlines the entire verification process, significantly reducing the time and effort required to achieve project
schedules and coverage goals. VC VIP offers the advantage of being developed, supported, and kept current by experts in the
protocols and verification methodologies, a multi-year effort by dedicated teams for each protocol. In addition, VIP are proven
across the industry in a wide range of designs and applications. VIP is optimized for ease-of-use, performance, debug, and rapid
coverage closure.

System Verilog/UVM VIP with Native Integration and Optimization

VC Verification IP is based on next generation architecture and implemented in native System Verilog/UVM, which eliminates the
need for language translation wrappers that affect performance and ease-of-use. The architecture has been engineered from the
ground up for enhanced VIP performance, configurability, portability, debug, planning, coverage management, and extensibility. It
provides full visibility into classes, callbacks, and messages and enables true SystemVerilog based constraints. All layers of the
protocol stack are visible, providing complete controllability of protocol and memory verification. Verification engineers can work at
the highest layer required to meet their verification plans, yet still have the ability to inject errors at the lowest layers.

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 Verification
Plan

Simulator

Test
Suite
DUT VIP

Performance Protocol Coverage

Analysis Analyzer Collection

Figure 3: System Verilog/UVM Verification Solution — VIP and Test Suite natively integrated and optimized with VCS, and Verdi

Verification Subsystem Solutions

VC Subsystem Verification Solution is a highly configurable verification environment with automated UVM test bench generation
capabilities and comprehensive set of subsystem level and performance verification features, enabling users to achieve accelerated
verification closure and thorough performance analysis of subsystem designs.

Subsystem level monitor, extensive checks and complete coverage is delivered as part of the solution. Synopsys Verdi Performance
Analyzer is natively integrated and pre-defined performance metrics are provided. Subsystem level Test Suite for functional and
performance verification is also available.

UVM Source Code Test Suites to Jump Start Verification

Writing tests to verify protocols is time consuming, challenging and requires deep protocol and methodology expertise. Synopsys
UVM source code test suites help eliminate the task of writing tests for today’s complex protocols. The test suite is a complete
self-contained, configurable environment and provided as System Verilog UVM source code to simplify integration, enable user
customization, and maximize reuse across projects. Test suites are updated, expanded and new tests are added with each release
of new protocol specifications. A built-in verification plan is provided with spec linking and coverage. In addition to functional tests,
performance tests are also provided for verification subsystems.

Best-in-Class Quality
The Synopsys VC VIP has a proven record of 20+ years of successful VIP deployments and a large number of competitive
displacements. Our leadership position continues with aggressive expansion of VIP for new protocols, with many first-in-industry and
customer proven. Synopsys collaborates extensively with industry leaders on next generation SoC designs and develops new VIP
rapidly to support the latest specifications and emerging new protocols. Synopsys VC VIP is used across the industry, including top
10 SoC semiconductor suppliers.

Collaboration with Standards Committees

Synopsys collaborates as an ecosystem partner with standard organizations on new protocol standards and JEDEC to develop
next generation VIP as new standards emerge. Proactive collaboration allows mutual customers to align with early versions of
specifications and develop and verify industry’s first solutions.

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Automation and Acceleration
Getting to first-test quickly is a major challenge in any verification project. VC VIP has a number of built-in features to streamline the
initial stage of verification, including:

• Support for native System Verilog and UVM for easy and quick integration, with no wrappers required
• Subsystems with automated test bench generation/configuration and IP-XACT signal connectivity
• Methodology-specific code examples
• Built-in protocol-based verification plans with spec linking and functional coverage for the different configurations of the VIP
• UVM source code test suite and sequence libraries to jump-start test development
• HTML-based, task-focused documents take engineers systematically through the key steps of integrating and using the
VIP in testbenches

Best-in-class Performance
Testbench performance has become increasingly important for SoC verification. With multiple interfaces to verify, VIPs can frequently
become a significant factor in testbenches affecting overall performance. VC VIP delivers improved performance, reducing regression
time by multi-fold and thereby meeting the challenging project schedules and time-to-market requirements. VIP leverages following
architectural advantages to achieve increased performance:

• 100% native System Verilog and UVM

• Native performance optimization with VCS
• There are no wrappers, legacy languages, PLI calls, or foreign simulators to degrade performance
• Native integration with Verdi Protocol Analyzer and Performance Analyzer

Verification Plan and Functional Coverage

Synopsys VC VIP comes with a verification plan. The verification plan shows how each functional coverage group is directly mapped
to the protocol specification. This verification plan is hierarchical with sub-plans based on the DUT feature set. The functional
coverage support in VIP includes coverage for protocol, toggle, transaction, and configuration along with cross coverage. In addition,
sequential coverage is provided to cover complex sequences that are hard to derive directly from the protocol specification.
Coverage is “configuration aware” which means bins are ignored if not applicable to the VIP configuration. Users can extend the
built-in coverage to add their own bins based on built-in VIP sampling events and groups or create their own groups with any
sampling event or data.

• Built-in verification plan with spec linking and coverage

• Automated coverage report generation
• Automatic back annotation of coverage data into test plan, identifying progress against coverage goals
• Rapid identification of remaining coverage points, enabling faster coverage closure
• Out-of-the-box sequence libraries and source code test suites to jump-start verification and accelerate coverage closure

Protocol Aware Debug

The growth in complexity and increasing number of protocols used on an SoC is creating a rapidly increasing verification challenge
and debug bottleneck for verification engineers. Verification engineers must quickly become protocol experts and try to correlate
information across different sources of information to find the root cause of problems. Protocol Aware Debug is natively integrated
with VIP and Verification Subsystems providing protocol-centric debug which enables user to quickly understand protocol activity,
identify bottlenecks and quickly find and debug unexpected behavior.

• Graphical, hierarchical view of transaction, packets, and handshaking with immediate access to context specific
detailed information
• Error, warning and messaging annotation within the protocol view to quickly find root cause
• Lock-step linking to simulator-trace views (waveforms) enabling easy debug at any level of abstraction

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Performance Analyzer
Synopsys Performance Analyzer is natively integrated with VIP and Verification Subsystems providing constraint specification and
checking, constraint violation tracing and debug, and performance report generation. Pre-defined and user-defined performance
metrics can be used for transaction, cross transaction, and cross component analysis to measure latency and bandwidth.

Figure 4: Protocol Aware Debug and Performance Analyzer (Native Integration)

Information on New Features

This data sheet provides a summary of supported protocol features and may not reflect all the features added in recent releases.
Please contact your local Synopsys sales office for complete information about new features and enhancements.

For more information, visit: www.synopsys.com/VIP

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available at synopsys.com/copyright.html . All other names mentioned herein are trademarks or registered trademarks of their respective owners.
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