CS/ECE/EEE/INSTR F241: Microprocessor and Interfacing

Mid-Semester Solutions

Section I
1) The code starts by displaying 4 spaces in the first row and then prints one star character. Next, it
keeps reducing the number of spaces by 1 for each subsequent row and also increases the
number of star characters to be printed by 2 for each subsequent row. The total number of rows
to be displayed is indicated by the variable “COLUMNS.” The code works in a manner similar to
those explained in lectures/tutorials.
2) There are several solutions possible. Any solution that exits the loop in a manner such that SI
contains the value 0003H during its exit will be awarded marks. Note that the instruction “LOOP
UP” decrements the CX register first, checks if this new value of CX is zero or not and then
decides the branching operation accordingly.
3) Intel family of microprocessors store the data in memory according to little Endian format byte-
by-byte. Program execution and the corresponding memory content updation will occur as
discussed in tutorial problems. Note that uninitialized memory locations also contain numerical
values. Hence, even those assuming “garbage” for these memory locations, need to take specific
numerical values and enter the resulting value in the space provided for marks to be awarded.
4) There are only 3 ways to update the IP register: CALL, branch instructions and RET. To obtain a
general code snippet, which will work irrespective of where in the complete code it is inserted,
use of branch instruction will require the CALL instruction to obtain the current IP address. As
per the questions, CALL cannot be used. Hence, the only way to load 1234H into the IP register
is to use the RET instruction. However, partial marks have been awarded to those who have
used JMP instruction with appropriate displacement. Note that ORG is not an instruction but an
assembler directive. Hence, no marks will be provided for using ORG.
5) The “JNZ” instruction checks for the status of the Zero flag, which is last updated by the POPF
instruction in the given code. Since FFFFH gets loaded into the FLAG register after the execution
of the POPF instruction, the loop is exited without any branching. Hence, the instructions within
the loop are executed just once consuming 31 clock cycles. Since the JNZ instruction never
branches, as discussed in lectures, the instruction queue will not be flushed. Note that via the BX
register and the stack, all bits in the FLAG register are being set to logic 1. Hence, the position of
the zero flag within FLAG register is immaterial for solving this question.
6) The total number of clock cycles for the execution of the given code snippet is 17𝑁 + 10𝑁 −
8. To obtain a delay of 2 seconds, the quadratic equation that needs to be solved is 17𝑁 +
10𝑁 − 24000008 = 0, which yields a value of 𝑁 = 1187.883. Hence, 𝑁 should be equal to
1188 (decimal) or 04A4H.
 Section II
1) Code Snippet Y is invalid since the instruction MOV DS, 1000H is invalid. Segment registers
cannot be used in the Immediate mode of addressing. Note that MOV AL, AL is a valid
instruction. Its machine code can easily be obtained using Intel’s datasheet, as described in the
lectures. The validity of an instruction depends purely on whether the microprocessor allows
such an operation, and not on any particular assembler that one chooses to use.
2) The CALL instruction is executed 3 times, once in the main program and twice in the procedure,
before the execution control is handed back to the main program.
3) Before the execution of the RET M instruction, the procedure is recursively called 3 times.
Hence, the stack contains 6 bytes of return addresses. RET M pops the latest return address and
adds a value of M to the SP. Hence, to obtain the address of .EXIT, M should be 4, which
correspond to the remaining bytes of the return addresses on stack. This will ensure that the
execution of the next RET instruction will hand the execution contol over to .EXIT instruction in
the main program, as discussed in lectures/tutorials.
4) In the instruction JMP NEAR DOWN, the label DOWN would be converted to a 16-bit signed
displacement. Hence, it can take any value between 0000H and FFFFH.
5) Irrespective of whether X is even or odd, the loop will be executed twice and take odd number
of clock cycles for each execution, making the overall clock cycles utilized even.
6) 6 bits of address lines A14-A19 are used for selecting the memory chips. However, when all these
bits are logic 1, the output will be logic 1 and the chips will not be selected. Hence, the foldback
occurs for the remaining 63 combinations, when the chips are selected.
7) Adding 58 (decimal) with 99 (decimal) yields a value 157 (decimal). Hence, the given code
snippet would store 57H in AL and set the carry flag.
8) The loop executes twice. During the first execution of the loop, both memory access instructions
correspond to reading of mis-aligned data. Hence, both instructions put together require 4
memory access cycles. In the second execution of the loop, MOV AX, [BX+5] corresponds to a
reading of mis-aligned data while MOV DX, [SI] corresponds to a reading of aligned data. Hence,
put together, they require 3 memory access cycles. Therefore, the total number of memory
access cycles is 7.