CONFIDENTIAL Ref. No.

: EE2205/ES/2021/05

INDIAN INSTITUTE OF ENGINEERING SCIENCE AND TECHNOLOGY, SHIBPUR

B. Tech (EE) 4th Semester Final Examination, May-2021
Digital Electronics (EE2205)
Full Marks: 50 Time: 1 hour 30 minutes
(i) Use a single answer-script for all questions
(ii) Answer Qs. No. 1 and ANY THREE full questions from the rest
(iii) All parts of a question MUST be answered in the same place
(iv) Relevant diagram(s) MUST be drawn for each problem

1. (a) Prove the following Boolean Law: A + BC = (A + B).(A + C)

(b) Deduce the Boolean Expression for a full-subtractor. Clearly mention the significance of all
symbols used. Hence, draw the Boolean Logic Circuit for a full subtractor.
(c) An ABCD-to-seven-segment decoder is a combinational circuit that converts a decimal digit in
BCD to an appropriate code for the selection of segment in an indicator used to display the
decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the
corresponding segments in the display, as shown in Fig. Q1(a). The numeric display chosen to
represent the decimal digit is shown in Fig. Q1(b). Using a truth table and Karnaugh maps, design
the BCD-to-seven-segment decoder, using minimum number of gates. The six invalid
combinations should result in a blank display.

(a) (b)
Fig. Q1

[5 + 5 + 10 = 20]

2. (a) Draw the internal schematic diagram, for a D-type flip-flop, with positive-edge-triggered
architecture, and clearly explain its working. Mention one advantage of this edge-triggered
architecture over master-slave architecture.
(b) Explain the phenomenon of 'contact-bouncing'. How can flip-flops be used as a 'contact de-
bouncer'?
[(2 + 3 + 2) + 3 = 10]

3. (a) With a neat sketch, clearly explain the working of a "Switch-Tail Ring Counter", using four flip-
flops. How many states does this counter have?
(b) Without using any external switch and the minimum number of flip-flops, design a binary counter,
which counts continuously in the following sequence: 0 → 1 → 2 → 4 → 8 → 0 → 1 → .... and so
on (where the decimal nos. given are equivalent decimal value of the binary output). Clearly
explain your steps.
[5 + 5 = 10]

4. (a) "DTL architecture supports wired-AND logic" – Explain the statement with suitable diagrams.

Page 1 of 2
Name of the Paper: Digital Electronics (EE-2205)
Name of the Examination: Final Examination, May-2021
Name of the Paper Setter: S. Dalapati

Signature of the Moderator (with date)

CONFIDENTIAL Ref. No.: EE2205/ES/2021/05

(b) In the circuit, shown in Fig. Q4, the input voltage is

vi, which swings between two levels – 0 and 12 V.
The output voltage is vo. It is assumed that Q will
enter hard saturation if β (= IC/IB) < 10. Determine
mathematically: (i) whether Q is in active zone or
saturation zone when vi = 12 V, and (ii) the levels of
vo for the two input levels of vi. Assume that all
voltages in the figure are with respect to ground
(unless mentioned otherwise) and VBE,sat = 0.8 V and
VCE,sat = 0.2 V.
[5 + 5 = 10] Fig. Q4
5. (a) With a neat sketch, describe the working of a DAC with binary weighted resistors. Mention one
advantage and one disadvantage of this DAC.
(b) A five-bit Digital to Analogue Converter produces an output of 0.4 V for a digital input of 00010.
(i) Find the output for an input of 10001. (ii) What is the resolution of this DAC? (iii) What is the
maximum output, obtainable from this DAC?
[(3 + 2) + (2 + 2 + 1) = 10]
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Page 2 of 2
Name of the Paper: Digital Electronics (EE-2205)
Name of the Examination: Final Examination, May-2021
Name of the Paper Setter: S. Dalapati

Signature of the Moderator (with date)