2020-EE-525 VLSI Lab-4

EE 476L
Introduction to VLSI Systems Laboratory
Lab 4
DRC, LVS, RCX and Post-layout simulation of an inverter

Objectives:
 To perform Design rules check (DRC), Layout vs. Schematic check (LVS) of inverter
 layout
 To extract parasitic resistance and capacitance from layout of designed inverter
 To perform transient simulation of extracted view
 To create layout views for body ties of NMOS and PMOS for further use

DRC Analysis of Inverter:

In this lab we use the previous designed inverter and now we want to find the DRC analysis
of this inverter. For this purpose, we have to first resolve the error of the circuit which we
have got from the DRC analysis so we will update out inverter which we wave designed and
after removing the errors now I can easily find the DRC analysis of the circuit.

Circuit Diagram:
2020-EE-525 VLSI Lab-4

After performing DRC analysis my error layer window and visual layer window showing
following errors:

Here is the error layer window

Now I have to remove my errors those are showing in the error layer window. For this I made
some changes in the layout and after doing successful changes I, finally, again run DRC
analysis and then got error layer window showing the following
2020-EE-525 VLSI Lab-4

Now here is the successful run DRC report after removing all the errors from the layout and
at the end my design rule check analysis run and showing report.
2020-EE-525 VLSI Lab-4

Conclusion:
In conclusion, the DRC (Design Rule Check) analysis of the inverter design conducted in
Cadence demonstrates that the layout adheres to the specified design rules and constraints.
This validation ensures the manufacturability and reliability of the inverter circuit, meeting
the necessary criteria for successful fabrication.