308
2, MARCH 2005
Input Impedance Analysis of Single-Phase
PFC Converters
Jian Sun, Member, IEEE
Abstract—The input impedance of single-phase boost power
factor corrected (PFC) ac–dc converters is modeled and ana-
lyzed in this paper. A large-signal model is presented for the
input impedance which overcomes the limitations of traditional
piece-wise linearized models. The model is valid at frequencies
ranging from the crossover frequency of the output voltage loop to
half the switching frequency of the converter. Experimental results
from a boost single-phase PFC converter are provided to validate
the model. Input characteristics of typical boost PFC converters,
such as input impedance dipping, leading phase of the input cur-
rent, and responses to distorted input voltages are studied by using
the model. A simple compensation technique to reduce the dipping
in the input impedance, thereby improving converter performance
and minimizing the potential for undesirable interactions with the
input filter or the ac source, is also presented.
Index Terms—Converter-source interaction, input impedance,
power factor correction (PFC), PFC converter modeling, PFC con-
verter stability.
I. INTRODUCTION
D YNAMIC interactions of converters with their input fil-
ters are a common problem in systems involving switching
power converters. For dc–dc converters, a systematic approach
based on averaging and linearization has been developed for an-
alyzing such interactions and their effects on stability of the
interconnected systems. Specifically, the input impedance of
a dc–dc converter at a given steady-state operating point can
be determined through linearization of the nonlinear averaged
model of the converter. The Nyquist criterion can then be ap-
plied to the ratio of the filter output impedance to the converter
input impedance to determine the stability of the interconnected
converter-filter system [1]. Linearization is a credible approach
in this case because most dc–dc converters can be assumed to
operate with constant input and output such that a steady-state
operating point can always be identified.
Filter-converter interactions also exist in systems employing
power factor corrected (PFC) ac–dc converters as the front end.
For example, [2] demonstrated that the interaction between a
PFC converter and the source impedance of a generator may
lead to voltage instability. There is, however, a lack of system-
atic method for analyzing and characterizing such interactions.
Manuscript received March 31, 2003; revised February 25, 2004. This paper
was presented in part at the IEEE Applied Power Electronics Conference,
Orlando, FL, February 2003. This work was supported in part by Rockwell
Collins, Inc., by RPI, and by the Center for Power Electronics Systems
(CPES - an Engineering Research Center of the National Science Foundation).
Recommended by Associate Editor F. Blaabjerg.
The author is with the Department of Electrical, Computer, and Systems En-
gineering, Rensselaer Polytechnic Institute, Troy, NY 12180-3590 USA (e-mail:
jsun@rpi.edu).
Digital Object Identifier 10.1109/TPEL.2004.843011
0885-8993/$20.00 © 2005 IEEE
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO.
A fundamental difficulty there is the sine wave input voltage to
a single-phase PFC converter, which prevents, in theory, the ap-
plication of conventional small-signal linearization techniques.
At frequencies below the line fundamental frequency, the time-
varying switching-cycle averaged model of the converter power
stage can be averaged again over a line cycle to eliminate its de-
pendency on time (due to time-varying input) [3]. The resulting
nonlinear, time-invariant, line-cycle averaged model can then
be linearized and combined with controller models to predict
converter small-signal behavior in the low-frequency region [4].
The resulting low-frequency model can be further simplified by
assuming ideal current loop, i.e., by assuming that the inductor
current follows perfectly the reference current [5]. However,
since most converter-filter interactions occur at high frequen-
cies, typically around the crossover of the current loop and/or
the corner frequency of the input EMI filter, the low-frequency
model is not sufficient for system stability analysis.
The traditional approach to high-frequency modeling of
single-phase PFC converters relies on the assumption of
quasi-stationary operation, i.e., the converter operates in a quasi
steady state at different points along the sine wave input. Under
this assumption, the nonlinear, switching-cycle averaged model
of the converter power stage can be linearized at different points
along the sine wave input. This results in a set of linear models
each being “valid” for a particular point along the sine wave.
From a practical point of view, it might be plausible to use such
piece-wise linear models to assist in the design and stability
analysis of PFC converter control loops. For example, if the
piece-wise linear models indicate instability of the current loop
under a particular input voltage (lower than the peak of the ac
line), one could arguably infer that the converter would also
have stability problems when operating from the ac line.1 This
has indeed been the approach used in previous works on control
design for single-phase PFC converters [6].
The piece-wise linear models have also been used to deter-
mine the input impedance of single-phase PFC converters above
the line fundamental frequency, see, e.g., [7]. Despite some de-
gree of correlation between model predictions and experimental
measurements reported in the literature, this approach has a fun-
damental deficiency in its theory, i.e., there is no clear physical
interpretation for the piece-wise linear input impedance calcu-
lated under different dc input voltages and its correlation to the
actual input impedance of a PFC converter under sine wave in-
puts. For example, the input impedance of a PFC converter at
three times the line frequency is, by definition, equal to the ratio
of a (small) third harmonic voltage superimposed onto the ac
line and the resulting third harmonic input current. A third har-
1However, stability of the converter with a sinusoidal input is not guaranteed
even if the piece-wise models predict stability at all points along the sinusoidal
input waveform.
 SUN: INPUT IMPEDANCE ANALYSIS 309

monic input voltage introduces a perturbation to the converter

operation along the entire fundamental cycle, not just at a par-
ticular point of the ac line. Hence the input impedance predicted
by the piece-wise linear model for a particular dc input voltage
is theoretically meaningless when the converter operates with a
sine wave input [5].
A new approach to high-frequency input impedance mod-
eling of boost single-phase PFC converters is presented in this
paper. The high-frequency input impedance model, which is
valid above half the line frequency, is derived by assuming that
the output voltage is constant, i.e., by ignoring the dynamics
of the voltage loop above half the line frequency, under which
the switching-frequency averaged model of the boost power
stage becomes linear. The resulting impedance model is valid
for large-signal operation and can be used to predict not only
the input impedance of the converter but also its input charac-
teristics under different lines.
The high-frequency impedance model described in this paper Fig. 1. Simplified boost single-phase PFC converter circuit for the calculation
was originally obtained as a by-product of a research effort of input impedance in the high-frequency region. The converter uses
aiming at understanding the input current zero-crossing distor- leading-edge modulation and standard average current control.
tion in single-phase PFC converters [9]. During the preparation
of the current paper, the author came across [10] and [11] which feedforward loop [8] can be ignored in the high-frequency re-
reported similar high-frequency models. In comparing the two gion. As such, the reference current, , can be expressed as
approaches, it was found that the derivation in [10] and [11] as-
(1)
sumed small-signal operation of the converter, and the results
were actually for the input impedance of the boost stage, i.e., in the high-frequency region, where is a constant. In steady
excluding the front-end rectifier bridge. In contrast, this paper state and under ideal control, the input current (rms) and power
uses a large-signal approach to determine the input impedance at of the converter are related to the parameter by following
the ac side of the converter directly. Additionally, the models in equations:
[10] and [11] were verified indirectly by measurements of con-
verter current loop gain, while direct measurements of converter (2)
input impedance are provided in this paper for model validation.
Furthermore, the large-signal nature of the model reported here The pulse-width modulator (PWM) in Fig. 1 is assumed to
allows it to be used for studying converter responses to distorted use leading-edge modulation such that the switch off-time duty
input voltages, which would not be possible with a small-signal ratio, , is proportional to the output of the current
model. amplifier, . Under the assumption that the ramp signal of the
PWM has a peak-to-peak voltage equal to , the modulator
II. HIGH-FREQUENCY IMPEDANCE MODEL has a gain of , and the off-time duty ratio of the switch
can be written as
This section presents the development of the high-frequency
input impedance model for boost single-phase PFC converters (3)
with average current control. The basic converter circuit and
control is depicted in Fig. 1. It is assumed here that the inductor where is the on-time duty ratio of the switch. It is known that
current is sensed by using a resistor. Other current sensing leading-edge modulation can reduce the output voltage ripple
methods can also be used, and the model presented in the of the PFC converter when its load is a trailing-edge modulated
following is applicable in general. The reference current, , dc–dc converter [14].
for the inductor is generated by a multiplier with three inputs Derivation of the high-frequency impedance model follows
the modeling procedure outlined in [9]. First, with standard av-
erage current control, the current compensator output, , can
be written as
where (4)
1) is the output of the output voltage compensator;
is generated by a low-pass circuit and represents the where is the current compensator transfer function
2)
rms value of the line voltage for input feedforward control
[8]. (5)
The crossover frequency of the output voltage loop in single-
phase PFC converters is usually well below the line frequency
[8]. Hence, the output of the voltage compensator, , can be with
assumed constant when calculating the input impedance in the
high-frequency region. Similarly, effects of the input voltage

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 310 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005

Since the pulse-width modulator can be modeled by a constant

gain under average current control [12], the off-time duty ratio
of the switch can be expressed as

(6)

To model the boost power stage, we further assume that

1) all components in the circuit are ideal; Fig. 2. Block diagram representing high-frequency dynamics of boost single-
phase PFC converters.
2) the boost inductor operates in the continuous conduction
mode (CCM) over the entire line cycle;
3) the sensing resistor, , is small such that the voltage
across it can be ignored;
4) the output voltage, , is constant.
Based on these, an average model can be written for the boost
inductor current,

(7)
Fig. 3. Boost single-phase PFC converter with an ac and a dc filter capacitor.
Since , (7) can be rearranged to give
Now, the input impedance of the converter can be determined
(8) from (13) and (1) as

On the other hand, multiplying both sides of (6) by the sign

(14)
function, , yields

(9)
Based on (8) and (9), a block diagram representing the dynamics
of the input current of a boost single-phase PFC converter with
average current control is obtained as shown in Fig. 2. Note
that the input and output in this diagram are the actual input
voltage and current of the PFC converter, not the input voltage
and current of the boost stage. Accordingly, the variable I_ref(s)
in the block diagram as well as in (9) shall be understood as the
reference for the actual input current of the converter, not the
boost inductor current.
Based on the diagram shown in Fig. 2, a transfer function can
be derived for the input current in response to the input voltage,
, and the reference current,
Note that (14) gives directly the input impedance of the PFC
converter at the ac side. It is also a large-signal model since
small-signal operation is not assumed in the derivation.
A small filter capacitor is usually placed on the dc side of the
rectifier bridge, as shown in Fig. 3, to reduce high-frequency
noises in the rectified dc voltage. This capacitor should be as
small as possible in order not to cause significant phase shift at
the fundamental frequency, which would otherwise lead to high
zero-crossing distortion of the input current [9]. Yet the effect
of this capacitor on the input impedance, especially at high fre-
quencies, may not be negligible. When considering this capac-
itor as well as the commonly used ac-side filter capacitor, ,
which could be part of the input filter, the total input impedance
of the converter can be written as follows where is de-
fined by (14)

(10) (15)
By defining
A couple comments are in order here before proceeding to the
(11) validation of the developed model.
1) The boost inductor current becomes discontinuous near
and assuming that the effects of the high-frequency current com- the zero crossing of the input current, which is ignored in
pensator pole, , on the input impedance can be ignored, i.e.,2 the derivation of the model. Since the discontinuous cur-
rent interval is usually short compared to a line cycle, ig-
noring it will not introduce any significant error into the
(12) final model, as the experimental results presented in the
next section will prove. On the other hand, the model ac-
transfer function (10) can be simplified to curacy could be affected by this if the discontinuous cur-
rent interval is relatively long, such as in the case when the
(13) converter operates with very light load. Equation (7) can
be modified to model the inductor current in the discon-
2This is justified as ! is usually placed at half the switching frequency to tinuous conduction mode. But the equation would become
attenuate high-frequency noise in the control loop. nonlinear in that case [13], and the overall model over a

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 SUN: INPUT IMPEDANCE ANALYSIS
Fig. 4. Input impedance of the boost single-phase PFC converter at 53-W
input. Solid lines: predicted; dashed lines: measured with 50-Hz input.
line cycle becomes discontinuous due to the transition be-
tween continuous and discontinuous conduction modes,
which makes it impossible to derive a linear impedance
model.
2) The inclusion of capacitors and in (15) was in-
tended to provide a model which can be directly validated
through measurements of converters incorporating such
capacitors. When using the model for analysis of con-
verter interactions with the ac source, the ac-side capacitor
is usually considered part of the input filter, hence doesn’t
need to be included in the input impedance of the PFC
converter.
III. MODEL VALIDATION
The boost single-phase PFC converter described in [14]
was measured under various operating conditions to verify
the impedance model (14) and (15). Following are the major
parameters of this converter (refer to Fig. 1): boost inductor
mH, steady state output voltage V, sensing
resistor , PWM ramp signal peak-peak voltage
V, k , k , nF, and
pF, switching frequency kHz. With the
given compensator parameters, the zero, , is calculated to be
rad/s, while its dc gain is 170 068. Then,
based on the definition of (11), can be calculated as
Input impedance measurement of the converter was con-
ducted by injecting, through a power amplifier and an isolation
transformer, a sinusoidal perturbation to the input voltage and
measuring the resulting perturbation in the input current. Fig. 4
shows the input impedance response of the converter with
115 V (rms) input voltage and 53-W input power (corresponds
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311
Fig. 5. Input impedance of the boost single-phase PFC converter at 106-W
input. Solid lines: predicted; dashed lines: measured with 400-Hz input.
to ). The dashed lines represent the experi-
mental measurement results taken with 50-Hz input, while the
solid lines are predicted from (15). A 30-nF capacitor was used
on the dc side of the rectifier in this measurement, but no ac-side
filter capacitor was used. As can be seen, the measurement
results agree with model predictions over the entire frequency
range (10 Hz–100 kHz). The measurement error around 50 Hz
was due to the fact that the frequency of the injected signal in
this region is equal or close to the fundamental frequency of
the line, hence cannot be distinguished from the fundamental
component of the input [15].
It shall be pointed out that averaged models, such as the input
impedance model (14), are usually useful for predicting fre-
quency responses up to half the switching frequency. The input
impedance of the experimental boost converter above 50 kHz
is dominated by the effect of the 30 nF dc side filter capacitor
mentioned above. Hence, the agreement between the measured
and predicted responses above 50 kHz in Fig. 4 should be inter-
preted as a proof of the accuracy of the total input impedance
expression (15), not as an indication that (14) is valid beyond
half the switching frequency.
Fig. 5 shows the input impedance response of the converter
with 106-W input power (corresponds to ) and
a 30-nF dc side filter capacitor. The measurements were taken
with 400-Hz input, which is the standard ac bus frequency on
most of today’s commercial jet airplanes. Good agreement be-
tween experimental measurements and model predictions can
again be seen. The measurement error around 400 Hz is again
due to the inability of the network analyzer to distinguish the in-
jected signal from the fundamental component of the line. Fur-
thermore, Fig. 6 shows the total input impedance of the con-
verter with a 1.5- F filter capacitor placed at the ac side and
a 30-nF capacitor on the dc side of the rectifier bridge. The
measurements were taken with 400-Hz input, with 106-W input
power. The deviation of the measured phase response from the
 312 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005

Fig. 7. Input impedance responses of the boost PFC converter without filter
Fig. 6. Input impedance of the boost PFC converter with an ac side capacitor
= 1:5 mF, a dc side capacitor = 30 nF, and at 106-W input. Solid capacitors C and C . The two sets of plots correspond to g = 0:5 10 2
C C
lines: predicted responses; dashed lines: measured responses with 400-Hz input. 2
(dashed lines) and g = 0:25 10 (solid lines), respectively.

model prediction under 100 Hz was found to be caused by mea- frequency of ,3 from which the impedance starts to rise. For
surement errors. the measured boost PFC converter, this happens at about 10 kHz,
The close correlation between experimental measurements as can be seen from Fig. 7.
and model predictions in Figs. 4–6 proved the accuracy of the The amount of maximum dipping in the input impedance is
input impedance model presented here. also affected by the characteristics of the zeros of , espe-
cially its damping factor, , defined by
IV. INPUT IMPEDANCE ANALYSIS
The impedance responses in the previous section were
measured under small-signal operation conditions. The input
impedance model (14) is, however, valid for large-signal op- To maximize the current loop gain, the common design prac-
eration as well and can be used to study characteristics of the tice is to place the zero, , of the current compensator at the
converter with different inputs. The impedance plots in Figs. 4 crossover frequency, , of the current loop [8]. Since the duty
and 5 included the effects of , the capacitor on the dc side of ratio to inductor current transfer function of the boost converter
the rectifier bridge, see Fig. 3. Since this capacitor is not part of in the high frequency region is given by , see Fig. 1,
the basic function of the converter and can have very different unity gain of the current loop at implies that [9]
values in different designs, frequency-domain responses of
(without and ) are plotted using (14) in Fig. 7 for the (17)
example boost converter with and
(corresponds to 53 W and 106 W input power), respectively. With this, the damping factor of as defined above can be
The input voltage is 115 V (rms) in both cases. calculated as
A. Input Impedance Dipping
(18)
The most noticeable feature of the plots in Fig. 7 is the dipping
of the input impedance in the frequency region ranging from
Therefore, the two zeros of (which are also zeros of the
1 kHz to about 30 kHz. This is caused by the pole
input impedance) are under-damped, which causes an under-
shoot at the resonant frequency of and further adds to the
(16) dipping in the input impedance. Fig. 8 shows the magnitude
response of for the measured boost converter with
in . As can be seen, this pole is always smaller than the . As can be seen, there is about 3 dB undershoot at
zero, , of the current compensator and moves to lower fre- 8 kHz, which contributes to the dipping in the input impedance.
quency as decreases (so does the input power). The maximum 3It will be shown below that the second-order function p(s) is always under-
dipping happens at a frequency corresponding to the resonant damped in conventional designs so that it has two complex conjugate poles.

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 SUN: INPUT IMPEDANCE ANALYSIS
Fig. 8. Frequency response of function p(s) defined by (11). Shown here is
2
the magnitude response with g = 0:25 10 .
Stability of a PFC converter connected with an input EMI
filter requires that the impedance ratio, , meets the
Nyquist criterion, where is the output impedance of the
filter. To provide sufficient attenuation for the switching-fre-
quency ripple, the corner frequency of the EMI filter is usually
designed to be 1/10 of the switching frequency, which would be
10 kHz for the measured boost PFC converter. Since the output
impedance of the EMI filter peaks at the corner frequency, a dip-
ping in the input impedance of the PFC converter in the same
frequency region can greatly increase the potential for insta-
bility or deteriorated performance of the converter. The analyt-
ical input impedance model derived here can be used to guide
the converter and its EMI filter design to avoid undesirable in-
teractions, see Section IV-C.
B. Response to Different Lines
The large-signal nature of the input impedance model (14)
also allows it to be used for studying the response of the con-
verter to input voltages at different frequencies. As can be seen
from Fig. 7, when the line frequency is well below the pole of
, the actual input current will be in phase with the input
voltage, with a magnitude determined by the control parameter
according to (2). However, the decrease of the input impedance
with frequency (beyond 500 Hz) implies that the same value
of will result in higher input current when the line frequency
approaches the pole of . Additionally, the input current
starts to lead the input voltage as the line frequency goes up, and
the leading phase of the input current becomes significant (e.g.,
at 1 kHz) even before the change in magnitude becomes appre-
ciable. Furthermore, the plots in Fig. 7 suggest that these effects
are more significant under light load conditions, i.e., when is
small. The leading phase of the input current also causes har-
monic distortion in the input current around the zero crossing of
the input voltage, as explained in [9].
The input impedance model can be used to predict responses
of the converter to distorted lines. In particular, dipping of the
input impedance above 2 kHz implies that an percent har-
monic voltage in this frequency region will generate more than
percent harmonic current. For example, the magnitude plot in
Fig. 4 shows a maximum of 15 dB dipping (from 48 dB
at 200 Hz and below to 33 dB at 9 kHz). This implies that,
with reference .." by "Assume that the magnitude of the ref-
erence current is held constant. The 15-dB dipping in the input
impedance implies that an input voltage at 9 kHz will produce
an input current that is 5.6 times (15 dB = 5.6234) of the input
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313
current produced by an input voltage of the same magnitude but
at 200 Hz or lower frequency. In other words, assuming the line
fundamental frequency is under 200 Hz, 1% harmonic voltage
(relative to the fundamental) at 9 kHz would generate as much
as 5.6% harmonic current at the same frequency. This can be a
major concern for PFC converters that have to meet harmonic
current limits under distorted lines, such as the recently issued
DO-160D for airborne equipment.4
C. Performance Improvement
The two causes discussed in Section IV-A for the dipping in
the input impedance, namely, the low-frequency pole and the
under-damped zeros of , also point to possible ways for
reducing the dipping.
First, (14) indicates that it is possible to redesign the refer-
ence current generation circuit to make purely resistive
over the entire frequency range (i.e., up to half the switching
frequency in which the average model is valid). This can be
achieved by adding a phase shift circuit to the input pin
of the multiplier shown in Fig. 1. Assuming the transfer func-
tion of such a phase shift circuit is , the reference current
can be expressed as . Based on (13), a
transfer function that will result in complete cancellation
of the pole and zeros of was found to be
(19)
As can be seen, this transfer function is dependent of the
control parameter . Therefore, its realization would require an
adaptive filter and is best implemented using digital circuits,
which is beyond the scope of this paper. A simplified version
of it, as
(20)
can be used instead for analog implementation. Fig. 9 com-
pares the input impedance responses of the boost PFC con-
verter [14] before and after a phase shift circuit described by
(20) is added. The plots correspond to an input power of 53 W
, and the measurement was taken with 400 Hz
input. As can be seen, the model predicts that inclusion of the
phase shift circuit would reduce the maximum input impedance
dipping by as much as 5 dB, while actual measurement shows
a 3-dB reduction due to imperfect experimental setup. For the
interconnected converter-filter system, this would translate into
improved system stability and/or more efficient EMI filter de-
sign as less damping would be required.
The phase shift circuit described by (20) was used in [9] as
a means to compensate for the leading phase of the input cur-
rent so as to reduce the associated input current zero-crossing
distortion. Practical implementation of the circuit and its other
benefits were also discussed there. It was also noted in [10] that
adding a phase shift, such as the one described by (20), to the
reference current can improve the stability of the current loop in
the interconnected EMI filter-PFC converter system, which is an
4DO-160D requires that, for every 1% of individual voltage harmonic, the
equipment shall not demand harmonic current greater than 1.25% above the
limit for the corresponding harmonic current with undistorted input.
 314
Fig. 9. Reduction of input impedance dipping by phase shifting the reference
current. (a) Input impedance response predicted by the model with phase
shift, (b) measured input impedance with phase shift, and (c) predicted input
impedance response when the phase shift is not present.
indirect proof of the effect of reference current phase shift in re-
ducing the dipping of converter input impedance. Furthermore,
the analysis in the previous subsection indicates that reducing
the dipping in the input impedance would also lower the input
harmonic current distortion when the converter is supplied from
distorted lines.
V. CONCLUSION
A large-signal model has been presented for single-phase
boost PFC converters to predict their input impedance re-
sponses. The model is valid above the crossover frequency
of the output voltage control loop. Direct measurement of
the input impedance from a prototype converter proved the
accuracy of the model. The input impedance model was also
used to study general input characteristics of boost single-phase
PFC converters. A particular issue we investigated was the
dipping of the input impedance in the high-frequency region
and its effects on converter operation, such as stability of con-
verter-filter interconnected systems and input current distortion
under distorted lines. Based on the analyses, a simple phase
compensation method was proposed and its effectiveness in
reducing input impedance dipping was demonstrated.
The focus of this paper has been on derivation, validation,
and analysis of the input impedance model. Applications of the
model in the analysis of high-frequency interactions between
single-phase converters and the source or input filters will be
presented in a future work. To study converter-source interac-
tions below the voltage loop crossover frequency, we are exam-
ining the existing low-frequency input impedance model [2], [5]
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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 20, NO. 2, MARCH 2005
and found that it is not suitable for system analysis. Further de-
tails will be reported in a separate work.
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[9] J. Sun, “On the zero-crossing distortion in single-phase PFC converters,”
IEEE Trans. Power Electron., vol. 19, no. 3, pp. 685–692, May 2004.
[10] G. Spiazzi, L. Rossetto, and J. A. Pomilio, “Analysis of EMI filter in-
duced instabilities in boost power factor preregulators,” in Proc. PESC
’98 Conf., 1998, pp. 1048–1053.
[11] G. Spiazzi and J. A. Pomilio, “Interaction between EMI filter and power
factor preregulators with average current control: analysis and design
considerations,” in Proc. PESC ’99 Conf., 1999, pp. 382–388.
[12] J. Sun and R. M. Bass, “Modeling and practical design issues for av-
erage current control,” in Proc. IEEE Applied Power Electronics Conf.
(APEC’99), 1999, pp. 980–986.
[13] J. Sun et al., “Averaged modeling of PWM converters operating in dis-
continuos conduction mode,” IEEE Trans. Power Electron., vol. 6, no.
4, pp. 482–4922, Jul. 2001.
[14] User’s Guide, UCC3817 BiCMOS Power Factor Preregulator Evalua-
tion Board, Texas Instruments, Jul. 2001.
[15] Environmental Conditions and Test Procedures for Airborne Equipment,
Tech. Rep. DO-160D, ch. 16, 2004.
Jian Sun (M’95) received the B.S. degree from the
Nanjing Institute of Aeronautics, Nanjing, China,
in 1984, the M.S. degree from Beijing University
of Aeronautics and Astronautics, Beijing, China,
in 1989, and the Ph.D. degree from the University
of Paderborn, Paderborn, Germany, in 1995, all in
electrical engineering.
He was a Post-Doctoral Fellow in the School
of Electrical and Computer Engineering, Georgia
Institute of Technology, Atlanta, from 1996 to
1997, where he taught undergraduate courses on
electromechanical energy conversion. He worked in the Advanced Technology
Center, Rockwell Collins, Inc., from 1997 to 2002, where he led several
projects on the development of various power conversion technologies for
aerospace applications. In August 2002, he joined the Department of Electrical,
Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy,
NY, as an Associate Professor. His research interests are in the general area of
power electronics and energy conversion, with particular emphasis on converter
topologies, modeling, control, and various applications including computers,
communications, aerospace, and energy systems.
Dr. Sun is a Member of the IEEE Power Electronics Society. He currently
serves as an Associate Editor for IEEE POWER ELECTRONICS LETTERS.