Input Impedance Analysis of Single-Phase
PFC Converters
Jian Sun
Department of Electrical, Computer, and Systems Engineering
Rensselaer Polytechnic Institute, Troy, NY 12180-3590, USA
Telephone: (518) 276-8297; Fax: (518) 276-6226; E-mail: jsun@rpi.edu
Abstract-Input impedance of single-phase boost power factor
corrected (PFC) ac-dc converters is modeled and analyzed in this
paper. A large-signal model is presented for the input impedance
which overcomes the limitations of traditional piece-wise
linearized models. The model is valid at frequencies ranging from
the crossover frequency of the output voltage loop to half the
switching frequency of the converter. Experimental results from a
boost single-phase PFC converter are provided to validate the
model. Input characteristics of typical boost PFC converter
designs, such as input impedance dipping, leading phase of the
input current, and responses to distorted lines are studied by using
the model. A simple compensation technique to reduce the dipping
in the input impedance thereby improving converter performance
and minimizing the potential for undesirable interactions with the
input EMI filter is also presented.
I. INTRODUCTION
Dynamic interactions of converters with their input filters
are a common problem in systems involving switching power
converters. For dc-dc converters, a systematic approach based
on averaging and linearization has been developed for
analyzing such interactions and their effects on interconnected
system stability. Specifically, the input impedance of a dc-dc
converter at a given steady-state operating point can be deter-
mined through linearization of the nonlinear averaged model of
the converter. The Nyquist criterion can then be applied to the
ratio of the filter output impedance to the converter input
impedance to determine the stability of the interconnected
converter-filter system [1]. Linearization is a credible approach
in this case because most dc-dc converters can be assumed to
operate with constant input and output such that a steady-state
operating point can always be identified.
Filter-converter interaction also exists in systems employing
power factor corrected (PFC) ac-dc converters as the front end.
For example, [2] demonstrated that the interaction between a
PFC converter and the source impedance of a generator may
lead to voltage instability. There is, however, a lack of
systematic method for analyzing and characterizing such inter-
actions. A fundamental difficulty here is the sine wave input
voltage to single-phase PFC converters, which prevents, in
theory, the application of conventional small-signal linear-
ization techniques. At frequencies below the line fundamental
frequency, the time-varying switching-cycle averaged model of
the converter power stage can be averaged again over a line
cycle to eliminate its dependency on time (due to time-varying
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input) [3]. The resulting nonlinear, time-invariant, line-cycle
averaged model can then be linearized and combined with
controller models to predict the input impedance in the low
frequency region [4]. The resulting low-frequency model can
be further simplified by assuming ideal current control, i.e., by
assuming that the inductor current follows perfectly the
reference current [5]. However, since most converter-filter
interactions occur at high frequencies, typically around the
crossover of the current loop and/or the corner frequency of the
input EMI filter, the low-frequency model is not sufficient for
system stability analysis.
The traditional approach to high-frequency modeling of
single-phase PFC converters relies on the assumption of quasi-
stationary operation, i.e., by assuming that the converter
operates in a quasi steady state at different points along the sine
wave input. Under this assumption, the nonlinear, switching-
cycle averaged model of the converter power stage can be
linearized at different points along the sine wave input. This
results in a set of linear models each being “valid” for a
particular point along the sine wave. From a practical point of
view, it might be plausible to use these piece-wise linear
models to assist in the design and stability analysis of PFC
converter control loops. For example, if the piece-wise linear
models indicate instability of the current loop under a particular
input voltage (lower than the peak of the ac line), one could
arguably infer that the converter would also have stability
problems when operating from the ac line†. This has indeed
been the approach used in previous works on control design for
single-phase PFC converters [6].
The piece-wise linear models have also been used to
determine the input impedance of single-phase PFC converters
above the line fundamental frequency, see, e.g., [7]. Despite
some degree of correlation between model predictions and
experimental measurements reported in the literature, this
approach has a fundamental deficiency in its theory, i.e., there
is no clear physical interpretation for the piece-wise linear input
impedance calculated under different dc input voltages and its
correlation to the actual input impedance of a PFC converter
under sine wave inputs. For example, the input impedance of a
PFC converter at three times the line frequency is, by
definition, equal to the ratio of a (small) third harmonic voltage
†. However, stability of the converter with a sinusoidal input is not guaranteed
even if the piece-wise models predict stability at all points along the sinusoi-
dal input waveform.
361
 superimposed onto the ac line and the resulting third harmonic assumed constant when calculating the input impedance at high
input current. A third harmonic input voltage introduces a frequencies. Similarly, the input voltage feedforward loop [8]
perturbation to the converter operation along the entire funda- can be ignored in the high-frequency region. As such, the
mental cycle, not just at a particular point of the ac line. Hence reference current, iref, can be expressed as
the input impedance predicted by the piece-wise linear model
for a particular dc input voltage is theoretically meaningless i ref = g ⋅ v in (1)
when the converter operates with a sine wave input.
in the high-frequency region, where g is a constant. In steady
A new approach to high-frequency (above half the line state and under ideal control, the input current (rms) and power
frequency) input impedance modeling of boost single-phase of the converter are related to the parameter g by follows:
PFC converters is presented in this paper. The high-frequency
model, which complements the existing low-frequency model gV in R l gV in 2R
l
-,
I in = --------------- P in = V in I in = ---------------- . (2)
[5], is derived by assuming that the output voltage is constant, Rs Rs
i.e., by ignoring the dynamics of the voltage loop above half the
line frequency, under which the switching-frequency averaged The pulse-width modulator in Fig. 1 is assumed to use
model of the boost power stage becomes linear. The resulting leading-edge modulation such that the off-time duty ratio,
impedance model is valid for large-signal operation and can be d ' = 1 – d , of the switch is proportional to the output of the
used to predict not only the input impedance of the converter current amplifier, vc. Assuming that the PWM signal has a
but also its input characteristics under different lines. peak-to-peak value equal to Vm, the modulator has a gain of 1/
The high-frequency impedance model described in this Vm, and the off-time duty ratio of the switch can be written as
paper was originally obtained as a by-product of a research
v
effort on input current zero-crossing distortion in single-phase d' = 1 – d = ------c- (3)
PFC converters [9]. During the preparation of the current paper, Vm
the author came across references [10] and [11] which reported
where d is the on-time duty ratio of the switch. It is known that
similar high-frequency models. In comparing the two
leading-edge modulation can reduce the output voltage ripple
approaches, it was found that the derivation in [10] and [11]
of the PFC converter when its load is a trailing-edge modulated
assumed small-signal operation of the converter, and the results dc-dc converter [13].
were actually for the input impedance of the boost stage, i.e.,
Derivation of the high-frequency impedance model follows
excluding the front-end rectifier bridge. In contrast, this paper
the modeling procedure outlined in the [9]. First, with standard
uses a large-signal approach to determine the input impedance
average current control, the current compensator output, vc, can
at the ac side directly. Additionally, the models in [10] and [11]
be written as
were verified indirectly by measurements of the current loop
gain, while direct measurements of the input impedance are V c(s) = [ R s i L – R l I ref(s) ]H c(s) (4)
provided in this paper for model validation.

II. HIGH-FREQUENCY IMPEDANCE MODEL iL

+ +
D1 D2 L D
This section presents the development of the high-frequency |vin| S +

Load
input impedance model for boost single-phase PFC converters vs V0
C _
with average current control. The basic converter circuit and d(t)
D3 D4 _
control is shown in Fig. 1. There, it is assumed that the inductor _
current is sensed by using a resistor. Other current sensing iin
Rs
methods can also be used, and the model presented in the +_ Rl
following is applicable in general. Reference iref for the vin
inductor current is generated by a multiplier with three inputs:
Cp
k mv a v in
i ref = --------------------
- |vin| Rz Cz
v ff2 km|vin|va
va _ vc d’(t)
where vff vff2 iref PWM
+
1) va is the output of the output voltage compensator, and
Rl
2) vff is generated by a low-pass circuit and represents the rms
value of the line voltage for input feedforward control [8].
The crossover frequency of the output voltage loop in single-
Fig. 1. Simplified boost single-phase PFC converter circuit for the derivation
phase PFC converters is usually well below the line frequency of input impedance at high frequencies. The converter uses leading-edge mod-
[8]. Hence the output of the voltage compensator, va, can be ulation and standard average current control.

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 where H c(s) is the current compensator transfer function: R l V 0V m –1 H (s)I (s) V in(s)
c ref
I in(s) = -----------------------------------------------
- + ----------------------------------------------
- (10)
Kc( 1 + s ⁄ ωz ) Ls + R s V 0 V m H c(s) Ls + R s V 0 V m
– 1 –1 H (s)
c
H c(s) = --------------------------------
-, (5)
s ( 1 + s ⁄ ωp)
Defining
with
RsV0 Kc s s2
Cp + C z ωn = ------------------ , p(s) = 1 + ------ + ------ (11)
1 1
- , ω z = ----------- , ω p = ------------------
K c = ---------------------------- . LV m ω z ω n2
( C p + C z )R l CzRz Cp Cz Rz
and assuming that the effects of the current compensator pole,
Since the pulse-width modulator can be modeled by a constant ω p , on the input impedance can be ignored, i.e.†,
gain under average current control [12], the off-time duty ratio
of the switch can be expressed as Kc( 1 + s ⁄ ωz )
H c(s) ≈ --------------------------------
-, (12)
s
1
D'(s) = ------- [ R s i L – R l I ref(s) ]H c(s) . (6)
Vm transfer function (10) can be simplified to

To model the boost power stage, we further assume that 1 + ----- s-

R l I ref(s) ω z V in(s) s
1) all components in the circuit are ideal, I in(s) = ------------------- ⋅ --------------- + -------------- ⋅ --------- . (13)
2) the boost inductor operates in the continuous conduction mode Rs p(s) Lω n2 p(s)
(CCM) over the entire line cycle, and
Considering (1), the input impedance of the converter can be
3) the sensing resistor, Rs, is small such that the voltage across it determined from (13) as follows:
can be ignored when modeling the power stage.
Based on these and the assumption that the output voltage is V in(s) R p(s)
- = -------s- ⋅ -------------------------------------------------
Z in(s) = ------------- (14)
constant, an average model can be written for the boost I in(s) gR l Rs 
1 + s  ------ + ------------------
1
inductor current, iL: -
 ω gR Lω 2
z l n
di Note that (14) gives directly the input impedance of the PFC
L ------L- = v in – d'V 0 . (7)
dt converter at the ac side. It is also a large-signal model since
small-signal operation is not assumed in the derivation.
Since i in = sgn ( v in ) ⋅ i L , (7) can be rearranged to
A small filter capacitor is usually placed on the dc side of the
di in rectifier bridge, as shown in Fig. 3, to reduce high-frequency
- = v in – sgn ( v in ) ⋅ d'V 0 .
L -------- (8) noises in the rectified dc voltage. This capacitor should be as
dt
small as possible in order not to cause significant phase shift at
On the other hand, multiplying both sides of equation (6) by the the fundamental frequency, which would otherwise lead to high
sign function, sgn(vin), yields zero-crossing distortion of the input current [9]. Yet the effect
of this capacitor on the input impedance, especially at high
1
sgn ( v in ) ⋅ D'(s) = ------- [ R s i in – R l I ref(s) ]H c(s) . (9) frequencies, may not be negligible. When considering this
Vm
capacitor as well as the commonly used ac-side filter capacitor,
Equations (8) and (9) indicate that the input current dynamics Cac, the total input impedance of the converter can be written as
of the boost single-phase PFC converter can be represented by follows where Z in(s) is defined by (14):
the block diagram shown in Fig. 2, based on which a transfer
Z in(s)
function can be derived for the input current in response to the Z in'(s) = ------------------------------------------------------
- (15)
input voltage and the reference: 1 + ( C dc + C ac )sZ in(s)

Vin(s) 1 Iin(s) +
+ Boost
sL
vin Cdc
V0 Cac Stage
Rs
Vm −
_
RlIref(s)
Hc(s) + Fig. 3. Boost single-phase PFC converter with an ac and a dc filter capacitor.

Fig. 2. Block diagram representing high-frequency dynamics of boost sin- †. This is justified as ω p is usually placed at half the switching frequency to
gle-phase PFC converters. attenuate high-frequency noise in the control loop.

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 III. MODEL VALIDATION in this measurement, but no ac-side filter capacitor was used.
As can be seen, the measurement results agree with the model
The boost single-phase PFC converter described in [13] was prediction over the entire frequency range (10 Hz to 100 kHz).
measured under various operating conditions to verify the The measurement error around 50 Hz was due to the fact that
impedance model (14). Following are the major parameters of the frequency of the injected signal in this region is equal or
this converter (refer to Fig. 1): boost inductor L = 1 mH, steady close to the fundamental frequency of the line so that it cannot
state output voltage V0 = 385 V, sensing resistor Rs = 0.25 Ω, be distinguished from the fundamental.
PWM signal peak-peak voltage Vm = 4 V, Rl = 4 kΩ, Rz = 12 kΩ, It shall be pointed out that averaged models, such as the
Cz = 1.2 nF, and Cp = 270 pF, switching frequency fs = 100kHz. input impedance models (14), are usually useful in predicting
With the given compensator parameters, the zero, ωz, is calculated frequency responses up to 1/3 of the switching frequency. The
to be ω z = 69444 rad/sec, while its dc gain is Kc = 170068. Then, input impedance of the experimental boost converter above 30
using (11), ω n can be calculated as follows: kHz is dominated by the effect of the 30 nF dc side filter
capacitor mentioned above, so that the agreement between the
R s V 0K c 0.25 × 385 × 170068 measured and predicted responses above 30 kHz in Fig. 4
ωn = ------------------ = -------------------------------------------------- = 63970.8
LV m 10 –3 × 4 should be interpreted as a proof of the accuracy of the total
input impedance expression (15), not as an indication that (14)
Input impedance measurement of the converter was is valid beyond 1/3 of the switching frequency.
conducted by injecting, through a power amplifier and an Fig. 5 shows the input impedance response of the converter
isolation transformer, a sinusoidal perturbation to the input at 400 Hz input, which is the standard ac bus frequency on most
voltage and measuring the resulting perturbation in the input of today’s commercial jet airplanes. The input power in this
current. Fig. 4 shows the input impedance responses of the case is 106 W (corresponds to g = 0.5 × 10 –6 ). Good
converter at 50 Hz input. The input voltage was 115 V (rms), agreement between experimental measurements and model
and the input power was 53W (corresponds to predictions can again be seen. The measurement error around
g = 0.25 × 10 –6 ). The dashed lines represent the experimental 400 Hz is again due to the inability of the network analyzer to
measurement results, while the solid lines are predicted from distinguish the injected signal from the fundamental component
(15). A 30 nF capacitor was used on the dc side of the rectifier of the line. Furthermore, Fig. 6 shows the total input impedance

60 65
55 60
Magnitude (dB-Ω)

Magnitude (dB-Ω)

55
50
50
45
45
40
40
35 35

100 1000 10000 100000. 100 1000 10000 100000.

Frequency (Hz) Frequency (Hz)

60 75
40
50
20
Phase (DEG)

Phase (DEG)

25
0
0
-20
-25
-40
-60 -50
-80 -75

100 1000 10000 100000. 100 1000 10000 100000.

Frequency (Hz) Frequency (Hz)
Fig. 4. Input impedance of the boost single-phase PFC converter at 50 Hz, 53 Fig. 5. Input impedance of the boost single-phase PFC converter at 400 Hz,
W input. Solid lines: predicted; dashed lines: measured. 106 W input. Solid lines: predicted; dashed lines: measured.

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 50 60
55
Magnitude (dB-Ω)

Magnitude (dB-Ω)
40
50
30
45
20
40
10 35

100 1000 10000 100000. 100 1000 10000 100000.

Frequency (Hz) Frequency (Hz)

0 100

-20 80
Phase (DEG)

Phase (DEG)
60
-40 40
-60 20
0
-80
-20

100 1000 10000 100000. 100 1000 10000 100000.

Frequency (Hz) Frequency (Hz)
Fig. 6. Input impedance of the boost PFC converter with an ac side capacitor Fig. 7. Input impedance responses of the boost PFC converter without filter
Cac = 1.5mF, a dc side capacitor Cdc = 30 nF, and at 400 Hz, 106 W input. capacitors Cdc and Cac. The two sets of plots correspond to g = 0.5x10-6
Solid lines: predicted responses; dashed lines: measured responses. (dashed lines) and g = 0.25x10-6 (solid lines), respectively.

of the converter with a 1.5 µF filter capacitor placed at the ac

side of the rectifier bridge. The measurements were taken at
400 Hz input, with 106 W input power. The close correlation
between experimental measurements and model predictions
proved the accuracy of the presented input impedance model.
IV. INPUT IMPEDANCE ANALYSIS
The impedance responses in the previous section were
measured under small-signal operation conditions. The input
impedance model (14) is, however, valid for large-signal
operation as well and can be used to study characteristics of the
converter to different inputs. The impedance plots in Fig. 4-5
included the effects of Cdc, the capacitor on the dc side of the
rectifier bridge, see Fig. 3. Since this capacitor is not part of the
essential function of the converter and can have very different
values in different designs, frequency-domain responses of Zin
(without Cdc) are plotted using (14) in Fig. 7 for the example
boost converter with g = 0.25 × 10 –6 and 0.5 × 10 –6 , respec-
tively. The input voltage is 115 V (rms) in both cases.
A. Input Impedance Dipping
The most noticeable feature of the plots in Fig. 7 is the
dipping of the input impedance in the frequency region ranging
from 1 kHz to about 30 kHz. This is caused by the pole
R s  –1
s p =  ------ + ------------------
1
- (16)
 ω gR Lω 2
z l n
in Zin(s). As can be seen, this pole is always smaller than the
zero, ω z , of the current compensator and moves to lower
frequency as g decreases (so does the input power). The
maximum dipping happens at a frequency corresponding to the
resonant frequency of p(s)†, from which the impedance starts to
rise. For the measured boost PFC converter, this happens at
about 10 kHz, as can be seen from Fig. 7.
The amount of maximum dipping in the input impedance is
also affected by the characteristics of the zeros of p(s),
especially its damping factor, ζ, defined by
ωn 1 R sV 0Kc
ζ = -------- -.
- = --------- -----------------
2ω z 2ω z LVm
To maximize the current loop gain, the common design practice
is to place the zero, ωz, of the current compensator at the cross-
over frequency, ωc, of the current loop [8]. Since the duty ratio
to inductor current transfer function of the boost converter in the
high frequency region is given by V 0 ⁄ ( sL ) , see Fig. 1, unity gain
of the current loop at ωc = ωz implies that [9]
†. It will be shown later that the second-order function p(s) is always under-
damped in conventional designs so that it has two complex conjugate poles.

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 R V0 2K R
H c(jω c) ⋅ ------s- ⋅ ---------
- ≈ -------------c ⋅ ------s- ⋅ ---------
V m ω cL ω c V m ω cL
Using this, the damping factor of p(s) can be calculated as follows:
1 R sV 0K c 1 ω
- = --------- ⋅ ------c- = 0.42
ζ = --------- -----------------
2ω z LV m 2ω c 4 2
Therefore, the two zeros of p(s) (hence zeros of the input
impedance) are under-damped, which causes an undershoot at
the resonant frequency of p(s) and further adds to the dipping in
the input impedance. Fig. 8 shows the magnitude response of
p(s) for the measured boost converter with g = 0.25 × 10 –6 .
As can be seen, there is about 3 dB undershoot at 8 kHz which
contributes to the dipping in the input impedance.
Stability of a PFC converter connected with an input EMI
filter requires that the impedance ratio, Z 0(s) ⁄ Z in(s) , meets the
Nyquist criterion, where Z 0(s) is the output impedance of the
filter. To provide sufficient attenuation for the switching-
frequency ripple, the corner frequency of the EMI filter is
usually designed to be 1/10 of the switching frequency, which
would be 10 kHz for the measured boost PFC converter. Since
the output impedance of the EMI filter peaks at the corner
frequency, a dipping in the input impedance of the PFC
converter in the same frequency region can greatly increase the
potential for instability or deteriorated performance of the
converter. The analytical input impedance model derived here
can be used to guide the converter and EMI filter design to
avoid undesirable interactions, see Subsection C.
75
70
65
Magnitude (dB)
60
55
50
45
100 1000
Frequency (Hz)
Fig. 8. Frequency response of function p(s) defined by (11). Shown here is
the magnitude response with g = 0.25x10-6.
B. Response to Different Lines
The large-signal nature of the input impedance model (14)
also allows it to be used to study the response of the converter
to input voltages at different frequencies. As can be seen from
Fig. 7, when the line frequency is well below the pole of Zin(s),
the actual input current will be in phase with the input voltage,
with a magnitude determined by the control parameter g
according to (2). However, the decrease of the input impedance
with frequency (beyond 500 Hz) implies that the same value of
g will result in higher input current when the line frequency
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V0 approaches the pole of Zin(s). Additionally, the input current
- = 1. (17) starts to lead the input voltage as the line frequency goes up,
and the leading phase of the input current becomes significant
(e.g., at 1 kHz) even before the change in magnitude becomes
appreciable. Furthermore, the plots in Fig. 7 suggest that these
effects are more significant under light load conditions when g
(18) is small. The leading phase of the input current also causes
harmonic distortion in the input current around the zero
crossing of the input voltage, as explained in [9].
The input impedance model can also be used to predict
response of the converter to distorted lines. In particular,
dipping of the input impedance at high frequencies imply that
an x percent harmonic voltage at these frequencies will
generate more than x percent harmonic current. For example,
the magnitude plot in Fig. 4 shows a maximum of 15 dB
dipping (from 48 dB at 200 Hz and below to 33 dB at 9 kHz).
This implies that, with reference currents having the same
amplitude, i.e., the same value of g, an input voltage at 9 kHz
would generate a current that is 5.6 times (15 dB = 5.6234) of
the current generated by the same voltage at 200 Hz or lower
frequency. In other words, assuming the line frequency is under
200 Hz, 1% harmonic voltage at 9 kHz would generate as much
as 5.6% harmonic current at the same frequency. This can be a
major concern for PFC converters that have to meet harmonic
current limits under distorted lines, such as the recently issued
DO-160D for airborne equipment†.
C. Performance Improvement
The two causes discussed in Subsection A for the dipping in
the input impedance, namely, the low-frequency pole and the
under-damped zeros of Zin(s), also point to possible ways for
reducing the dipping.
First, (14) indicates that it is possible to redesign the
reference current generation circuit to make Zin(s) purely
resistive over the entire frequency range (i.e., up to 1/3 of the
switching frequency in which the average model is valid). This
can be achieved by adding a phase shift circuit to the |vin| input
pin of the multiplier shown in Fig. 1. Assuming the transfer
function of this circuit is Q(s), the reference current becomes
10000 100000. then I ref(s) = gQ(s)V in(s) . Based on (13), a transfer function
Q(s) that will result in complete cancellation of the pole and
zeros of Zin(s) is determined to be
Rs  s 2
1 + s  ------ – ------------------
1
- + ------
 ω gR Lω 2 ω 2
z
Q(s) = --------------------------------------------------------------n- .
l n
(19)
1 + s ⁄ ωz
As can be seen, this transfer function is dependent of control
parameter g. Therefore, its realization would require an
adaptive filter and is best implemented using digital circuits,
which is beyond the scope of this paper. A simplified version of
it, as given below
†. DO-160D requires that, for every 1% of individual voltage harmonic, the
equipment shall not demand harmonic current greater than 1.25% above the
limit for the corresponding harmonic current with undistorted input.
366
 1 V. CONCLUSIONS
Q(s) ≈ ---------------------
1 + s ⁄ ωz
can be used instead for analog implementation. Fig. 9 compares
the input impedance responses of the boost PFC converter [13]
before and after a phase shift circuit described by (20) is added.
The plots correspond to an input power of 53 W
( g = 0.25 × 10 –6 ), and the measurement was taken with 400
Hz input. As can be seen, the model predicts that inclusion of
the phase shift circuit would reduce the maximum input
impedance dipping by as much as 5 dB, while actual
measurement shows a 3 dB reduction due to imperfect experi-
mental setup.
The phase shift circuit described by (20) was used in [9] as a
means to compensate for the leading phase of the input current
so as to reduce the associated input current zero-crossing
distortion. Practical implementation of the circuit and its other
benefits were also discussed there. It was also noted in [10] that
adding a phase shift, such as the one described by (20), to the
reference current can improve the stability of the current loop
in the interconnected EMI filter-PFC converter system, which
is an indirect proof of the effect of reference current phase shift
in reducing the dipping of converter input impedance.
Furthermore, the analysis in the previous subsection indicates
that reducing the dipping in the input impedance would also
improve the response of the converter to distorted line voltages.
(20)
A large-signal model is presented for predicting input
impedance response of single-phase boost PFC converter with
average current control. The model complements previously
published low-frequency impedance models and is directly
verified by impedance measurements from a prototype
converter. It is also used to study input characteristics of boost
single-phase PFC converters in general. A particular issue
discussed is the dipping in the input impedance and its impacts
on converter performance. Based on the analyses, a simple
phase compensation method is proposed and its effectiveness in
reducing input impedance dipping demonstrated.
ACKNOWLEDGMENTS
The experimental results were taken at Rockwell Collins,
Inc. where the author worked until August 2002. Continuation
of the work at RPI was supported in part by Rockwell Collins
through the Center for Power Electronics Systems (CPES), an
Engineering Research Center of the National Science
Foundation. The author also wants to thank Mr. James Noon of
Texas Instruments for providing the UCC3817 single-phase
PFC evaluation boards used for the experiments.
REFERENCES

[1] R. D. Middlebrook, “Input filter considerations in design and application

65 of switching regulators,” Proceedings of IEEE Industry Applications
60 Society Annual Meeting, pp. 366-382, 1976.
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