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How to Use and Design Interposer PCB in Chip Packaging?

Advanced semiconductor devices exist today only due to the major

advances their packaging gives. Heterogeneously incorporated

components depend on the physical structure, which is known as an

interposer. It offers electrical connections among the various components

of a package and dies. These types of structures are reliable for circuit

boards as they offer a substrate material for making connections between

various components of one package. As regards design, an interposer

gives more freedom than a PCB.

Nevertheless, interposer provides packaging designers with a certain kind

of flexibility in the process of arranging and connecting 2.5 and 3D

incorporated electrical components. They give restrictions over what one

can do with an interposer. EDA software tools for PCB designs and ICs do

not automate the necessary design tasks of interposer completely. This

happens because the interposer does not have any characterized

standard, and it keeps growing day by day.

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Table of Contents

Anatomy Of An Interposer PCB

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Advanced packages of components need custom-designed interposers to

accommodate the substrate of the package and particular chip packages.

This makes the interposers most likely similar to bare PCBs. As they offer a

complete platform for assembling the full package. However, all sorts of

interposers have specially designed three main roles, which include:

1. To give a surface mounted for a semiconductor die inside the

incorporated heterogeneous components.

2. Thus, to allow a connection to create between the dies of the

semiconductor.

3. To create a connection of the whole stack to the substrate of

packaging.

This structure consists of small pada and small via to create a connection

to the dies of the semiconductor within the package. However, the

interposer then connects again with the substrate of a package. This

provides routing between the package’s external side and the

components. The substrates’ lower side encompasses a solder balls array

that can easily be put on the ground pattern of the surface of a PCB.

Moreover, between micro bumps which present on the interposer top

layer and the TSV area, there is RDL or a redistribution surface. The layer

consists of the primary horizontal interfacial link that offers a connection

between the dies of components over the interposer top layer. Though,

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the interconnected structure in the redistribution later looks similar to

buried or blind microbial of an HDI PCB.

Furthermore, Interposer uses three materials. This includes an organic

substrate, glass, or silicone. Interposer produces at main founders, which

includes the horizontal interconnection and TSVs that connect

semiconductor dies and substrate of package. The interposer has two

different types of functions: as a passive or an active device.

Active & Passive Interposer PCB

STM32 PDB Design

Passive interposer works simply with the main function. It creates

connections between the component dies, which are present over the

interposer top layer. Apart from conductive trails, these electrical

components do not have any type of electrical circuit. They only provide

structure to support the conductive routes for signals.

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Moreover, glass and organic materials are substrate materials

for insulation. Therefore, this enables them to work only in the form of

passive interposers, especially for conductive interconnects across the

package. As silicon acts as a semiconductor, it helps in creating an active

interposer. This consists of devices incorporated in the structure of

silicone. These types of interposers must possess TSVs’ lower density

because of the location of keep-outs inside the structure. Inactive

interposers, a typical device includes input-output interface controllers.

or DC-DC converter.

Packaging Substrate

The substrate of the package refers to another significant part of the

package. However, if you focus on the bottom substrate’s cross-section

area, then you may find it resembling the PCB internal layers. Moreover,

the interposer creates connections using the substrate with its

connections of mini solder balls. Then substrates take these connections

among the component dies placed over the interposer. Thus, the electrical

connections eventually come to the lower surface, where these

connections create further links with the ball array present in the package

of BGA.

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Interposer PCB-Based Components In Electronics Assembly

Interposer serves as an important structure. It helps in driving advanced

innovations with high-tech packaging and constant incorporation of great

features in a compact space. But all packages of chips seem worthless

unless they are incorporated in the assembly of PCB along with

other electronic components. For HD interposer-based electrical

components, PCB designers must understand how to route and place a

BGA package with escape and fanout routing specifications.

However, before routing or placing these components or BGA footprint,

keep the following points in mind:

1. Stackup design creates specific requirements of routing, like

impedance-controlled signals trace width.

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2. The via restricts the available area for signal escape routing.

Therefore, via-in-pad is needed in this situation.

3. Ensure the house requirements of your fabrication. This helps in

understanding the compatibility of design of via and stack up along

with capabilities.

Amazing Benefits of Interposer PCB

Many PCB manufacturers tend to use interposer PCBs. It helps in creating

an interface or connection that supports the eliminated electrical

components on the surface of the board that does not redesign. This may

happen because of manufacturing specifications, or it may be more

affordable and practical to use than the one you have.

With time, the popularity of interposer usage in the package of IC chips

keeps growing. Though, many regulators and manufacturers keep

pushing businesses to not use lead-based electrical components in the

device. Moreover, these components may limit the new PCB’s ability to

work along with the old techniques and equipment.

This enhances the significance of 9f manufacturers and vendors of IC

substrates such as MCL. We will assist you in working for your board with

the existing equipment and techniques to get the most out of the

investment every time.

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Silicon Interposer PCB – Challenges

Silicon interposers prove a growing and successful achievement in the

technology of IC packaging. This advanced technology soon superseded

the conventional methods of designing chips. Attaching distinct memory

and functional blocks in the same IC package enhances the performance

and offers high speed for advanced technology of design. However,

imposters with new features arise unfamiliar challenges for the designers,

so they must understand the thermal integrity, signal integrity,

and power integrity intercar between the dies of the chipset, the package,

and the interposer. Simulation of the system becomes a vital factor for the

desired functionality of an IC package.

The interposer also serves as a passive element layer along with a thermal

expansion coefficient that matches the chipsets. This describes the fame

of silicon for the interposers. Although, it will not obsolete the joule

heating and therm hot points problems in a design. However, an

interposer with a distinct coefficient of thermal expansion on the surface

of the ordinary substrate. This enhances the interposer warpage and

mechanical stress. This is the point where a designer must be worried

about the system’s ability. Because this stress can easily break thousands

of micropump links.

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Moreover, silicone interposer offers significantly dense input/output

connectivity. This allows better usage of die area and higher bandwidth.

But multiple IPs of the same package need multiple sources of power,

which makes a complex network of power delivery inside a single package.

The PDN goes through the whole package and becomes sensitive to the

noise of power. This leads to problems of power integrity. Evaluating the

current signature and voltage distribution of each chip inside the

interposer ensures power integrity. Furthermore, a considerable power

amount across the vertical links between components makes more power

integrity problems. This may include C4 bumps, TSVs, hybrid bonding links,

and tiny micro-bumps. Lastly, various signals with high speed routed

between interposers and chips can easily create problems of

electromagnetic crosstalk and coupling.

Ensure to put signal integrity for digital signals with high speed in your list

while designing the IC package with an interposer. Also, this technology

consists of a high-density, power-efficient approach and cost-effectiveness.

Yet, it is still sensitive to thermal, EM interference, power, and signal

integrity problems.

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Power Integrity

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INA common PCB layout

Power proves the most essential factor for any design of an IC package.

However, chip power consumption drives everything across the design of

the package inside the package IC. 3ach chip requires different types of

power. This leads to the specifications of the delivery network of power.

Moreover, The PDN also plays an important role in managing the integrity

of power within the IC package by reducing the IR drop or voltage drop.

Therefore, to maintain the network of power delivery, simulate the

fluctuating current over each connection of IC along with a passive

element parasitic that is set up to the PDN. The interposer makes it more

complicated as chips are linked across the interposer. Ground and power

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trails that route across the interposer give new challenges while evaluating

the power integrity.

However, this does not seem to be a signal issue. It creates PI problems

along with electromigration issues. Make sure that the density of the

current at each geometry piece must mold and keep it below the max limit.

However, wires and micro bumps joule heating directly impacts the max

limit of current density. This allows the thermal simulation degree for max

precision.

Signal Integrity

In the package of IC, signals with high-speed transfer from one component

die to the other using interposer at high rates. However, the signal is

compact with a long space. This enables them to be sensitive to

electromagnetic coupling and interface. Although, digital designers must

follow design with high-speed guidelines to keep the Signal integrity. This

is the only method to manage the EMI or EMC faster. An electromagnetic

solver with high capacity extracts the EMC, which includes chipsets, the

coupling effect of the system, and signal routing with an interposer. You

can easily analyze all th3 factors in one large model and be able to get

desired results of a clear eye graph. Ansys Q3D and HFSS also help in

extracting the RLC parasitics and offer electromagnetic field visualization,

and get up the extraction of system level far from the interposer.

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Related Posts:

1. A Comprehensive Overview of WLCSP: Wafer Level Chip Scale

Packaging

2. Revolutionize Your Business with EDA Chip Design

3. The Essential Guide to Electronic Component Packaging

4. What is BGA Chip ?

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