Set A Answer

ROYAL UNIVERSITY OF BHUTAN

COLLEGE OF SCIENCE AND TECHNOLOGY
PHUENTSHOLING : BHUTAN

SUMMER SEMESTER EXAMINATION: 2013

Class : BE Third Year Electrical Engineering

Module : Microprocessor and Interfacing

Module Code : SAS302

Max. Marks : 50

Max. Time : 3 Hrs

General Instructions:
1. Answer all the questions.

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Question No.1 [ 2,2]
1.1 Explain “Moore’s Law”.
The number of transistors per integrated circuit would double 18
months. 2 mark
1.2 Explain hand assembly.
1. Write the instructions in mnemonics obtained from the
instruction set supplied by the manufacturer. 0.5 mark
2. Find the hexadecimal machine code for each instruction by
searching through the set of instructions. 0.5 mark
3. Enter (Load) the program in the user memory in a sequential
order by using the Hex keyboard as the input device. 0.5 mark
4. Execute the program by pressing the Execute key. The answer
will be displayed by the LEDs. 0.5 mark

Question No.2 [ 2.2,1.2,2]

2.1 Assemble the following program, starting with the memory
address 8000H.
MVI A,8FH ;Load the first byte
MVI C,D3H ;Load the second byte
XRI A2H ;Excusive-OR A2H with (A)
ADD C ;Add (C) to (A)
STA 800BH ;Save the result in 800BH
HLT ;End of the program
Memory Address Hex Code
8000 3E 0.2 mark
8001 8F 0.2 mark
8002 0E 0.2 mark
8003 D3 0.2 mark
8004 EE 0.2 mark
8005 A2 0.2 mark
8006 81 0.2 mark
8007 32 0.2 mark
8008 0B 0.2 mark
8009 80 0.2 mark
800A 76 0.2 mark
2.2 In Question 2.1, specify the contents of the memory location
800BH and the status of flags S, Z, AC, P, and CY after the
program is executed. each 0.2 mark
(800BH) = 00H, S = 0, Z = 1, AC = 1, P = 1, CY = 1
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2.3 In Question 2.1, write the assembly program if the second byte
8FH of the instruction MVI A,8FH, the second byte D3H of the
instruction MVI C,D3H, and the second byte A2H of the
instruction XRI A2H are omitted. Also, specify the contents of
the memory location 800BH and the status of flags S, Z, AC, P,
and CY after the program is executed.
The program changes as follows. 0.8 mark
MVI A,0EH
XRI 81H
STA 800BH
HLT No ‘HLT’ −0.2 mark
(800BH) = 8FH, S = 1, Z = 0, AC = 0, P = 0, CY = 0
each 0.2 mark
Question No.3 [ 2,2,2.8,2.4,1.2]
3.1 Write logical steps to load the four decimal numbers 00H, 04H,
06H and 0AH in registers A, B, C and D, respectively. Multiply
the three numbers 04H, 06H and 0AH, and store the product in
memory location 8018H. Order is important.
i. Load the numbers 00H, 04H, 06H and 0AH in registers A, B,
C and D, respectively. each 0.2 mark
ii. Add the contents of register B to the accumulator.
iii. Decrement the contents of register C by 1.
iv. If the contents of register C are not equal to zero, go to ii.
v. Copy the accumulator contents to register E.
vi. Clear the accumulator.
vii. Add the contents of register E to the accumulator.
viii. Decrement the contents of register D by 1.
ix. If the contents of register D are not equal to zero, go to ii.
x. Store the accumulator contents in memory location 8018H.
3.2 Draw a flowchart of Question 3.1.

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 Order is important.
Start

Load Hex Numbers

in Registers Clear the accumulator
0.2 mark 0.2 mark

Add register B to Add register E to the

the accumulator accumulator
0.2 mark 0.2 mark
Decrement register C Decrement register D
by 1 by 1
0.2 mark 0.2 mark

No Is register No Is register
C Zero? D Zero?

0.2 mark 0.2 mark

Yes Yes
Copy the accumulator Store the accumulator
contents to register E contents in memory
0.2 mark 0.2 mark
End

3.3 Translate the logical step in Question 3.1 into the 8085 assembly
program. Use the instructions ‘JNZ LOOP1’ and ‘JNZ LOOP2’.
MVI A,00H ;Load the first byte Order is important.
MVI B,04H ;Load the second byte
each 0.2 mark
MVI C,06H ;Load the third byte
MVI D,0AH ;Load the fourth byte
LOOP1:ADD B ;Add the contents of B to the accumulator
DCR C ;Decrement the contents of C by 1
JNZ LOOP1 ;Jump if the contents of C is non-zero
MOV E,A ;Copy the accumulator contents to E
SUB A ;Clear the accumulator
LOOP2:ADD E ;Add the contents of E to the accumulator
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 DCR D ;Decrement the contents of D by 1
JNZ LOOP2 ;Jump if the contents of D is non-zero
STA 8018H ;Store the accumulator contents in memory
HLT ;End of the program
3.4 Assemble the assembly program in Question 3.3, starting with the
memory location 8000H.
Memory Address Hex Code each byte 0.1 mark
8000 3E
8001 00
8002 06
8003 04
8004 0E
8005 06
8006 16
8007 0A
8008 80
8009 0D
800A C2
800B 08
800C 80
800D 5F
800E 97
800F 83
8010 15
8011 C2
8012 0F
8013 80
8014 32
8015 18
8016 80
8017 76
3.5 In Question 3.4, specify the contents of the memory location
8018H and the status of flags S, Z, AC, P, and CY after the
program is executed. each 0.2 mark
(8018H) = F0H, S = 0, Z = 1, AC = 1, P = 1, CY = 0

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Question No.4 [ 1,2,1]
4.1 In Figure 1, specify the output line that goes low if the input
(including the enable lines) to the 4-to-16 decoder is
A7 A6 A5 A4 A3 A2 A1 A0
0 0 1 0 1 1 1 1

Figure 1
The line 5 (O5). (01012 = 5H) 1 mark
4.2 List the high-order, low-order, and don’t care address lines in
Figure 2. How many pages of memory does the chip include?
The high-order address lines are A15-A14, 0.5 mark
the low-order address lines are A9-A0, 0.5 mark
and the don’t care address line are A13-A10. 0.5 mark
The chip includes 4 pages (1024/256 = 4) 0.5 mark
4.3 In Figure 2, identify the memory addresses, assuming all the
don’t care address lines at logic 0.

Figure 2
The memory addresses range 1 mark
from 8000H (= 10 0000 00000000002)
to 83FFH (= 10 0000 11111111112).
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Question No.5 [ 4,4]
5.1 In Figure 3, specify the memory address ranges of ROM1, ROM2,
R/WM1, and R/WM2.
The memory addresses of ROM1 range 1 mark
from 0000H (= 000 00000000000002)
to 1FFFH (= 000 11111111111112).
The memory addresses of ROM2 range 1 mark
from E000H (= 111 00000000000002)
to FFFFH (= 111 11111111111112).
The memory addresses of RW/M1 range 1 mark
from 8400H (= 100001 00000000002)
to 87FFH (= 100001 11111111112).
The memory addresses of RW/M2 range 1 mark
from 9400H (= 100101 00000000002)
to 97FFH (= 100101 11111111112).
5.2 In Figure 3, eliminate the second [lower] decoder and connect
̅̅̅̅̅4 ) of the first [upper] decoder to (CE
(CS ̅̅̅̅ ) of the R/WM1, and
connect (CS ̅̅̅̅̅6 ) of the first [upper] decoder to (CE
̅̅̅̅) of the R/WM2.
Then, identify the primary address ranges and the mirror
(foldback) address ranges of the R/WM1 and RW/M2.

Figure 3

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 The primary memory addresses of R/WM1 range 1 mark
from 8000H (= 100 000 00000000002)
to 83FFH (= 100 000 11111111112).
The foldback memory addresses of R/WM1 range 1 mark
from 8400H (= 100 001 00000000002)
to 9FFFH (= 100 111 11111111112).
The primary memory addresses of R/WM2 range 1 mark
from C000H (= 110 000 00000000002)
to C3FFH (= 110 000 11111111112).
The foldback memory addresses of R/WM2 range 1 mark
from C400H (= 110 001 00000000002)
to DFFFH (= 110 111 11111111112).

Question No.6 [ 1,2,2.4,2,1.8]

6.1 Specify the crystal frequency required for an 8085 system to
operate at 1.2 MHz.
The crystal frequency is internally divided by two; therefore, the
crystal frequency should have a frequency of 2.4 MHz. 1 mark
6.2 Figure 4 shows 8085 timing for execution of some instruction.
Identify the machine cycles M1, M2, M3, and M4.
M1; Opcode Fetch 2 mark
M2; Memory Read
M3; Memory Read
M4; Memory Read
6.3 In Figure 4, specify the Hex machine code and its memory
address 8018 F0H −0.8 mark
8014 3A 0.8 mark
8015 18H 0.8 mark
8016 80H 0.8 mark
6.4 In Question 6.3, identify mnemonics.
LDA 8018H 2 mark
6.5 In Figure 4, identify the accumulator contents after the execution
of the instruction.
A=F0H 1.8 mark

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Figure 4

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Question No.7 [ 1,1,1,1,1,1]
7.1 In Figure 5, identify the primary port address and the foldback
(mirror) port address for the input port A.
The primary port address is F7H (=1111 0 1112). 0.5 mark
The foldback (mirror) port address is FFH (= 1111 1 1112). 0.5 mark
7.2 In Figure 5, identify the primary port address and the foldback
(mirror) port address for the input port B.
The primary port address is F6H (= 1111 0 1102). 0.5 mark
The foldback (mirror) port address is FEH (= 1111 1 1102). 0.5 mark
7.3 In Figure 5, identify the primary port address and the foldback
(mirror) port address for the output port A.
The primary port address is F3H (= 1111 0 0112). 0.5 mark
The foldback (mirror) port address is FBH (= 1111 1 0112). 0.5 mark
7.4 In Figure 5, identify the primary port address and the foldback
(mirror) port address for the output port B.
The primary port address is F2H (= 1111 0 0102). 0.5 mark
The foldback (mirror) port address is FAH (= 1111 1 0102).0.5 mark
7.5 In Figure 5, Switch A is correspondent to LED A, and Switch B
is to LED B. which switches from S0 to S7 of Switch A are turned
on to display the number “5.3”? Also, which switches from S0 to
S7 of Switch B are turned on to display the number “5.3”?
Switch A: S0, S2, S3, S5, S6, and S7 are turned on. 0.5 mark
Switch B: S0, S1, S2, S3, and S6 are turned on. 0.5 mark
7.6 In Figure 5, write assembly program to read input port A and
display it at output port A and read input port B and display it at
output port B? Use the primary port address for all the ports.
IN F7H ;Read data from input port A 1 mark
OUT F3H ;Write data to output port A
IN F6H ;Read data from input port B
OUT F2H ;Write data to output port B
HLT ;End of the program No ‘HLT’ −0.2 mark

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Figure 5

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Question No.8 [ 1,1,1]
8.1 In Figure 6, identify the primary port address and the foldback
(mirror) port address for the lower common-anode seven-segment
LED port (The one’s place).
The primary port address is F1H (= 1111 0 0012). 0.5 mark
The foldback (mirror) port address is F9H (= 1111 1 0012). 0.5 mark
8.2 In Figure 6, identify the primary port address and the foldback
(mirror) port address for the upper common-anode seven-segment
LED port (The ten’s place).
The primary port address is F4H (= 1111 0 1002). 0.5 mark
The foldback (mirror) port address is FCH (= 1111 1 1002).0.5 mark
8.3 In Figure 6, write an assembly program to display the number “20”
at the common-anode seven-segment LED ports. Use the primary
port address for both of the common-anode seven-segment LED
ports.
MVI A,A4H ;Code for ‘2’ to upper LED 1 mark
OUT F4H ;Display at upper LED
MVI A,C0H ;Code for ‘0’ for lower LED
OUT F1H ;Display at lower LED
HLT ;End of the program No ‘HLT’ −0.2 mark

Figure 6
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 Appendix 8085 Instruction Summary

Mnemonic Hex Mnemonic Hex Mnemonic Hex Mnemonic Hex

MOV A,A 7F MOV D,C 51 MOV L,E 6B LHLD adr 2A
MOV A,B 78 MOV D,D 52 MOV L,H 6C LDA adr 3A
MOV A,C 79 MOV D,E 53 MOV L,L 6D STAX B 02
MOV A,D 7A MOV D,H 54 MOV L,M 6E STAX D 12
MOV A,E 7B MOV D,L 55 MOV M,A 77 SHLD adr 22
MOV A,H 7C MOV D,M 56 MOV M,B 70 STA adr 32
MOV A,L 7D MOV E,A 5F MOV M,C 71 ADD A 87
MOV A,M 7E MOV E,B 58 MOV M,D 72 ADD B 80
MOV B,A 47 MOV E,C 59 MOV M,E 73 ADD C 81
MOV B,B 40 MOV E,D 5A MOV M,H 74 ADD D 82
MOV B,C 41 MOV E,E 5B MOV M,L 75 ADD E 83
MOV B,D 42 MOV E,H 5C XCHG EB ADD H 84
MOV B,E 43 MOV E,L 5D MVI A,byte 3E ADD L 85
MOV B,H 44 MOV E,M 5E MVI B,byte 06 ADD M 86
MOV B,L 45 MOV H,A 67 MVI C,byte 0E ADC A 8F
MOV B,M 46 MOV H,B 60 MVI D,byte 16 ADC B 88
MOV C,A 4F MOV H,C 61 MVI E,byte 1E ADC C 89
MOV C,B 48 MOV H,D 62 MVI H,byte 26 ADC D 8A
MOV C,C 49 MOV H,E 63 MVI L,byte 2E ADC E 8B
MOV C,D 4A MOV H,H 64 MVI M,byte 36 ADC H 8C
MOV C,E 4B MOV H,L 65 LXI B,dble 01 ADC L 8D
MOV C,H 4C MOV H,M 66 LXI D,dble 11 ADC M 8E
MOV C,L 4D MOV L,A 6F LXI H,dble 21 SUB A 97
MOV C,M 4E MOV L,B 68 LXI SP,dble 31 SUB B 90
MOV D,A 57 MOV L,C 69 LDAX B 0A SUB C 91
MOV D,B 50 MOV L,D 6A LDAX D 1A SUB D 92

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Mnemonic Hex Mnemonic Hex Mnemonic Hex Mnemonic Hex
SUB E 93 INX H 23 ANA E A3 CMP L BD
SUB H 94 INX SP 33 ANA H A4 CMP M BE
SUB L 95 DCR A 3D ANA L A5 ADI byte C6
SUB M 96 DCR B 05 ANA M A6 ACI byte CE
SBB A 9F DCR C 0D XRA A AF SUI byte D6
SBB B 98 DCR D 15 XRA B A8 SBI byte DE
SBB C 99 DCR E 1D XRA C A9 ANI byte E6
SBB D 9A DCR H 25 XRA D AA XRI byte EE
SBB E 9B DCR L 2D XRA E AB ORI byte F6
SBB H 9C DCR M 35 XRA H AC CPI byte FE
SBB L 9D DCX B 0B XRA L AD JMP adr C3
SBB M 9E DCX D 1B XRA M AE JNZ adr C2
DAD B 09 DCX H 2B ORA A B7 JZ adr CA
DAD D 19 DCX SP 3B ORA B B0 JNC adr D2
DAD H 29 DAA 27 ORA C B1 JC adr DA
DAD SP 39 CMA 2F ORA D B2 JPO adr E2
INR A 3C STC 37 ORA E B3 JPE adr EA
INR B 04 CMC 3F ORA H B4 JP adr F2
INR C 0C RLC 07 ORA L B5 JM adr FA
INR D 14 RRC 0F ORA M B6 PCHL E9
INR E 1C RAL 17 CMP A BF CALL adr CD
INR H 24 RAR 1F CMP B B8 CNZ adr C4
INR L 2C ANA A A7 CMP C B9 CZ adr CC
INR M 34 ANA B A0 CMP D BA CNC adr D4
INX B 03 ANA C A1 CMP E BB CC adr DC
INX D 13 ANA D A2 CMP H BC CPO adr E4

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Mnemonic Hex Mnemonic Hex
CPE adr EC POP H E1
CP adr F4 POP PSW F1
CM adr FC XTHL E3
RET C9 SPHL F9
RNZ C0 OUT byte D3
RZ C8 IN byte DB
RNC D0 DI F3
RC D8 EI FB
RPO E0 NOP 00
RPE E8 HLT 76
RP F0 RIM 20
RM F8 SIM 30
RST 0 C7
RST 1 CF
RST 2 D7
RST 3 DF
RST 4 E7
RST 5 EF
RST 6 F7
RST 7 FF
PUSH B C5
PUSH D D5
PUSH H E5
PUSH PSW F5
POP B C1
POP D D1

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