Compal La-E903p R1.a (Diagramas - Com.br)

A B C D E
1 1
Compal Confidential
2
C5V08/C5V09/D5PR8 Schematics Document 2
AMD Bristol Ridge/Stoney Ridge Platform
APU 15W/35W + Radeon R17M-P1-50/70/G1-70 25W/40W/50W

3 3
LA-E903P REV:1.A
2017-04-18
4 4
Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2017/04/18 Deciphered Date 2019/04/18 Title
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
COVER PAGE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C5V08/D5PR8_LA-E903PR1A
Date: Tuesday, May 02, 2017 Sheet 1 of 50
A B C D E
A B C D E
Compal Confidential
Model Name : Wartortle_BS
(Channel A) page 13 (Channel B) *SR only Ch B page 14
1
260pin DDRIV SO-DIMM 260pin DDRIV SO-DIMM 1
Memory BUS(DDR4)
GPU PEG x8
S4 Package 1.2V DDRIV
1866Mhz
RX540 : R17M-P1-50
RX550 : R17M-P1-70
RX560 : R17M-G1-70
AMD USB2.0
page 15~23 Port 0 Port 1 Port 2 Port 3

Display Port
BRISTOL RIDGE S/B page 31 S/B page 31 WLAN/BT Camera
STONEY RIDGE 2.0 Conn. 2.0 Conn. Combopage 29 page 27
Port 0 Port 1
USB2.0 Co-Lay
eDP Conn. HDMI Conn.
page 27 page 26
USB3.0
Port 3
Port 1,2 Port 3
page 32
2 Type-C M/B page 31 2
3.0 Conn. 3.0 Conn.

AMD FP4 APU Port 5 Port 7
BGA 968-balls
HD Audio(AZ)
PCIE
SATA III
Port 2, 3 Port 0 Port 1 page 6~12
SSD page 30 LAN+CR WLAN/BT Port 0 Port 1
NGFF Conn. RTL8411 NGFF Conn.
page 28 page 29 HDD SSD page 30 Audio
Conn. page 30 NGFF Conn. ALC255
USB2.0
SPI page 34
Port 2
Transformer Card Reader
RJ45page 28 Conn. page 28 LPC I2C
page 27 page 31
Port 1 Port 3
3 3
page 10 Int. DMIC Int. Speaker UAJ

ENE G-Sensor PTP on Camera Conn. page 34 on Sub/B
BIOS (8M)
KBC9022 (Reserve) (BR/SR)
page 24 page 30 page 33
page 33
PS2
Discrete TPM
Fan Control page 33
page 35
Int.KBD
RTC CKT.
page 11
Power On/Off CKT.

page 33
4
DC/DC Interface CKT.
Power Circuit DC/DC

page 25
page 38~51 Sub Board
LS-E901 USB2.0/B
page 31
www.vinafix.com Security Classification Compal Secret Data Compal Electronics, Inc.
4
LS-E892 Hall Sensor/B BLOCK DIAGRAMS

VRAM Config Table page 33
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
page 23 Custom 1.A
A B C D E
5 4 3 2 1
PJP101
AC-IN
APU Power Rail
20493mA +APU_CORE 55000mA +APU_CORE
+19V_VIN VDDCR_CPU @0.75-1.5V
+19VB 5416mA
PU301 PU801
+APU_CORE_NB 17000mA +APU_CORE_NB VDDCR_NB @0.75-1.2V
+17.4V_BATT
2843mA +APU_GFX 45000mA +APU_GFX Group C, S0 domain
PU901 VDDCR_GFX @0.75-1.2V
D D
PJP201 200mA +3VS

DC-IN VDD_33 @0.2A
1500mA +1.8VS
VDD_18 @1.5A
1500mA +0.95VS_GFX
VDDP_GFX @1.5A
8500mA +0.95VS 7000mA +0.95VS Group B, S0 domain
U4 VDDP @7.0A
+1.2V 6500mA 3000mA +1.2V
449mA VDDIO_MEM_S3 @3A
PU501
+0.6VS 1200mA 200mA +3VALW
VDD_33_S5 @0.2A
1753mA +1.8VALW 1013mA To VGA 500mA +1.8VALW
PU602 VDD_18_S5 @0.5A Group B, S3 domain
3213mA
+1.8VS 200mA +1.8VS
9300mA U3 VDDIO_AUDIO @0.2A
+0.95VALW 1700mA
514mA (+1.05VALW) 800mA +0.95VALW
PU601 VDDP_S5 @0.8A
212mA +0.775VALW 900mA +APU_CORE_FCH
PU902 VDDCR_FCH_S5 @0.9A
+RTC_APU_R 45mA +RTC_APU_R Group A, S5 domain
U102 VDDBT_RTC_G @0.045A
JRTC1
DDR4 SO-DIMM/MEM-DOWN
304mA +2.5V 400mA +2.5V
C PU502 +2.5V C
3500mA +1.2V
+1.2V
1200mA +0.6VS
+0.6VS
125mA
SATA Redriver
3500mA +3VS_SSD_NGFF
RM9
SSD
2311mA
PU401 13305mA +3VALW 1400mA +3V_LAN
RL2
LAN RTL8411
+3VLP R463
200mA +TP_VCC
KB9022 U13
Touch Pad
R212
1500mA +3VS_WLAN
U2606
WLAN
1500mA +LCDVDD
U8
Panel Logic
50mA +3VS_TPM
RW2
1mA +3VALW_TPM TPM R17M-P1-50/70
RW1
B B
U45
7285mA +3VS 200mA +3VS_CAM Camera
R110 GPU Power Rail
U2 290mA +1.2V_HDMI
3685mA 14000mA +5VALW 6500mA +5VS U1302 HDMI Redriver
PU401 2969mA +19VB 47000mA +VGA_CORE
PU1401 VDDC @47A
To VGA 10mA
250mA +3VALW_CC @1.2V
RS10
Type C
3000mA +5VALW_CC 379mA +19VB 8000mA +VDDCI
JPA8 PU1402 VDDCI+VDD_08 @8A
@0.8~0.9V
2000mA +USB3_VCCA
U25
USB3.0 2000mA
427mA +19VB 6000mA +1.35VSDGPU
2500mA PU1001 VMEMIO @2A
JUSB3
USB/B
2000mA +5VS_HDD
RO3
HDD 10mA +3VS 10mA +3VSDGPU VDD_GPIO33 @0.01A
UV7
2000mA +VCC_FAN1 +VCC_FAN2
RF1/RF7
FAN1/FAN2
1013mA +1.8VALW 1013mA +1.8VSDGPU VDD_18 @1A
1500mA +VDDA
JPA1 TSVDD @13mA
Audio UV8
1500mA +INVPWR_B+
L11 1000mA +5VS_DISP
Panel BackLight U73
HDMI Logic
A A
4000mA
To VGA +1.35VSDGPU
+VGA_CORE 2969mA VRAM x4pcs
+VDDCI/VDD_08 379mA
+1.35VSDGPU 427mA

POWER MAP
Custom 1.A
5 4 3 2 1
5 4 3 2 1
Bristol/Stoney Platform Power Sequence
AC-IN G3 --> S0 S0 --> S3 S3 --> S0

S0 --> S5
+3VLP +3VLP
ACIN 14.82us ACIN
D
EC_ON 227us EC_ON D
+5VALW 3.348ms, Tr = 637us +5VALW

160ms
ON/OFFBTN# 4.32us ON/OFFBTN#
3V_EN 91ms 8.532s 3V_EN
+3VALW 1.033ms, Tr = 670us Tf = 19.35ms +3VALW
+0.775VALW 1.108ms, Tr = 364us Tf = 9.193ms +0.775VALW
0.95_1.8VALW_PWREN 91ms 8.542s 0.95_1.8VALW_PWREN
+1.8VALW 2.385ms, Tr = 691us Tf = 3.951ms +1.8VALW
+0.95VALW 841us, Tr = 382us Tf = 14.24mss +0.95VALW
100ms
PBTN_OUT# 7ms 9.041s PBTN_OUT#
EC_RSMRST# 114ms 9.042s EC_RSMRST#
SLP_S5# 120us SLP_S5#
SLP_S3# 120us SLP_S3#
SYSON 120ms 61ms SYSON
+1.2V 807us, Tr = 239us Tf = 1.135ms +1.2V
+2.5V 1.456ms, Tr = 1.025ms Tf = 11.64ms +2.5V
C
SUSP# 20ms 57.1ms 14.88ms 53.3ms SUSP# C
+5VS 770us, Tr = 616us Tf = 13.95ms 733us, Tr = 575us Tf = 14.83ms +5VS

+3VS 823us, Tr = 599us Tf = 21.44ms 789us, Tr = 551us Tf = 23.94ms +3VS
+1.8VS 290us, Tr = 193us Tf = 8.428ms 282us, Tr = 174us Tf = 8.909ms +1.8VS
+0.6VS 10.14us, Tr = 9.399us Tf = 662us 8.25us, Tr = 6.9us Tf = 677us +0.6VS
KBRST# 20ms 57.1ms 19.98ms 53.27ms KBRST#
0.95VS_PWR_EN# 19.97ms 58.11ms 20.22ms 53.3ms 0.95VS_PWR_EN#
+0.95VS 317us, Tr = 146us 139us, Tf = 1.419ms 307us, Tr = 138us 133us, Tf = 955us +0.95VS
VR_ON 20.2ms 88.45ms 21.37ms 83.5ms VR_ON
+APU_CORE 1.089ms, Tr = 293us Tf = 4.119ms 1.098ms, Tr = 301us Tf = 5.572ms +APU_CORE
+APU_CORE_NB 1.103, Tr = 320us Tf = 817us 1.083, Tr = 300us Tf = 698us +APU_CORE_NB
+APU_GFX 1.112ms, Tr = 318us Tf = 807us 1.108ms, Tr = 306us Tf = 803us +APU_GFX
VGATE 1.254ms 1.249ms VGATE
SYS_PWRGD_EC 39.81ms 28ms 39.61ms 23.17ms SYS_PWRGD_EC
APU_PWROK 14.61ms 1.418ms 14.6ms 1.416ms APU_PWROK
LPC_RST# 13.38ms 2.06ms 13.4ms 2.072ms LPC_RST#
B APU_PCIE_RST# 1.005ms 108us 1.004ms 97us APU_PCIE_RST# B
APU_RST# 6.709ms 13.51ns 6.708ms 36.63ns APU_RST#
VGA Sequence VGA Sequence

PE_GPIO1 228ms 3.145ms 113.9ms 3.001ms PE_GPIO1
VGA_ON 1.399ms 6.158ms 1.404ms 6.039ms VGA_ON
+3VSDGPU 2.769ms, Tr = 1.598ms Tf = 754us 2.782ms, Tr = 1.598ms Tf = 685us +3VSDGPU
+1.8VSDGPU 3.553ms, Tr = 917us Tf = 3.864ms 3.568ms, Tr = 918us Tf = 3.659ms +1.8VSDGPU
VGA_ON_B 6.571ms 10.6us 6.545ms 13.21us VGA_ON_B
+VGA_CORE 5.880ms, Tr = 37.32us Tf = 5.215ms 5.840ms, Tr = 37.84us Tf = 5.215ms +VGA_CORE
+VDDCI 5.943ms, Tr = 35.7us Tf = 16.42ms 5.932ms, Tr = 35.6us Tf = 16.42ms +VDDCI
DGPU_PWROK 5.976ms 395ns 5.976ms 390.7ns DGPU_PWROK
+1.35VSDGPU Tr = 325us Tf = 8.199ms Tr = 257us Tf = 9.667ms +1.35VSDGPU
PE_GPIO0 206ms 16.7ns 197.2ms 17.79ns PE_GPIO0
PLT_RST_VGA# 1.008ns 6.871ns 7.374ns 8.908ns PLT_RST_VGA#
A A

POWER SEQUENCE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
Custom 1.A
5 4 3 2 1
A B C D E
Voltage Rails BOARD ID Table Board ID / SKU ID Table for AD channel

Board ID PCB Revision
Power Plane Description S0 S3 S5
0 C5V08 EVT
+19V_VIN Adapter power supply (19V) ON ON ON
ON ON ON
1 C5V08 DVT
+19VB AC or battery power rail for power circuit.
+APU_CORE ON OFF OFF
2 C5V08 PVT
Core voltage for APU
+APU_CORE_NB ON OFF OFF
3 C5V08 MP
Voltage for On-die VGA of APU
ON OFF OFF
4 D5PR8 DVT
+APU_CORE_GFX Voltage for GFX
1 5 D5PR8 PVT 1
+APU_CORE_FCH Fusion Controller Hub Power Supply ON ON ON
ON ON OFF
6 D5PR8 MP
+0.95VALW 0.95V always on power rail
ON OFF OFF
7 D5PR8_PVT_32P
+0.95VS 0.95V switched power rail
ON ON OFF
8 D5PR8_MP_32P
+1.8VALW 1.8V always on power rail
+1.8VS 1.8V switched power rail ON OFF OFF
+2.5V 2.5V power rail for APU and DDR ON ON OFF

ZZZ ZZZ
+1.2V 1.2V power rail for APU and DDR ON ON OFF
+0.6VS 0.6V switched power rail for DDR terminator ON OFF OFF
+0.775VALW 0.775V always on power rail ON ON OFF

PCB PCB
+3VALW 3.3V always on power rail ON ON OFF DA8001C0010 DAZ21800201
PCB 218 LA-E903P REV1 MB 2 PCB C5V08 LA-E903P LS-E901P/E892P
+3VS 3.3V switched power rail ON OFF OFF @
+5VALW 5V always on power rail ON ON AC:ON

DC:OFF
+5VS 5V switched power rail ON OFF OFF BOM Structure Table
+RTC_APU RTC power ON ON ON BOM Structure BTO Item
+3VSDGPU VGA power ON OFF OFF @ Unpop
+1.8VSDGPU VGA power ON OFF OFF @EMC@ EMI/ESD Unpop
+VDDCI VGA power ON OFF OFF EMC@ EMI/ESD pop
2
+VGA_CORE VGA power ON OFF OFF 45@ HDMI Royalty 2
CONN@ ME Connector
JP@ Jump
RS@ R-Short
TP@ Test Point
APU SMBus/I2C Address Table TPM@ TPM Pop
Address [7:0] POWER SEQUENCE
Master Device Address[7:1] PCIE@ PCIE SSD Device
Write Read
SATA@ SATA SSD Device G-A +RTCBATT
I2C Port 0 T1@ Bristol Pop EC_ON

(+1.8VS) T3@ Stoney Pop +5VALW
GS@ G-Sensor Circuits 3V_EN

I2C Port 1 G-Sensor 0001 1000b 0011 0000b 0011 0001b +3VALW/+0.775VALW
(+1.8VS) (Reserver) 18h 30h 31h LDO@ RTL8411 LDO mode G-B
SWR@ RTL8411 Switching mode 0.95_1.8VALW_PWREN
2D@ For 2 SO-DIMM use +1.8VALW/+0.95VALW

I2C Port 2
(+3VS) PAR@ SATA Redriver PARADE solution S5_MUX_CTRL
TI@ SATA Redriver TI solution +APU_CORE_FCH

0101 0000b 1010 0000b 1010 0001b SYSON
JDIMM1 50h EVT@ Only use on EVT
SBMus Port 0 A0h A1h G-C
+1.2V/+2.5V
(+3VS) CHG@ USB Charger
3
NCHG@ Non-USB Charger SUSP# 3
0101 0001b 1010 0010b 1010 0011b
JDIMM2 51h A2h A3h +5VS/+3VS/+1.8VS/+0.6VS
UMA@ UMA Config
CPU PN Refer p.6 0.95VS_PWR_EN#
PTP 0010 1100b 0101 1000b 0101 1001b +0.95VS
(Synaptics) 2Ch 58h 59h EA@ EA Series
I2C Port 3
(+3VALW) VX@ VX Series
VR_ON
PTP 0001 1111b 0011 1110b 0011 1111b DIS@ VGA Circuits Pop
+APU_CORE
(ELAN) 15h 3Eh 3Fh V2G_S@ VRAM use SAMSUNG G-D
+APU_CORE_NB
V2G_H@ VRAM use HYNIX
+APU_GFX
SMBus Port 1
(+3VALW) V2G_M@ VRAM use MICRON
GPU PN Refer p.23
RX540@ R17M-P1-50 GPU
VGA POWER SEQUENCE
RX550@ R17M-P1-70 GPU
RX560@ R17M-G1-70 GPU PE_GPIO1/VGA_ON
EC SMBus Address Table +3VSDGPU
+1.8VSDGPU
0000 1011b 0001 0110b 0001 0111b
Smart Battery 0Bh 16h 17h VGA_ON_B
SMBus Port 1
(+3VALW) +VGA_CORE
Charger IC 0000 1001b 0001 0010b 0001 0011b +VDDCI
4 (BQ24735) 09h 12h 13h 4
DGPU_PWROK
+1.35VSDGPU
APU Temp. 0100 1100b 1001 1000b 1001 1001b
SMBus Port 2 (TSI) 4Ch 98h 99h PE_GPIO0
(+3VS)
0100 0001b 1000 0010b 1000 0011b
GPU Temp. 41h 82h 83h Security Classification Compal Secret Data Compal Electronics, Inc.
NOTES LIST
Custom 1.A
A B C D E
5 4 3 2 1
UAPU1B @
PCIE
U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_ATX_DRX_P0 C19 1 2 .1U_0402_16V7K

<28> PCIE_ARX_DTX_P0 PCIE_ATX_DRX_N0 PCIE_ATX_C_DRX_P0 <28>
U9 P_GPP_RXN[0] LAN + CR P_GPP_TXN[0] R2 C20 1 2 .1U_0402_16V7K
<28> PCIE_ARX_DTX_N0 PCIE_ATX_C_DRX_N0 <28>
D T6 P_GPP_RXP[1] P_GPP_TXP[1] R4 PCIE_ATX_DRX_P1 C17 1 2 .1U_0402_16V7K D
T5 P_GPP_RXN[1] WLAN P_GPP_TXN[1] R3 C18 1 2 .1U_0402_16V7K
T9 P_GPP_RXP[2] P_GPP_TXP[2] N1 PCIE_ATX_DRX_P2 C2702 1 2 .1U_0402_16V7K
T8 P_GPP_RXN[2] P_GPP_TXN[2] N2 C2701 1 2 .1U_0402_16V7K
PCIE SSD
P7 P_GPP_RXP[3] P_GPP_TXP[3] N4 PCIE_ATX_DRX_P3 C2704 1 2 .1U_0402_16V7K
P6 P_GPP_RXN[3] P_GPP_TXN[3] N3 C2703 1 2 .1U_0402_16V7K
R542 1 2 196_0402_1% P_ZVDDP U7 P_ZVDDP P_ZVSS/P_RX_ZVDDP U6 P_ZVSS R541 1 2 196_0402_1%
+0.95VS
P10 P_GFX_RXP[0] P_GFX_TXP[0] M2

<15> PEG_GTX_C_HRX_P0 PEG_HTX_C_GRX_P0 <15>
P9 P_GFX_RXN[0] P_GFX_TXN[0] M1
<15> PEG_GTX_C_HRX_N0 PEG_HTX_C_GRX_N0 <15>
N6 P_GFX_RXP[1] P_GFX_TXP[1] L1
N5 P_GFX_RXN[1] P_GFX_TXN[1] L2
N9 P_GFX_RXP[2] P_GFX_TXP[2] L4
N8 P_GFX_RXN[2] P_GFX_TXN[2] L3
L7 P_GFX_RXP[3] P_GFX_TXP[3] J1
L6 P_GFX_RXN[3] P_GFX_TXN[3] J2
L10 P_GFX_RXP[4] P_GFX_TXP[4] J4
L9 P_GFX_RXN[4] P_GFX_TXN[4] J3
K6 P_GFX_RXP[5] P_GFX_TXP[5] H2
C K5 P_GFX_RXN[5] P_GFX_TXN[5] H1 C
K9 P_GFX_RXP[6] P_GFX_TXP[6] G1
K8 P_GFX_RXN[6] P_GFX_TXN[6] G2
J7 P_GFX_RXP[7] P_GFX_TXP[7] G4
J6 P_GFX_RXN[7] P_GFX_TXN[7] G3
FP4 REV 0.93
FP4_BGA968
CPU PN Table CPU PN Table

CPU Platform PN R1(ROH) PN R3(ABO!) CPU Platform PN R1(ROH) PN R3(ABO!)
UAPU1 BR_A10@ UAPU1 BR_A10R3@ UAPU1 BR_35W A10@
S IC A10-9620P AM962PADY44AB 2.5G BGA 968P AP S IC A10-9620P AM962PADY44AB 2.5G ABO! S IC A10-9630P AM963PAEY44AB 2.6G BGA968
SA0000AK010 SA0000AK020 SA0000AOQ00
B UAPU1 BR_A12@ UAPU1 BR_A12R3@ UAPU1 BR_35W A12@ B
Bristol Bristol
15W 35W
S IC A12-9720P AM972PADY44AB 2.7G BGA 968P APU S IC A12-9720P AM972PADY44AB 2.7G ABO! S IC A12-9730P AM973PAEY44AB 2.8G BGA968
SA0000AJY10 SA0000AJY20 SA0000AOR00
UAPU1 BR_FX@ UAPU1 BR_FXR3@ UAPU1 BR_35W FX@
S IC FX-9800P FM980PADY44AB 2.7G BGA 968P APU S IC FX-9800P FM980PADY44AB 2.7G ABO! S IC FX-9830P FM983PAEY44AB 3G BGA 968P
SA00009LB00 SA00009LB40 SA0000AOS00
CPU PN Table
CPU Platform PN R1(ROH) PN R3(ABO!)
UAPU1 SR_A6@ UAPU1 SR_A6R3@

A A
Stoney S IC A6-9220 AM9220AVY23AC 2.5G BGA 968P S IC A6-9220 AM9220AVY23AC 2.5G BGA ABO!
SA0000ALL00 SA0000ALL10 Security Classification Compal Secret Data Compal Electronics, Inc.
FP4 PCIE
Custom 1.A
5 4 3 2 1
5 4 3 2 1
UAPU1A @ UAPU1I @
MEMORY A MEMORY B
<13> DDRA_SMA[13..0] DDRA_SMA0 AE28 H17 DDRA_SDQ0 DDRA_SDQ[63..0] <13> <14> DDRB_SMA[13..0] DDRB_SMA0 AG31 A25 DDRB_SDQ0 DDRB_SDQ[63..0] <14>
MA_ADD[0] MA_DATA[0] MB_ADD[0] MB_DATA[0]
DDRA_SMA1 Y27 J17 DDRA_SDQ1 DDRB_SMA1 AC30 C25 DDRB_SDQ1
DDRA_SMA2 Y29 MA_ADD[2] MA_DATA[2] F20 DDRA_SDQ2 DDRB_SMA2 AC31 MB_ADD[2] MB_DATA[2] C27 DDRB_SDQ2
D DDRA_SMA3 DDRA_SDQ3 DDRB_SMA3 DDRB_SDQ3 D
Y26 MA_ADD[3] MA_DATA[3] H20 AB32 MB_ADD[3] MB_DATA[3] D27
DDRA_SMA4 W28 E17 DDRA_SDQ4 DDRB_SMA4 AA32 B24 DDRB_SDQ4
DDRA_SMA5 W29 F17 DDRA_SDQ5 DDRB_SMA5 AA33 B25 DDRB_SDQ5
DDRA_SMA6 W26 K18 DDRA_SDQ6 DDRB_SMA6 AA31 B27 DDRB_SDQ6
DDRA_SMA7 U29 MA_ADD[7] MA_DATA[7] E20 DDRA_SDQ7 DDRB_SMA7 Y33 MB_ADD[7] MB_DATA[7] A27 DDRB_SDQ7
DDRA_SMA8 W25 MA_ADD[8]
DDRB_SMA8 AA30 MB_ADD[8]
DDRA_SMA9 U26 A21 DDRA_SDQ8 DDRB_SMA9 W32 A29 DDRB_SDQ8
DDRA_SMA10 AG29 C21 DDRA_SDQ9 DDRB_SMA10 AG32 C29 DDRB_SDQ9
DDRA_SMA11 U27 C23 DDRA_SDQ10 DDRB_SMA11 Y32 B32 DDRB_SDQ10
DDRA_SMA12 T28 MA_ADD[12] MA_DATA[11] D23 DDRA_SDQ11 DDRB_SMA12 W33 MB_ADD[12] MB_DATA[11] D32 DDRB_SDQ11
DDRA_SMA13 AK26 MA_ADD[13] MA_DATA[12] B20 DDRA_SDQ12 DDRB_SMA13 AL31 MB_ADD[13] MB_DATA[12] B28 DDRB_SDQ12
DDRA_BG1 T26 B21 DDRA_SDQ13 DDRB_BG1 W30 B29 DDRB_SDQ13
MA_ADD[14]/MA_BG[1] MA_DATA[13] MB_ADD[14]/MB_BG[1] MB_DATA[13]
<13> DDRA_BG1 MEM_MA_ACT# DDRA_SDQ14 <14> DDRB_BG1 MEM_MB_ACT# DDRB_SDQ14
T25 MA_ADD[15]/MA_ACT_L MA_DATA[14] B23 V32 MB_ADD[15]/MB_ACT_L MB_DATA[14] A31
<13> MEM_MA_ACT# DDRA_SDQ15 <14> MEM_MB_ACT# DDRB_SDQ15
MA_DATA[15] A23 MB_DATA[15] C31
G22 DDRA_SDQ16 E30 DDRB_SDQ16

MA_DATA[16] MB_DATA[16]
DDRA_SBS0# AG26 H22 DDRA_SDQ17 DDRB_SBS0# AH32 E31 DDRB_SDQ17
MA_BANK[0] MA_DATA[17] MB_BANK[0] MB_DATA[17]
<13> DDRA_SBS0# DDRA_SBS1# DDRA_SDQ18 <14> DDRB_SBS0# DDRB_SBS1# DDRB_SDQ18
AG27 MA_BANK[1] MA_DATA[18] E25 AG33 MB_BANK[1] MB_DATA[18] G33
<13> DDRA_SBS1# DDRA_BG0 DDRA_SDQ19 <14> DDRB_SBS1# DDRB_BG0 DDRB_SDQ19
T29 MA_BANK[2]/MA_BG[0] MA_DATA[19] G25 W31 MB_BANK[2]/MB_BG[0] MB_DATA[19] G32
<13> DDRA_BG0 DDRA_SDQ20 <14> DDRB_BG0 DDRB_SDQ20
MA_DATA[20] J20 MB_DATA[20] C33
<13> DDRA_SDM[7..0] DDRA_SDM0 E19 E22 DDRA_SDQ21 <14> DDRB_SDM[7..0] DDRB_SDM0 D25 D33 DDRB_SDQ21
MA_DM[0] MA_DATA[21] MB_DM[0] MB_DATA[21]
DDRA_SDM1 D21 H23 DDRA_SDQ22 DDRB_SDM1 D29 G30 DDRB_SDQ22
DDRA_SDM2 K21 J23 DDRA_SDQ23 DDRB_SDM2 E33 G31 DDRB_SDQ23
DDRA_SDM3 F29 DDRB_SDM3 J33
MA_DM[3] MB_DM[3]
DDRA_SDM4 AP28 F26 DDRA_SDQ24 DDRB_SDM4 AR30 J30 DDRB_SDQ24
DDRA_SDM5 AV26 E27 DDRA_SDQ25 DDRB_SDM5 AW30 J31 DDRB_SDQ25
DDRA_SDM6 AR22 J26 DDRA_SDQ26 DDRB_SDM6 BC30 L33 DDRB_SDQ26
DDRA_SDM7 BC22 J27 DDRA_SDQ27 DDRB_SDM7 BC26 L32 DDRB_SDQ27
K29 H25 DDRA_SDQ28 N33 H32 DDRB_SDQ28
E26 DDRA_SDQ29 H33 DDRB_SDQ29
DDRA_SDQS0 H19 G28 DDRA_SDQ30 DDRB_SDQS0 B26 L30 DDRB_SDQ30
MA_DQS_H[0] MA_DATA[30] MB_DQS_H[0] MB_DATA[30]
<13> DDRA_SDQS0 DDRA_SDQS0# DDRA_SDQ31 <14> DDRB_SDQS0 DDRB_SDQS0# DDRB_SDQ31
G19 MA_DQS_L[0] MA_DATA[31] G29 A26 MB_DQS_L[0] MB_DATA[31] L31
<13> DDRA_SDQS0# DDRA_SDQS1 <14> DDRB_SDQS0# DDRB_SDQS1
B22 MA_DQS_H[1] B30 MB_DQS_H[1]
A22 MA_DQS_L[1] MA_DATA[32] AN26 A30 MB_DQS_L[1] MB_DATA[32] AN31
<13> DDRA_SDQS1# DDRA_SDQS2 DDRA_SDQ33 <14> DDRB_SDQS1# DDRB_SDQS2 DDRB_SDQ33
F23 MA_DQS_H[2] MA_DATA[33] AP29 F32 MB_DQS_H[2] MB_DATA[33] AP32
C <13> DDRA_SDQS2 DDRA_SDQS2# E23 AR26 DDRA_SDQ34 <14> DDRB_SDQS2 DDRB_SDQS2# E32 AT32 DDRB_SDQ34 C
MA_DQS_L[2] MA_DATA[34] MB_DQS_L[2] MB_DATA[34]
G27 MA_DQS_H[3] MA_DATA[35] AP24 K32 MB_DQS_H[3] MB_DATA[35] AU32
F27 MA_DQS_L[3] MA_DATA[36] AN29 J32 MB_DQS_L[3] MB_DATA[36] AN33
AP25 MA_DQS_H[4] MA_DATA[37] AN27 AR32 MB_DQS_H[4] MB_DATA[37] AN32
AP26 MA_DQS_L[4] MA_DATA[38] AR29 AR33 MB_DQS_L[4] MB_DATA[38] AR31
<13> DDRA_SDQS4# DDRA_SDQS5 AW27 AR27 DDRA_SDQ39 <14> DDRB_SDQS4# DDRB_SDQS5 AW32 AT33 DDRB_SDQ39
MA_DQS_H[5] MA_DATA[39] MB_DQS_H[5] MB_DATA[39]
<13> DDRA_SDQS5 DDRA_SDQS5# <14> DDRB_SDQS5 DDRB_SDQS5#
AV27 MA_DQS_L[5] AW33 MB_DQS_L[5]
AV22 MA_DQS_H[6] MA_DATA[40] AU26 BA29 MB_DQS_H[6] MB_DATA[40] AU30
<13> DDRA_SDQS6 DDRA_SDQS6# AU22 AV29 DDRA_SDQ41 <14> DDRB_SDQS6 DDRB_SDQS6# AY29 AV32 DDRB_SDQ41
BA21 MA_DQS_H[7] MA_DATA[42] AU25 BA25 MB_DQS_H[7] MB_DATA[42] BA33
AY21 MA_DQS_L[7] MA_DATA[43] AW25 AY25 MB_DQS_L[7] MB_DATA[43] AY32
<13> DDRA_SDQS7# DDRA_SDQ44 <14> DDRB_SDQS7# DDRB_SDQ44
L27 MA_DQS_H[8] MA_DATA[44] AU29 P32 MB_DQS_H[8] MB_DATA[44] AU33
L26 AU28 DDRA_SDQ45 N32 AU31 DDRB_SDQ45
AW26 DDRA_SDQ46 AW31 DDRB_SDQ46
DDRA_CLK0 AE25 MA_CLK_H[0] MA_DATA[47] AT25 DDRA_SDQ47 DDRB_CLK0 AE33 MB_CLK_H[0] MB_DATA[47] AY33 DDRB_SDQ47
<13> DDRA_CLK0 DDRA_CLK0# <14> DDRB_CLK0 DDRB_CLK0#
AE26 MA_CLK_L[0] AE32 MB_CLK_L[0]
<13> DDRA_CLK0# DDRA_CLK1 AD26 AV23 DDRA_SDQ48 <14> DDRB_CLK0# DDRB_CLK1 AE30 BC31 DDRB_SDQ48
MA_CLK_H[1] MA_DATA[48] MB_CLK_H[1] MB_DATA[48]
<13> DDRA_CLK1 DDRA_CLK1# AD27 AW23 DDRA_SDQ49 <14> DDRB_CLK1 DDRB_CLK1# AE31 BB30 DDRB_SDQ49
MA_CLK_L[1] MA_DATA[49] MB_CLK_L[1] MB_DATA[49]
<13> DDRA_CLK1# DDRA_SDQ50 <14> DDRB_CLK1# DDRB_SDQ50
AB28 MA_CLK_H[2] MA_DATA[50] AV20 AD32 MB_CLK_H[2] MB_DATA[50] BB28
AB29 MA_CLK_L[2] MA_DATA[51] AW20 DDRA_SDQ51 AD33 MB_CLK_L[2] MB_DATA[51] AY27 DDRB_SDQ51
AB25 AR23 DDRA_SDQ52 AC33 BB32 DDRB_SDQ52
MA_CLK_H[3] MA_DATA[52] MB_CLK_H[3] MB_DATA[52]
AB26 AT23 DDRA_SDQ53 AC32 BA31 DDRB_SDQ53
MA_CLK_L[3] MA_DATA[53] MB_CLK_L[3] MB_DATA[53]
AR20 DDRA_SDQ54 BC29 DDRB_SDQ54
MEM_MA_RST# N29 AT20 DDRA_SDQ55 MEM_MB_RST# T33 BB29 DDRB_SDQ55
MA_RESET_L MA_DATA[55] MB_RESET_L MB_DATA[55]
<13> MEM_MA_RST# MEM_MA_EVENT# AE29 <14> MEM_MB_RST# MEM_MB_EVENT#AG30
MA_EVENT_L MB_EVENT_L
<13> MEM_MA_EVENT# DDRA_SDQ56 <14> MEM_MB_EVENT# DDRB_SDQ56
MA_DATA[56] BB23 MB_DATA[56] BB27
DDRA_CKE0 P27 MA_CKE0 BB22 DDRA_SDQ57 DDRB_CKE0 U32 MB_CKE0 BB26 DDRB_SDQ57
<13> DDRA_CKE0 DDRA_CKE1 DDRA_SDQ58 <14> DDRB_CKE0 DDRB_CKE1 DDRB_SDQ58
P29 MA_CKE1 MA_DATA[58] BB20 U33 MB_CKE1 MB_DATA[58] BB24
<13> DDRA_CKE1 DDRA_SDQ59 <14> DDRB_CKE1 DDRB_SDQ59
MA_DATA[59] AY19 MB_DATA[59] AY23
BA23 DDRA_SDQ60 BA27 DDRB_SDQ60
BC23 DDRA_SDQ61 BC27 DDRB_SDQ61
DDRA_ODT0 AK27 BC21 DDRA_SDQ62 DDRB_ODT0 AL30 BC25 DDRB_SDQ62
MA0_ODT[0] MA_DATA[62] MB0_ODT[0] MB_DATA[62]
<13> DDRA_ODT0 DDRA_ODT1 DDRA_SDQ63 <14> DDRB_ODT0 DDRB_ODT1 DDRB_SDQ63
AL26 MA0_ODT[1] MA_DATA[63] BB21 AM32 MB0_ODT[1] MB_DATA[63] BB25
<13> DDRA_ODT1 <14> DDRB_ODT1
AH25 MA1_ODT[0] AJ32 MB1_ODT[0]
AL25 MA1_ODT[1] MA_CHECK[0] K26 AM33 MB1_ODT[1] MB_CHECK[0] N30
B MA_CHECK[1] K28 MB_CHECK[1] N31 B
DDRA_SCS0# AH26 N26 DDRB_SCS0# AJ33 R33
MA0_CS_L[0] MA_CHECK[2] MB0_CS_L[0] MB_CHECK[2]
<13> DDRA_SCS0# DDRA_SCS1# <14> DDRB_SCS0# DDRB_SCS1#
AL29 MA0_CS_L[1] MA_CHECK[3] N28 AL32 MB0_CS_L[1] MB_CHECK[3] R32
<13> DDRA_SCS1# <14> DDRB_SCS1#
AH29 MA1_CS_L[0] MA_CHECK[4] J29 AJ30 MB1_CS_L[0] MB_CHECK[4] M32
AL28 MA1_CS_L[1] MA_CHECK[5] K25 AL33 MB1_CS_L[1] MB_CHECK[5] M33
MA_CHECK[6] L29 MB_CHECK[6] R30
MA_CHECK[7] N25 MB_CHECK[7] R31
DDRA_SMA16 AG24 DDRB_SMA16 AH33
MA_RAS_L/MA_RAS_L_ADD[16] MB_RAS_L/MB_RAS_L_ADD[16]
<13> DDRA_SMA16 DDRA_SMA15 <14> DDRB_SMA16 DDRB_SMA15
AK29 MA_CAS_L/MA_CAS_L_ADD[15] AK32 MB_CAS_L/MB_CAS_L_ADD[15]
<13> DDRA_SMA15 DDRA_SMA14 <14> DDRB_SMA15 DDRB_SMA14
AH28 MA_WE_L/MA_WE_L_ADD[14] AJ31 MB_WE_L/MB_WE_L_ADD[14]
<13> DDRA_SMA14 <14> DDRB_SMA14
R74 R75
39.2_0402_1% 39.2_0402_1%
MA_VREFDQ B19 AD29 MEM_MA_ZVDDIO 1 T1@ 2 MB_VREFDQ A19 MEM_MB_ZVDDIO
T80 MA_VREFDQ MA_ZVDDIO_MEM_S T45 MB_VREFDQ MB_ZVDDIO_MEM_S AF32 1 2
M_VREF +1.2V +1.2V
T4957 T32 M_VREF
FP4 REV 0.93 FP4 REV 0.93
FP4_BGA968 FP4_BGA968
+1.2V
R3979 2D@
1K_0402_5%
2 1 MEM_MA_EVENT#
R3994
1K_0402_5%
2 1 MEM_MB_EVENT#
A A

FP4 MEMORY INTERFACE
Custom 1.A
5 4 3 2 1
A B C D E
+1.8VS UAPU1C @
@ RP14 DISPLAY/SVI2/JTAG/TEST
8 1 APU_SVT_R
7 2 APU_SVC
6 3 APU_SVD B6 DP2_TXP[0] DP_ZVSS A9 DP_ZVSS R400 1 2 2K_0402_1%
5 4 A6 DP2_TXN[0] DP_AUX_ZVSS B9 DP_AUX_ZVSS R401 1 2 150_0402_1% +1.8VALW +1.8VALW
1 DP_BLON G5 ENBKL_R 1
1K_0804_8P4R_5% D7 DP2_TXP[1] DP_DIGON G6 ENVDD_R
5
@ RP17 C7 DP2_TXN[1] DP_VARY_BL F11 INVTPW M_R U64 U2611
8 1 GFX_SVC 1 1
P
7 2 GFX_SVD A7 NC 4 NC 4
DP2_TXP[2]
Y ENVDD <27> Y INVTPW M <27>
6 3 GFX_SVT_R B7 DP2_TXN[2] DP2_AUXP H9 ENVDD_R 2 INVTPW M_R 2
A A
G
5 4 DP2_AUXN G9 @
D9 DP2_TXP[3] DP2_HPD E9 NL17SZ07DFT2G_SC70-5 NL17SZ07DFT2G_SC70-5
3
1K_0804_8P4R_5% C9 DP2_TXN[3] SA00004BV00 SA00004BV00
DP1_AUXP F7
HDMI_SCLK <26>
A2 DP1_TXP[0] DP1_AUXN E7
APU_PROCHOT# <26> APU_DP1_P0 HDMI_SDATA <26> +1.8VALW
A3 DP1_TXN[0] DP1_HPD F5
APU_RST# <26> APU_DP1_N0 HDMI_HPD <26> ENVDD_R R683
APU_PW ROK
Close to APU 1 RS@ 2 0_0402_5% ENVDD
B4 DP1_TXP[1] DP0_AUXP F8
<26> APU_DP1_P1
5
A4 E8 EDP_AUXP <27> U2610
1 1 1 <26> APU_DP1_N1 DP1_TXN[1] DP0_AUXN
EMC@ EMC@ @EMC@ DP0_HPD G8 EDP_AUXN <27> 1
P
EDP_HPD <27> NC
C2647 C2648 C2649 D5 DP1_TXP[2] 4
<26> APU_DP1_P2 ENBKL_R 2 Y ENBKL <24>
33P_0402_50V8J 33P_0402_50V8J .1U_0402_16V7K C5 DP1_TXN[2] RSVD_1 K24
<26> APU_DP1_N2 A
G
2 2 2 E15
TEMPIN0
A5 DP1_TXP[3] TEMPIN1 E14 NL17SZ07DFT2G_SC70-5 +3VS
<26> APU_DP1_P3
3
B5 DP1_TXN[3] TEMPIN2 E12 SA00004BV00
<26> APU_DP1_N3 ENVDD_R
TEMPINRETURN F14 ENVDD 1 @ 2 1 2
E2 DP0_TXP[0] TEST410 AK24 APU_TEST410 TP@ R1160 R3847
<27> EDP_TXP0 APU_TEST411 T32
E1 DP0_TXN[0] TEST411 AL24 T33 TP@ 4.7K_0402_5% 100K_0402_5%
<27> EDP_TXN0 APU_TEST4 INVTPW M_R 1
TEST4 P24 T34 TP@ INVTPW M 1 2 @ 2
E3 DP0_TXP[1] TEST5 N24 APU_TEST5 TP@ R1161 R3835
<27> EDP_TXP1 T35
E4 DP0_TXN[1] TEST6 AN24 4.7K_0402_5% 100K_0402_5%
<27> EDP_TXN1 ENBKL_R
TEST9 AB8 ENBKL 1 2 1 2
D1 DP0_TXP[2] TEST10 Y9 R3905 R3906
<27> EDP_TXP2 APU_TEST14
2 D2 DP0_TXN[2] TEST14 B10 @ RP30 4.7K_0402_5% 100K_0402_5% 2
<27> EDP_TXN2 APU_TEST15 APU_TEST11
TEST15 D11 T40 TP@ 8 1
C1 DP0_TXP[3] TEST16 A10 APU_TEST16 APU_TEST17 7 2
<27> EDP_TXP3 APU_TEST17 APU_TEST16
B1 DP0_TXN[3] TEST17 C11 6 3
<27> EDP_TXN3 APU_TEST11 APU_TEST14
TEST11 B11 5 4
APU_SVT_R C15 SVT0 TEST18 A14 APU_TEST18
<44> APU_SVT_R APU_SVC_R APU_TEST19
R2612 1 2 0_0402_5% D17 SVC0 TEST19 B14 1K_0804_8P4R_5%
<44> APU_SVC APU_SVD_R
R2613 1 2 0_0402_5% D19 SVD0
<44> APU_SVD
GFX_SVT_R B15 A13 APU_TEST28_H
<45> GFX_SVT_R GFX_SVC_R
SVT1 TEST28_H
APU_TEST28_L T43 TP@ +1.8VS
R2614 1 T1@ 2 0_0402_5% B16 SVC1 TEST28_L B13 T42 TP@
<45> GFX_SVC GFX_SVD_R APU_TEST31
R2615 1 T1@ 2 0_0402_5% A18 SVD1 TEST31 P26 T41 TP@
<45> GFX_SVD APU_TEST36 APU_TEST37 APU_TEST36
DP_STEREOSYNC/TEST36 E11 1 @ 2 1 2 +1.8VS
APU_SIC B18 SIC TEST37 A17 APU_TEST37 R117 R155
APU_SID C17 SID 1K_0402_5% 1K_0402_5%
1 @ 2
+1.8VS R80 1 2 300_0402_5% APU_RST# D15 RESET_L R118
+1.8VS R82 1 2 300_0402_5% APU_PW ROK C19 PWROK 1K_0402_5%
1 @ 2
<44,45> APU_PW ROK APU_PROCHOT# A15 PROCHOT_L R154
<16,24,44,45> APU_PROCHOT# APU_ALERT# B17 ALERT_L 1K_0402_5%
VDDCR_GFX_SENSE H11
APU_TDI APU_COREGFX_SEN_H <45>
H15 TDI VDDCR_NB_SENSE J12
APU_TDO APU_CORENB_SEN_H <44>
H14 VDDCR_CPU_SENSE G12
+1.8VS
RP25
APU_TCK
APU_TMS
D13
G15
TDO
TCK
TMS
VDDP_SENSE AY18
APU_CORE_SEN_H <44>
+1.8VS
HDT+
8 1 APU_PROCHOT# APU_TRST# J14 TRST_L VSS_SENSE H12 JHDT1 @
APU_SID APU_DBRDY APU_VSS_SEN_L <44,45> APU_TCK_R APU_TCK
7 2 C13 DBRDY 1 2 1 @ 2
6 3 APU_ALERT# APU_DBREQ# A11 1 2 R706 0_0402_5% +1.8VS
DBREQ_L
3 5 4 APU_SIC 3 4 APU_TMS_R 1 @ 2 APU_TMS RP28 3
3 4 R694 0_0402_5% APU_DBREQ# 1 8
1K_0804_8P4R_5% 5 6 APU_TDI_R 1 @ 2 APU_TDI APU_TDI 2 7
FP4 REV 0.93 5 6 R705 0_0402_5% APU_TMS 3 6
FP4_BGA968 7 8 APU_TDO_R 1 @ 2 APU_TDO APU_TCK 4 5
7 8 R704 0_0402_5%
APU_TRST# 1 2 APU_TRST#_R 9 10 APU_PW ROK_R 1 @ 2 APU_PW ROK 1K_0804_8P4R_5%
R671 33_0402_5% 9 10 R682 0_0402_5%
RP29 HDT_P11 11 12 APU_RST#_R 1 @ 2 APU_RST# +1.8VS
+1.8VS 1 8 11 12 R707 0_0402_5% RP27
2 7 HDT_P13 13 14 APU_DBRDY_R 1 @ 2 APU_DBRDY 1 8
3 6 13 14 R708 0_0402_5% APU_TRST# 2 7
4 5 HDT_P15 15 16 APU_DBREQ#_R 1 2 APU_DBREQ# APU_TEST19 3 6
15 16
5
R672 33_0402_5% APU_TEST18 4 5

+3VS 10K_0804_8P4R_5% 17 18 APU_TEST19
G
EC_SMB_CK2 3 4 APU_SIC 17 18 1K_0804_8P4R_5%

<16,24> EC_SMB_CK2 APU_TEST18 APU_TRST#
D
Q79A 19 20 1 2
19 20
2
1 2 EC_SMB_CK2 DMN63D8LDW _SOT363-6

R3969 2.2K_0402_5% C141
G
1 2 EC_SMB_DA2 EC_SMB_DA2 6 1 APU_SID 0.01U_0402_16V7K

<16,24> EC_SMB_DA2
D
R3970 2.2K_0402_5% Q79B SAMTE_ASP-136446-07-B

DMN63D8LDW _SOT363-6
VGS,on = 0.8~1.5V
www.vinafix.com Security Classification

Issued Date 2017/04/18
Compal Secret Data
Deciphered Date
2019/04/18 Title
Compal Electronics, Inc.
FP4 DISP/MISC/HDT
4
Custom 1.A
A B C D E
A B C D E
C912 1 2 150P_0402_50V8J Length<1.0"

C615 1 2 150P_0402_50V8J UAPU1D @
ACPI/SD/AZ/GPIO/RTC/I2C/UART/MISC
+3VALW
R602 1 2 33_0402_5%LPC_RST_A# BB12 LPC_RST_L SD0_WP/EGPIO101 BB2
<24,33> LPC_RST#
R907 1 2 33_0402_5%APU_PCIE_RST#_R AN7 PCIE_RST_L/EGPIO26 SD0_PWR_CTRL/AGPIO102 BB5
<15,28,29,30> APU_PCIE_RST#
SD0_CD/AGPIO25 BC2
EC_RSMRST# AE4 RSMRST_L SD0_CLK/EGPIO95 BB4
<24> EC_RSMRST#
AY5
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
SD0_CMD/EGPIO96
1 RX550@ 2
1 RX560@ 2
T1@ 2
VX@ 2
1 UMA@ 2
PBTN_OUT# AE1 PWR_BTN_L/AGPIO0
<24> PBTN_OUT# SYS_PW RGD_EC BC9 PWR_GOOD
<24> SYS_PW RGD_EC SYS_RST# AF2
R4001
R3999
R3892
R3953
R3978
SYS_RESET_L/AGPIO1
APU_PCIE_W AKE# AG2 WAKE_L/AGPIO2 SD0_DATA0/EGPIO97 BC3
1 SD0_DATA1/EGPIO98 BA3 1
1
SLP_S3# AK7 SLP_S3_L SD0_DATA2/EGPIO99 BC5 AGPIO5
<24> SLP_S3# SLP_S5# AH5 SLP_S5_L SD0_DATA3/EGPIO100 BA5 AGPIO7
<24> SLP_S5# PE_GPIO1
SD0_LED/EGPIO93 BB6 AGPIO10
PE_GPIO1 <25>
AGPIO10 AE8 S0A3_GPIO/AGPIO10 AGPIO12
AH8 S5_MUX_CTRL/EGPIO42 SCL0/I2C2_SCL/EGPIO113 BA15
APU_SMB_CLK0 AGPIO69
<25> S5_MUX_CTRL APU_SMB_DATA0 APU_SMB_CLK0 <13,14>
SDA0/I2C2_SDA/EGPIO114 AY17
APU_TEST0 APU_SMB_DATA0 <13,14> If no use, need Config Low
AH6
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
TEST0
1 RX540@ 2
T3@ 2
EA@ 2
1 DIS@ 2
APU_TEST1 AK8 TEST1/TMS SCL1/I2C3_SCL/AGPIO19 AG5
APU_I2C3_SCL
APU_TEST2 APU_I2C3_SCL <33>
AE3 TEST2 SDA1/I2C3_SDA/AGPIO20 AG4 APU_I2C3_SDA R4002 UMA@
APU_I2C3_SDA <33>
R936
R4002
R4000
R2624
R3952
KBRST# AY15 ESPI_RESET_L/KBRST_L/AGPIO129
<24> KBRST#
GATEA20 BC19 GA20IN/AGPIO126
<24> GATEA20
1
EC_SCI# AD7 LPC_PME_L/AGPIO22 AGPIO3 AL5 AGPIO3
<24> EC_SCI#
BB13 LPC_SMI_L/AGPIO86 AGPIO4 AL6
AGPIO5 AJ1 AGPIO5 10K_0402_5%
AG3 AC_PRES/USB_OC4_L/IR_RX0/AGPIO23 AGPIO6/LDT_RST AJ3 SD028100280
AD5 IR_TX0/USB_OC5_L/AGPIO13 AGPIO7/LDT_PWROK AH1 AGPIO7
AL8 IR_TX1/USB_OC6_L/AGPIO14 AGPIO8 AJ4 AGPIO8
AGPIO8 <30>
AN8 IR_RX1/AGPIO15 AGPIO9 AK5
AGPIO12 AE2 IR_LED_L/LLB_L/AGPIO12 VDDGFX_PD/AGPIO39 AD8 AGPIO5 AGPIO7 AGPIO10 AGPIO12 AGPIO69
LAN_CLKREQ# BC15 CLK_REQ0_L/SATA_IS0_L/SATA_ZP0_L/AGPIO92 AGPIO40 AG8 VDDGFX_PW RGD
<28> LAN_CLKREQ# W LAN_CLKREQ# VDDGFX_PW RGD <45>
<29> W LAN_CLKREQ#
BB17 CLK_REQ1_L/AGPIO115 AGPIO64 AW15 H RX550 RX560 BR VX UMA
DGPU_PW ROK BC17 CLK_REQ2_L/AGPIO116 AGPIO65 AU15
<47,48> DGPU_PW ROK SSD_CLKREQ#
<30> SSD_CLKREQ#
BB18 CLK_REQ3_L/SATA_IS1_L/SATA_ZP1_L/EGPIO131 L RX540 x SR EA DIS
PEG_CLKREQ# BB16 CLK_REQG_L/OSCIN/EGPIO132 AGPIO66/SHUTDOWN_L AT15 G_INT#_APU
<16> PEG_CLKREQ# USB_OC0# G_INT#_APU <30>
AH9 USB_OC0_L/TRST_L/AGPIO16 AGPIO68/SGPIO_CLK AU12
<31> USB_OC0#
AG1 USB_OC1_L/TDI/AGPIO17 AGPIO69/SGPIO_LOAD AT14 AGPIO69
AH2 USB_OC2_L/TCK/AGPIO18 AGPIO71/SGPIO_DATAOUT AR14 PE_GPIO0
PE_GPIO0 <15>
2 AL9 USB_OC3_L/TDO/AGPIO24 AGPIO72/SGPIO_DATAIN BC13 2
HDA_BITCLK AU6 BA17 APU_SPKR

<34> HDA_SDIN0
HDA_SDIN0
HDA_SDIN1
AR8
AP6
AZ_BITCLK/I2S_BCLK_MIC
AZ_SDIN0/I2S_DATA_MIC[0]
AZ_SDIN1/I2S_LR_PLAYBACK
SPKR/AGPIO91
BLINK/USB_OC7_L/AGPIO11 AN5 AGPIO11

APU_SPKR <34>
32.768KMHz CRYSTAL
HDA_SDIN2 AR5 AZ_SDIN2/I2S_DATA_MIC[1]
32K_X1
HDA_RST# AU9 AZ_RST_L/I2S_LR_MIC GENINT1_L/AGPIO89 BB14 HVB
1
HDA_SYNC AT9 AZ_SYNC/I2S_BCLK_PLAYBACK GENINT2_L/AGPIO90 BA19 TP_I2C_INT#_APU
HDA_SDOUT TP_I2C_INT#_APU <33>
AR7 AZ_SDOUT/I2S_DATA_PLAYBACK Y3
FANIN0/AGPIO84 BC18 32.768KHZ_12.5PF_Q13FC135000040
APU_I2C0_SCL BB10 I2C0_SCL/EGPIO145 FANOUT0/AGPIO85 BB19
2
APU_I2C0_SDA BB9 I2C0_SDA/EGPIO146 2 1 32K_X2
APU_I2C1_SCL BB7 I2C1_SCL/EGPIO147 UART0_CTS_L/EGPIO135 AY9 R914
<30> APU_I2C1_SCL APU_I2C1_SDA BC7 I2C1_SDA/EGPIO148 UART0_RXD/EGPIO136 AW8 20M_0402_5%
<30> APU_I2C1_SDA
UART0_RTS_L/EGPIO137 AV5 1 1
RTC_CLK AG7 RTCCLK UART0_TXD/EGPIO138 AV8
UART0_INTR/AGPIO139 AW9 C686 C682
18P_0402_50V8J 22P_0402_50V8J
32K_X1 AT1 X32K_X1 UART1_CTS_L/BT_I2S_BCLK/EGPIO140AV11
2 2
+3VALW UART1_RXD/BT_I2S_SDI/EGPIO141AU7
UART1_RTS_L/EGPIO142 AT11
R930 1 @ 2 10K_0402_5% APU_PCIE_W AKE# UART1_TXD/BT_I2S_SDO/EGPIO143AR11
R905 1 @ 2 100K_0402_5% USB_OC0# 32K_X2 AT2 X32K_X2 UART1_INTR/BT_I2S_LRCLK/AGPIO144AP9
R3927 1 2 10K_0402_5% EC_SCI# FP4 REV 0.93
R685 1 @ 2 10K_0402_5% APU_I2C3_SCL FP4_BGA968

APU_I2C3_SDA
R686 1 @ 2 10K_0402_5% MEM_VOLT_SEL/AGPIO3 RTC_CLK BLINK/AGPIO11 SYS_RST#
APU_TEST0
LPC_CLK0_EC LPC_CLK1 LPC_FRAME# <INT PU> <INT PU> <INT PU> <INT PU>
R2616 1 @ 2 2.2K_0402_5%
3 APU_TEST1 LDT_RST#/PG 3
R2618 1
R2617 1
@
@
2
2
1K_0402_5%
2.2K_0402_5% APU_TEST2
EMC@
RP13 BOOT FAIL CLKGEN SPI ROM
CZL CZ COIN BATT NORMAL
R3948 1 2 10K_0402_5% AGPIO8
<34>
<34>
HDA_BITCLK_AUDIO
HDA_SDOUT_AUDIO
1
2
3
8
7
6
HDA_BITCLK
HDA_SDOUT
HDA_SYNC
H TIMER
ENABLED
ENABLE
(DEFAULT)
(DEFAULT) 1.8V SPI ROM ENHANCED
RESET
ON BOARD
(DEFAULT)
OUTPUT TO
APU
(DEFAULT)
RESET MODE
(DEFAULT)
+3VS <34> HDA_SYNC_AUDIO
4 5 HDA_RST# (DEFAULT)
<34> HDA_RST#_AUDIO
BOOT FAIL
R676 1 2 2.2K_0402_5% APU_SMB_CLK0 33_0804_8P4R_5% CLKGEN TRADITION COIN BATT OUTPUT SHORT RST
R677 1
R3863 1
R3864 1
@
@
2
2
2
2.2K_0402_5%
10K_0402_5%
10K_0402_5%
APU_SMB_DATA0
LAN_CLKREQ#
W LAN_CLKREQ#
T1@
RP68
L TIMER
DISABLED
(DEFAULT)
DISABLED LPC ROM 3.3V SPI ROM
(Default)
RESET NOT ON
BOARD
TO PADS MODE
R3975 1 @ 2 10K_0402_5% SSD_CLKREQ# 8 1

7 2 +3VS +3VALW
+1.8VS 6 3
1
5 4
R3946 1 2 10K_0402_5% APU_I2C1_SCL @
R3947 1 2 10K_0402_5% APU_I2C1_SDA 1K_0804_8P4R_5% R902 R904 R925 R928 R949 R951 R954
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
2
R3945 1 @ 2 10K_0402_5% HDA_SDIN0
HDA_SDIN1 <10,24,33> LPC_FRAME#
R3929 1 2 10K_0402_5%
HDA_SDIN2 +1.8VALW +3VS <10,24> LPC_CLK0_EC
R3928 1 2 10K_0402_5%
HDA_BITCLK <10,33> LPC_CLK1
R3954 1 @ 2 10K_0402_5% AGPIO3
RTC_CLK
1
R3850 1 2 10K_0402_5% PEG_CLKREQ# SYS_RST#

4.7K_0402_5%
R348
R3879 1 @ 2 0_0402_5% HVB R346 AGPIO11

R40 1 2 15K_0402_5% APU_TEST0 22K_0402_1%
1
1
R41 1 2 15K_0402_5% APU_TEST1
R42 1 2 15K_0402_5% APU_TEST2 @ @ @ @ @ @
4
2
EC_RSMRST# 4
R903 R926 R927 R929 R2619 R2620 R2621
2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5% 2K_0402_5%
SYS_PW RGD_EC
2
2
2 2
R3949 1 2 10K_0402_5% APU_I2C0_SCL
R3950 1 2 10K_0402_5% APU_I2C0_SDA C999 C1000
R3961 1 T3@ 2 10K_0402_5% VDDGFX_PW RGD 1U_0402_6.3V6K 0.22U_0402_16V7K
1 1
FP4 GPIO/AZ/MISC/STRAPS
Custom 1.A
A B C D E
A B C D E
UAPU1E @
CLK/SATA/USB/SPI/LPC
SATA_ATX_DRX_P0 AU3 SATA_TX0P USBCLK/25M_48M_OSC AP8
<30> SATA_ATX_DRX_P0 SATA_ATX_DRX_N0 AU4 SATA_TX0N
<30> SATA_ATX_DRX_N0 USB_ZVSS
USB_ZVSS AP5 R641 1 2 11.8K_0402_1%
1 HDD <30> SATA_ARX_DTX_N0 SATA_ARX_DTX_N0 AV1 SATA_RX0N 1
SATA_ARX_DTX_P0 AV2 SATA_RX0P USB_HSD0P AR2 USB20_P0
<30> SATA_ARX_DTX_P0 USB20_N0 USB20_P0 <31>
USB_HSD0N AR1 S/B USB2.0 Conn.
SATA_ATX_DRX_P1 AY2 USB20_N0 <31>
SATA_TX1P
<30> SATA_ATX_DRX_P1 SATA_ATX_DRX_N1 AY1 USB20_P1
SATA_TX1N USB_HSD1P AR3
<30> SATA_ATX_DRX_N1 USB20_N1 USB20_P1 <31>
SSD USB_HSD1N AR4 S/B USB2.0 Conn.
SATA_ARX_DTX_N1 AW4 USB20_N1 <31>
SATA_RX1N
<30> SATA_ARX_DTX_N1 SATA_ARX_DTX_P1 AW3 USB20_P2
SATA_RX1P USB_HSD2P AN2
<30> SATA_ARX_DTX_P1 USB20_N2 USB20_P2 <29>
USB_HSD2N AN1 WLAN/BT combo
USB20_N2 <29>
R90 2 1 1K_0402_1% SATA_ZVSS AW1 SATA_ZVSS
2 1 DEVSLP0 +0.95VS R96 2 1 1K_0402_1% SATA_ZVDD AW2 SATA_ZVDDP USB_HSD3P AN3 USB20_P3
USB20_N3 USB20_P3 <27>
R3852 10K_0402_5% DEVSLP0 AT17 DEVSLP[0]/EGPIO67 USB_HSD3N AN4 Camera
USB20_N3 <27>
2 1 DEVSLP1 DEVSLP1 AT12 DEVSLP[1]/EGPIO70
<30> DEVSLP1
R3853 10K_0402_5% AGPIO130 BB15 SATA_ACT_L/AGPIO130 USB_HSD4P AM1
2 1 AGPIO130 USB_HSD4N AM2
R3882 10K_0402_5% AU2 SATA_X1
USB_HSD5P AL2 USB20_P5
USB20_N5 USB20_P5 <32>
USB_HSD5N AL1 Type-C Conn. (U3 port 1,2)
USB20_N5 <32>
AU1 SATA_X2 USB_HSD6P AL3
+3VS USB_HSD6N AL4
2 @ 1 CLKRUN# CLK_PEG_VGA U4 GFX_CLKP USB_HSD7P AK2 USB20_P7

<15> CLK_PEG_VGA CLK_PEG_VGA# USB20_N7 USB20_P7 <31>
R3872 10K_0402_5% VGA U3 AJ2 M/B USB3.0 Conn. (U3 port 3)
+3VALW
<15> CLK_PEG_VGA#
CLK_PCIE_LAN U1
GFX_CLKN
GPP_CLK0P
USB_HSD7N
USB20_N7 <31>
48MHz CRYSTAL
<28> CLK_PCIE_LAN CLK_PCIE_LAN#
LAN+CR <28> CLK_PCIE_LAN# U2 GPP_CLK0N R3980
2 1 LPCPD# 0_0402_5%
R3873 10K_0402_5% CLK_PCIE_W LAN W4 GPP_CLK1P 1 2 48M_X2
+1.8VS <29> CLK_PCIE_W LAN CLK_PCIE_W LAN# W3
2 WLAN <29> CLK_PCIE_W LAN# GPP_CLK1N 2
1 R938 2 1 2 48M_X1
2 1 APU_SPI_HOLD# W1 GPP_CLK2P 1M_0402_5%
R634 10K_0402_5% W2 GPP_CLK2N R3981
2 1 APU_SPI_W P# 0_0402_5%
R635 10K_0402_5% CLK_PCIE_SSD Y2 GPP_CLK3P
APU_SPI_CS1# <30> CLK_PCIE_SSD CLK_PCIE_SSD#
2 1 PCIE_SSD Y1 GPP_CLK3N 2 1
<30> CLK_PCIE_SSD# 2 1
R636 10K_0402_5%
BC10 X25M_48M_OSC
USB_SS_ZVSS AD2 USBSS_ZVSS R644 1 2 1K_0402_1%
USB_SS_ZVDDP AD1 USBSS_ZVDD R645 1 2 1K_0402_1% +0.95VALW
48M_X1 T2 X48M_X1 Y1
USB_SS_0TXP AA3 48MHZ_8PF_X3S048000D81H-W
USB_SS_0TXN AA4 Part Number = SJ10000AF00
48M_X2 T1 X48M_X2 USB_SS_0RXP W9
USB_SS_0RXN W8 3 4
3 4
1 1
R107 1 RS@ 2 0_0402_5% AW14 LPCCLK0/EGPIO74 USB_SS_1TXP AA2 C795
APU_SPI_CS2# <9,24> LPC_CLK0_EC USB3_ATX_DRX_P1 <32>
2 1 R108 1 RS@ 2 0_0402_5% AY13 LPCCLK1/EGPIO75 USB_SS_1TXN AA1 4.7P_0402_50V8C
<9,33> LPC_CLK1 USB3_ATX_DRX_N1 <32>
R637 10K_0402_5% Type-C Conn. C794
2 1 APU_SPI_TPMCS# LPC_AD0 BB11 LAD0 USB_SS_1RXP W5 2 4.7P_0402_50V8C 2
<24,33> LPC_AD0 LPC_AD1 USB3_ARX_DTX_P1 <32>
R638 10K_0402_5% BA11 LAD1 USB_SS_1RXN W6
<24,33> LPC_AD1 LPC_AD2 USB3_ARX_DTX_N1 <32>
AY11 LAD2
<24,33> LPC_AD2 LPC_AD3 BA13 LAD3 USB_SS_2TXP AC1
<24,33> LPC_AD3 LPC_FRAME# USB3_ATX_DRX_P2 <32>
AV14 LFRAME_L USB_SS_2TXN AC2
<9,24,33> LPC_FRAME# USB3_ATX_DRX_N2 <32>
BA1 ESPI_ALERT_L/LDRQ0_L Type-C Conn.
SERIRQ BC14 SERIRQ/AGPIO87 USB_SS_2RXP Y6
<24,33> SERIRQ USB3_ARX_DTX_P2 <32>
CLKRUN# BC11 LPC_CLKRUN_L/AGPIO88 USB_SS_2RXN Y7
3 <33> CLKRUN# USB3_ARX_DTX_N2 <32> 3
LPCPD# AE9 LPC_PD_L/AGPIO21
USB_SS_3TXP AC4
USB3_ATX_DRX_P3 <31>
USB_SS_3TXN AC3
APU_SPI_CLK 1 RS@ USB3_ATX_DRX_N3 <31>
2 APU_SPI_CLK_R BC6 SPI_CLK/ESPI_CLK/EGPIO117 M/B USB3.0 Conn.
APU_SPI_CS1# BB8 SPI_CS1_L/EGPIO118 USB_SS_3RXP AB5
APU_SPI_CS2# USB3_ARX_DTX_P3 <31>
R106 AW7 SPI_CS2_L/ESPI_CS_L/EGPIO119 USB_SS_3RXN AB6
APU_SPI_MISO USB3_ARX_DTX_N3 <31>
0_0402_5% BA9 SPI_DI/ESPI_DATA/EGPIO120
APU_SPI_MOSI AY7 SPI_DO/EGPIO121
APU_SPI_W P# AW11 SPI_WP_L/EGPIO122
APU_SPI_HOLD# BA7 SPI_HOLD_L/EGPIO133
APU_SPI_TPMCS# AW12 SPI_TPM_CS_L/AGPIO76
FP4 REV 0.93
8MB SPI ROM FP4_BGA968
+1.8VS
U56
APU_SPI_CS1# 1 8 2 1
APU_SPI_MISO 2 CS# VCC 7 APU_SPI_HOLD# @
APU_SPI_W P# 3 DO(IO1) HOLD#(IO3) 6 APU_SPI_CLK C635 0.1U_0201_10V6K
4 WP#(IO2) CLK 5 APU_SPI_MOSI
GND DI(IO0)
W 25Q64FW SSIQ_SOIC_8P
APU_SPI_CLK 1 2 1 2
R617 @EMC@ C636 @EMC@
4
10_0402_1% 10P_0402_50V8J 4

FP4 SATA/CLK/USB/SPI
Custom 1.A
A B C D E
A B C D E
UAPU1F @
+1.2V POWER
C1008
+1.2V P25 VDDIO_MEM_S3_1 VDDCR_CPU_1 U8 +APU_CORE
C1057
C1058
C1059
C1060
C1061
C1062
C1063
C1064
C1065
C1066
C1087
C1088
C1089
C1090
C1091
C1092
C1093
P28 W7
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3A T24
VDDIO_MEM_S3_2
VDDIO_MEM_S3_3
VDDCR_CPU_2
VDDCR_CPU_3 W12 35A
T27 VDDIO_MEM_S3_4 VDDCR_CPU_4 W15
U25 VDDIO_MEM_S3_5 VDDCR_CPU_5 W18
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
180P_0402_50V8J
U28 VDDIO_MEM_S3_6 VDDCR_CPU_6 W21
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 V30 VDDIO_MEM_S3_7 VDDCR_CPU_7 Y8
@ @ @ V33 VDDIO_MEM_S3_8 VDDCR_CPU_8 Y10
W24 VDDIO_MEM_S3_9 VDDCR_CPU_9 Y13
W27 VDDIO_MEM_S3_10 VDDCR_CPU_10 Y16
Y25 VDDIO_MEM_S3_11 VDDCR_CPU_11 Y19
1 Y28 VDDIO_MEM_S3_12 VDDCR_CPU_12 Y22 1
Y30 VDDIO_MEM_S3_13 VDDCR_CPU_13 AB7
AB24 VDDIO_MEM_S3_14 VDDCR_CPU_14 AB9
AB27 AB12
Under APU AB30
VDDIO_MEM_S3_15
VDDIO_MEM_S3_16
VDDCR_CPU_15
VDDCR_CPU_16 AB15
AB33 VDDIO_MEM_S3_17 VDDCR_CPU_17 AB18
+1.2V AD25 VDDIO_MEM_S3_18 VDDCR_CPU_18 AB21
AD28 VDDIO_MEM_S3_19 VDDCR_CPU_19 AD6
C1111
C1112
C1113
C1114
C1115
C1116
AD30 VDDIO_MEM_S3_20 VDDCR_CPU_20 AD10
1 1 1 1 1 1 AE24 VDDIO_MEM_S3_21 VDDCR_CPU_21 AD13
AE27 VDDIO_MEM_S3_22 VDDCR_CPU_22 AD16
AF30 VDDIO_MEM_S3_23 VDDCR_CPU_23 AD19
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
180P_0402_50V8J
180P_0402_50V8J
AF33 VDDIO_MEM_S3_24 VDDCR_CPU_24 AD22
2 2 2 2 2 2 AG25 VDDIO_MEM_S3_25 VDDCR_CPU_25 AE7
AG28 VDDIO_MEM_S3_26 VDDCR_CPU_26 AE12
AH24 VDDIO_MEM_S3_27 VDDCR_CPU_42 AK9
AH27 VDDIO_MEM_S3_28 VDDCR_CPU_31 AG10
AH30 VDDIO_MEM_S3_29 VDDCR_CPU_43 AK10
AK25 VDDIO_MEM_S3_30 VDDCR_CPU_32 AG13
AK28 VDDIO_MEM_S3_31 VDDCR_CPU_44 AK13
AK30 AG16
DIMMS/GND AK33
VDDIO_MEM_S3_32
VDDIO_MEM_S3_33
VDDCR_CPU_33
VDDCR_CPU_45 AK16
AL27 VDDIO_MEM_S3_34 VDDCR_CPU_34 AG19
AM30 VDDIO_MEM_S3_35 VDDCR_CPU_46 AK19
VDDCR_CPU_35 AG22
+3VALW +3VS 1 RS@ 2 +3VS_APU +1.8VS AR19 VDDIO_AUDIO VDDCR_CPU_47 AK22
AH7
0.2A VDDCR_CPU_36
C1124
C1126
C1137
R119 +0.95VS_GFX AE6 VDDP_GFX_2 VDDCR_CPU_28 AE18

0_0402_5% AE5 AE21
1 1 1 1.5A VDDP_GFX_1 VDDCR_CPU_29
VDDCR_CPU_40 AH21
+3VS_APU AP19 VDD_33_1 VDDCR_CPU_30 AG6
10U_0603_6.3V6M
0.22U_0402_16V7K
10U_0603_6.3V6M
AP21 AH12
2
2 2 2 0.2A VDD_33_2 VDDCR_CPU_37
VDDCR_CPU_49 AN6
2
+1.8VS
AP16 VDD_18_1 VDDCR_CPU_38 AH15
AP18 AH18
1.5A VDD_18_2 VDDCR_CPU_39
VDDCR_CPU_48 AL7
+1.8VALW AP10 VDD_18_S5_1 VDDCR_CPU_41 AK6
AR9 AE15
0.5A VDD_18_S5_2 VDDCR_CPU_27
+3VALW AP15 VDD_33_S5_1

AR15 L8
For Audio 0.2A VDD_33_S5_2 VDDCR_GFX_14
L13
+APU_GFX
Near to AR19 AN12 VDDP_S5_1
VDDCR_GFX_15
VDDCR_GFX_16 L16 35A
+0.95VALW
AP12 L19
+APU_CORE_FCH +1.8VALW +1.8VS +1.8VS 0.8A VDDP_S5_2 VDDCR_GFX_17
VDDCR_GFX_18 L22
C1108
C1109
C1110
C1085
C1086
C1101
C1102
+APU_CORE_FCH AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7

C1005
C1006
C1007 AR12 N12

1 1 1 1 1 1 1
1 1 1
0.2A/0.9A VDDCR_FCH_S5_2 VDDCR_GFX_20
VDDCR_GFX_21 N15
+0.95VS
AW19 VDDP_6 VDDCR_GFX_22 N18
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_16V7K
10U_0603_6.3V6M
0.22U_0402_16V7K
10U_0603_6.3V6M
0.22U_0402_16V7K
AU17 N21
2 2 2 2 2 2 2 7A VDDP_1 VDDCR_GFX_23
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
AU19 VDDP_2 VDDCR_GFX_24 P8

2 2 2 AV17 VDDP_3 VDDCR_GFX_25 P13
AV19 VDDP_4 VDDCR_GFX_26 P16
AW17 VDDP_5 VDDCR_GFX_27 P19
VDDCR_GFX_28 P22
+APU_CORE_NB AL12 VDDCR_NB_1 VDDCR_GFX_29 T7
AL13 F12
17A AL15
VDDCR_NB_2
VDDCR_NB_3
VDDCR_GFX_1
VDDCR_GFX_2 F15
AL18 VDDCR_NB_4 VDDCR_GFX_3 G11
AL21 VDDCR_NB_5 VDDCR_GFX_4 G14
AN13 VDDCR_NB_6 VDDCR_GFX_5 J8
AN16 VDDCR_NB_7 VDDCR_GFX_6 J9
3 AN19 J11 3
+0.95VALW +0.95VS VDDCR_NB_8 VDDCR_GFX_7
AN22 VDDCR_NB_9 VDDCR_GFX_8 K7
C1118
C1119
C949
C950
C1080
C1083
C1099
C2690
C2691
C2692
C2693
C2694
C245
VDDCR_GFX_9 K12
1 1 1 1 1 1 1 1 1 1 1 1 1 VDDCR_GFX_10 K13
+RTC_APU_R AR17 VDDBT_RTC_G VDDCR_GFX_11 K15
+RTC_APU_R
VDDCR_GFX_12 K16
10U_0603_6.3V6M
0.22U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
0.22U_0402_16V7K
180P_0402_50V8J
VDDCR_GFX_30 T12
2 2 2 2 2 2 2 2 2 2 2 2 2 VDDCR_GFX_31 T15
VDDCR_GFX_32 T18
VDDCR_GFX_33 T21
VDDCR_GFX_34 U13
VDDCR_GFX_35 U16
VDDCR_GFX_36 U19
VDDCR_GFX_37 U22
VDDCR_GFX_13 K19
For VDDP_S5 For VDDP FP4 REV 0.93
FP4_BGA968 +RTCBATT
+0.95VS 1 T1@ 2 +0.95VS_GFX

RTC OF APU +RTCBATT
2
R3880
+RTC_APU
C2699
C2700
0_0603_5% +RTC_APU R4003

+RTCVCC
1 1 Vo=1.5V 1K_0402_5% JRTC1
W=20mils 1
+RTC_APU_R R93 1 2 1K_0402_5% U102 D103 2 1
1
2
10U_0603_6.3V6M
0.22U_0402_16V7K
AP2138N-1.5TRG1_SOT23-3 3
2 2 3 3
1 2 Vout GND
1
T1DIS@
T1DIS@
1 1 4
C166 C923 CLRP1 2 Vin GND
1 GND
0.22U_0402_16V7K 1U_0402_6.3V6K @ 0_0603_5% 1 2 +CHGRTC ACES_50271-0020N-001
4 2 1 4
C106
CONN@
0.1U_0201_10V6K C105
2
2 CHN202UPT_SC70-3
BR+DIS need pop Need OPEN 680P_0603_50V8J
2 SC600000B00
SP02000RO00
for Clear CMOS
For VDDP_GFX
FP4 PWR
Custom 1.A
A B C D E
A B C D E
UAPU1G @ UAPU1H @ UAPU1J @

GND GND
A8 VSS_1 VSS_63 L28 AE10 VSS_125 VSS_187 AV30 U30 RSVD_2
1 RS@ 2 ORIENT_APU# A12 VSS_2 VSS_64 M4 AE13 VSS_126 VSS_188 AV33 U31 RSVD_3
A16 VSS_3 VSS_65 M30 AE16 VSS_127 VSS_189 AW22 AN30 RSVD_4
R157 A20 VSS_4 VSS_66 N10 AE19 VSS_128 VSS_190 AY4
0_0402_5% A24 VSS_5 VSS_67 N13 AE22 VSS_129 VSS_191 AY6
A28 VSS_6 VSS_68 N16 AF1 VSS_130 VSS_192 AY8
1 A32 VSS_7 VSS_69 N19 AF4 VSS_131 VSS_193 AY10 1
B2 VSS_8 VSS_70 N22 AG9 VSS_132 VSS_194 AY12
B8 VSS_9 VSS_71 N27 AG12 VSS_133 VSS_195 AY14
B12 VSS_10 VSS_72 P1 AG15 VSS_134 VSS_196 AY16
B33 VSS_11 VSS_73 P2 AG18 VSS_135 VSS_197 AY20 FP4 REV 0.93
C3 VSS_12 VSS_74 P4 AG21 VSS_136 VSS_198 AY22
D4 VSS_13 VSS_75 P5 AH4 VSS_137 VSS_199 AY24 FP4_BGA968
D6 VSS_14 VSS_76 P12 AH10 VSS_138 VSS_200 AY26
D12 VSS_17 VSS_79 P21 AH19 VSS_141 VSS_203 BB1
D14 VSS_18 VSS_80 P30 AH22 VSS_142 VSS_204 BB33
D16 VSS_19 VSS_81 P33 AK1 VSS_143 VSS_205 BC4
D18 VSS_20 VSS_82 T4 AK4 VSS_144 VSS_206 BC8
D26 VSS_24 VSS_86 T19 AL16 VSS_148 VSS_210 BC24
F1 VSS_27 VSS_89 U5 AM4 VSS_151
F2 VSS_28 VSS_90 U12 AN9 VSS_152
2 F4 VSS_29 VSS_91 U15 AN10 VSS_153
2
F9 VSS_30 VSS_92 U18 AN15 VSS_154
F19 VSS_31 VSS_93 U21 AN18 VSS_155
F22 VSS_32 VSS_94 U24 AN21 VSS_156
F25 VSS_33 VSS_95 V1 AN25 VSS_157
F30 VSS_34 VSS_96 V2 AN28 VSS_158
F33 VSS_35 VSS_97 V4 AP1 VSS_159
G7 VSS_36 VSS_98 W10 AP2 VSS_160
G17 VSS_37 VSS_99 W13 AP4 VSS_161
G20 VSS_38 VSS_100 W16 AP7 VSS_162
G23 VSS_39 VSS_101 W19 AP22 VSS_163
G26 VSS_40 VSS_102 W22 AP27 VSS_164
H4 VSS_41 VSS_103 Y4 AP30 VSS_165
H30 VSS_42 VSS_104 Y5 AP33 VSS_166
J5 VSS_43 VSS_105 Y12 AR6 VSS_167
J15 VSS_44 VSS_106 Y15 AR25 VSS_168
J19 VSS_45 VSS_107 Y18 AR28 VSS_169
J22 VSS_46 VSS_108 Y21 AT4 VSS_170
J25 VSS_47 VSS_109 Y24 AT19 VSS_171
J28 VSS_48 VSS_110 AB1 AT22 VSS_172
K1 VSS_49 VSS_111 AB2 AT30 VSS_173
K2 VSS_50 VSS_112 AB4 AU5 VSS_174
3 K4 VSS_51 VSS_113 AB10 AU8 VSS_175
3
K10 VSS_52 VSS_114 AB13 AU11 VSS_176
K22 VSS_53 VSS_115 AB16 AU14 VSS_177
K27 VSS_54 VSS_116 AB19 AU20 VSS_178
K30 VSS_55 VSS_117 AB22 AU23 VSS_179
K33 VSS_56 VSS_118 AD4 AU27 VSS_180
L5 VSS_57 VSS_119 AD9 AV4 VSS_181
L18 VSS_60 VSS_122 AD18 AV12 VSS_184 VSS_213 L24
L21 VSS_61 VSS_123 AD21 AV15 VSS_185 VSS_215 AL10
L25 VSS_62 VSS_124 AD24 AV25 VSS_186 VSS_214 AK21
FP4 REV 0.93 FP4 REV 0.93
FP4_BGA968 FP4_BGA968
4 4

FP4 GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
Custom 1.A
A B C D E
A B C D E
Reverse Type-4H
2-3A to 1 DIMMs/channel
JDIMM1A
DDRA_CLK0 REVERSE DDRA_SDQ0 DDRA_SDQ[7..0] <7>
137 8
<7> DDRA_CLK0 DDRA_CLK0# 139 CK0(T) DQ0 7 DDRA_SDQ1
<7> DDRA_CLK0# DDRA_CLK1 138 CK0#(C) DQ1 20 DDRA_SDQ2 +1.2V +1.2V
<7> DDRA_CLK1 DDRA_CLK1# 140 CK1(T) DQ2 21 DDRA_SDQ3 JDIMM1B
1
Address : A0 <7> DDRA_CLK1#
<7> DDRA_CKE0
DDRA_CKE0
DDRA_CKE1
109
110
CK1#(C)
CKE0
DQ3
DQ4
DQ5
4
3
16
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
Follow CRB design
111
112
REVERSE
VDD1 VDD11
141
142
1
<7> DDRA_CKE1 CKE1 DQ6 17 DDRA_SDQ7 117 VDD2 VDD12 147
+3VS DDRA_SCS0# 149 DQ7 13 DDRA_SDQS0 +1.2V 118 VDD3 VDD13 148
<7> DDRA_SCS0# DDRA_SCS1# 157 S0# DQS0(T) 11 DDRA_SDQS0# DDRA_SDQS0 <7> 123 VDD4 VDD14 153
<7> DDRA_SCS1# S1# DQS0#(C) DDRA_SDQS0# <7> VDD5 VDD15
162 124 154
S2#/C0 DDRA_SDQ[15..8] <7> VDD6 VDD16
2
165 28 DDRA_SDQ8 129 159
S3#/C1 DQ8 VDD7 VDD17
1
29 DDRA_SDQ9 RD3 130 160

DDRA_ODT0 DQ9 DDRA_SDQ10 +3VS VDD8 VDD18 +0.6VS
0_0402_5%
RD5
0_0402_5%
RD6
0_0402_5%
RD7
155 41 1K_0402_1% 135 163

<7> DDRA_ODT0 DDRA_ODT1 161 ODT0 DQ10 42 DDRA_SDQ11 +VREFA_CA 136 VDD9 VDD19
<7> DDRA_ODT1 ODT1 DQ11 DDRA_SDQ12 VDD10 +2.5V
24
1
@ @ @ DDRA_BG0 115 DQ12 25 DDRA_SDQ13 255 258
<7> DDRA_BG0 BG0 DQ13 VDDSPD VTT
2
DDRA_BG1 113 38 DDRA_SDQ14

<7> DDRA_BG1 DDRA_SBS0# 150 BG1 DQ14 37 DDRA_SDQ15 15mil 164 257
DDRA_SA2 <7> DDRA_SBS0# DDRA_SBS1# BA0 DQ15 DDRA_SDQS1 VREFCA VPP1
145 34 259
DDRA_SA1 <7> DDRA_SBS1# BA1 DQS1(T) DDRA_SDQS1# DDRA_SDQS1 <7> VPP2
CD20 4.7U_0402_6.3V6M
CD22 0.1U_0201_10V6K
CD21 0.1U_0201_10V6K
CD19 1000P_0402_50V7K
32
DDRA_SA0 <7> DDRA_SMA[16..0] DDRA_SMA0 DQS1#(C) DDRA_SDQS1# <7>
CD31 1U_0402_6.3V6K
144 1 99
A0 DDRA_SDQ[23..16] <7> VSS VSS
2
DDRA_SMA1 133 50 DDRA_SDQ16 2 102
A1 DQ16 1 2 2 1 VSS VSS
1
DDRA_SMA2 132 49 DDRA_SDQ17 RD4 5 103

DDRA_SMA3 A2 DQ17 DDRA_SDQ18 VSS VSS 1
RS@
0_0402_5%
RD8
RS@
0_0402_5%
RD9
RS@
0_0402_5%
RD10
131 62 1K_0402_1% 6 106

DDRA_SMA4 128 A3 DQ18 63 DDRA_SDQ19 9 VSS VSS 107
DDRA_SMA5 A4 DQ19 DDRA_SDQ20 2 1 1 2 VSS VSS
2D@
126 46 10 167
A5 DQ20 VSS VSS
1
DDRA_SMA6 127 45 DDRA_SDQ21 14 168 2
A6 DQ21 VSS VSS
2
DDRA_SMA7 122 58 DDRA_SDQ22 15 171

DDRA_SMA9 121 A8 DQ23 55 DDRA_SDQS2 19 VSS VSS 175
DDRA_SMA10 146 A9 DQS2(T) 53 DDRA_SDQS2# DDRA_SDQS2 <7> 22 VSS VSS 176
DDRA_SMA11 A10_AP DQS2#(C) DDRA_SDQS2# <7> VSS VSS
120 23 180
DDRA_SMA12 A11 DDRA_SDQ24 DDRA_SDQ[31..24] <7> VSS VSS
119 70 26 181 CRB use 1uF x1
Note: DDRA_SMA15
DDRA_SMA16
156 A14_WE#
A15_CAS#
DQ26
DQ27
84 DDRA_SDQ27
DDRA_SDQ28
Place near to SO-DIMM connector. 31 VSS
VSS
VSS
VSS
188
Layout Note: DDR4 support Even Parity check in DRAMs. 152 66 35 189
Check voltage tolerance of A16_RAS# DQ28 67 DDRA_SDQ29 36 VSS VSS 192
Place near JDIMM1 VREF_DQ at the DIMM socket +1.2V MEM_MA_ACT# 114 DQ29 79 DDRA_SDQ30 39 VSS VSS 193
<7> MEM_MA_ACT# ACT# DQ30 DDRA_SDQ31 VSS VSS
80 40 196
2
RD225 1 RS@ 2 0_0402_5% DDRA_PARITY 143 DQ31 76 DDRA_SDQS3 43 VSS VSS 197 2
PARITY DQS3(T) DDRA_SDQS3 <7> VSS VSS
RD1 2 1 1K_0402_1% DDRA_ALERT# 116 74 DDRA_SDQS3# 44 201
CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2 MEM_MA_EVENT# ALERT# DQS3#(C) DDRA_SDQS3# <7> VSS VSS
134 47 202
<7> MEM_MA_EVENT# MEM_MA_RST# EVENT# DDRA_SDQ32 DDRA_SDQ[39..32] <7> VSS VSS
108 174 48 205
+1.2V <7> MEM_MA_RST# RESET# DQ32 DDRA_SDQ33 VSS VSS
@EMC@ 2 1 173 51 206
CD1 .1U_0402_16V7K DQ33 187 DDRA_SDQ34 52 VSS VSS 209
APU_SMB_DATA0 254 DQ34 186 DDRA_SDQ35 56 VSS VSS 210
<9,14> APU_SMB_DATA0 APU_SMB_CLK0 SDA DQ35 DDRA_SDQ36 VSS VSS
253 170 57 213
<9,14> APU_SMB_CLK0 SCL DQ36 DDRA_SDQ37 VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
169 60 214
DDRA_SA2 166 DQ37 183 DDRA_SDQ38 61 VSS VSS 217
1 1 1 1 1 1 DDRA_SA1 SA2 DQ38 DDRA_SDQ39 VSS VSS
CD2
CD3
CD4
CD5
CD6
CD7
260 182 64 218

DDRA_SA0 256 SA1 DQ39 179 DDRA_SDQS4 65 VSS VSS 222
SA0 DQS4(T) 177 DDRA_SDQS4# DDRA_SDQS4 <7> 68 VSS VSS 223
2 2 2 2 2 2 DQS4#(C) DDRA_SDQS4# <7> VSS VSS
69 226
DDRA_SDQ40 DDRA_SDQ[47..40] <7> VSS VSS
92 195 72 227
91 CB0_NC DQ40 194 DDRA_SDQ41 73 VSS VSS 230
+1.2V 104 CB6_NC DQ46 204 DDRA_SDQ47 86 VSS VSS 243
97 CB7_NC DQ47 200 DDRA_SDQS5 89 VSS VSS 244
Follow MA51 95 DQS8(T) DQS5(T) 198 DDRA_SDQS5# DDRA_SDQS5 <7>
90 VSS VSS 247
DQS8#(C) DQS5#(C) DDRA_SDQS5# <7> VSS VSS
93 248
DDRA_SDQ48 DDRA_SDQ[55..48] <7> VSS VSS
1 216 94 251
<7> DDRA_SDM[7..0] DDRA_SDM0 DQ48 DDRA_SDQ49 VSS VSS
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
@ 12 215 98 252
+ CD18 DDRA_SDM1 33 DM0#/DBI0# DQ49 228 DDRA_SDQ50 VSS VSS
1 1 1 1 1 1 DDRA_SDM2 DM1#/DBI1# DQ50 DDRA_SDQ51
CD10
CD11 2D@
CD12 2D@
CD13 2D@
CD14 2D@
CD15 2D@
330U_D2_2V_Y 54 229 262 261

DDRA_SDM3 75 DM2#/DBI2# DQ51 211 DDRA_SDQ52 GND GND
2 DDRA_SDM4 178 DM3#/DBI3# DQ52 212 DDRA_SDQ53
2 2 2 2 2 2 SGA00009S00 DDRA_SDM5 199 DM4#/DBI4# DQ53 224 DDRA_SDQ54 LOTES_ADDR0206-P001A
330U 2V H1.9 DDRA_SDM6 220 DM5#/DBI5# DQ54 225 DDRA_SDQ55
CONN@
9mohm POLY DDRA_SDM7 241 DM6#/DBI6# DQ55 221 DDRA_SDQS6
DM7#/DBI7# DQS6(T) DDRA_SDQS6# DDRA_SDQS6 <7>
96 219
3 DM8#/DBI8# DQS6#(C) DDRA_SDQS6# <7> 3
DDRA_SDQ56 DDRA_SDQ[63..56] <7>

237
+1.2V DQ56 236 DDRA_SDQ57
DQ57 249 DDRA_SDQ58
DQ58 250 DDRA_SDQ59
DQ59 232 DDRA_SDQ60
DQ60 233 DDRA_SDQ61
DQ61 DDRA_SDQ62
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
180P_0402_50V8J
2 2 2 2 2 245
DQ62 DDRA_SDQ63
CD61
CD62
CD63
CD64
CD65
246
DQ63 242 DDRA_SDQS7
DQS7(T) DDRA_SDQS7# DDRA_SDQS7 <7>
240
1 1 1 1 1 DQS7#(C) DDRA_SDQS7# <7>
LOTES_ADDR0206-P001A
CONN@ Layout Note:
Place near JDIMM1.258
CRB use 4.7uF x1,0.1uF x1
+0.6VS
Layout Note: Layout Note:
Place near JDIMM1.257,259 Place near JDIMM1.255
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CD27 2D@
CD28 2D@
CD29
CD30
CRB use 0.1uF x2,180pF x1 CRB use 1uF x1
+2.5V +3VS 2 2 2 2
4 4
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CD23
CD24 2D@
CD25
CD26
2 2 2 2

DDR4_SO-DIMM
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
C5V08/D5PR8_LA-E903PR1A 1.A

A B C D E
A B C D E
*Stoney Platform will use 4H on JDIMM2*

Need to confirm Footprint Reverse Type-8H
2-3A to 1 DIMMs/channel
JDIMM2A
DDRB_CLK0 RESERVE DDRB_SDQ0 DDRB_SDQ[7..0] <7>
137 8
<7> DDRB_CLK0 DDRB_CLK0# 139 CK0(T) DQ0 7 DDRB_SDQ1
<7> DDRB_CLK0# DDRB_CLK1 138 CK0#(C) DQ1 20 DDRB_SDQ2 +1.2V +1.2V
<7> DDRB_CLK1 DDRB_CLK1# 140 CK1(T) DQ2 21 DDRB_SDQ3 JDIMM2B
1
Address : A2 <7> DDRB_CLK1#
<7> DDRB_CKE0
DDRB_CKE0
DDRB_CKE1
109
110
CK1#(C)
CKE0
DQ3
DQ4
DQ5
4
3
16
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
Follow CRB design
111
112
RESERVE
VDD1 VDD11
141
142
1
<7> DDRB_CKE1 CKE1 DQ6 17 DDRB_SDQ7 117 VDD2 VDD12 147
+3VS DDRB_SCS0# 149 DQ7 13 DDRB_SDQS0 +1.2V 118 VDD3 VDD13 148
<7> DDRB_SCS0# DDRB_SCS1# 157 S0# DQS0(T) 11 DDRB_SDQS0# DDRB_SDQS0 <7> 123 VDD4 VDD14 153
<7> DDRB_SCS1# S1# DQS0#(C) DDRB_SDQS0# <7> VDD5 VDD15
162 124 154
S2#/C0 DDRB_SDQ[15..8] <7> VDD6 VDD16
2
165 28 DDRB_SDQ8 129 159
S3#/C1 DQ8 VDD7 VDD17
1
DDRB_SDQ9
10K_0402_5%
RD244
29 RD243 130 160

DDRB_ODT0 DQ9 DDRB_SDQ10 +3VS VDD8 VDD18 +0.6VS
0_0402_5%
RD247
0_0402_5%
RD248
155 41 1K_0402_1% 135 163

<7> DDRB_ODT0 DDRB_ODT1 161 ODT0 DQ10 42 DDRB_SDQ11 +VREFB_CA 136 VDD9 VDD19
<7> DDRB_ODT1 ODT1 DQ11 DDRB_SDQ12 VDD10 +2.5V
24
1
@ @ DDRB_BG0 115 DQ12 25 DDRB_SDQ13 255 258
<7> DDRB_BG0 BG0 DQ13 VDDSPD VTT
2
DDRB_BG1 113 38 DDRB_SDQ14

<7> DDRB_BG1 DDRB_SBS0# 150 BG1 DQ14 37 DDRB_SDQ15 15mil 164 257
DDRB_SA2 <7> DDRB_SBS0# DDRB_SBS1# BA0 DQ15 DDRB_SDQS1 VREFCA VPP1
145 34 259
DDRB_SA1 <7> DDRB_SBS1# BA1 DQS1(T) DDRB_SDQS1# DDRB_SDQS1 <7> VPP2
CD84 4.7U_0402_6.3V6M
CD76 0.1U_0201_10V6K
CD80 0.1U_0201_10V6K
CD87 1000P_0402_50V7K
32
DDRB_SA0 <7> DDRB_SMA[16..0] DDRB_SMA0 DQS1#(C) DDRB_SDQS1# <7>
CD89 1U_0402_6.3V6K
144 1 99
A0 DDRB_SDQ[23..16] <7> VSS VSS
2
DDRB_SMA1 133 50 DDRB_SDQ16 2 102
A1 DQ16 1 2 2 1 VSS VSS
1
DDRB_SMA2 132 49 DDRB_SDQ17 RD251 5 103

DDRB_SMA3 A2 DQ17 DDRB_SDQ18 VSS VSS 1
RS@
0_0402_5%
RD252
RS@
0_0402_5%
RD246
0_0402_5%
RD249
131 62 1K_0402_1% 6 106

DDRB_SMA4 128 A3 DQ18 63 DDRB_SDQ19 9 VSS VSS 107
DDRB_SMA5 A4 DQ19 DDRB_SDQ20 2 1 1 2 VSS VSS
2D@
126 46 10 167
A5 DQ20 VSS VSS
1
@ DDRB_SMA6 127 45 DDRB_SDQ21 14 168 2
A6 DQ21 VSS VSS
2
2
DDRB_SMA7 122 58 DDRB_SDQ22 15 171

DDRB_SMA9 121 A8 DQ23 55 DDRB_SDQS2 19 VSS VSS 175
DDRB_SMA10 146 A9 DQS2(T) 53 DDRB_SDQS2# DDRB_SDQS2 <7> 22 VSS VSS 176
DDRB_SMA11 A10_AP DQS2#(C) DDRB_SDQS2# <7> VSS VSS
120 23 180
DDRB_SMA12 A11 DDRB_SDQ24 DDRB_SDQ[31..24] <7> VSS VSS
119 70 26 181 CRB use 1uF x1
Note: DDRB_SMA15
DDRB_SMA16
156 A14_WE#
A15_CAS#
DQ26
DQ27
84 DDRB_SDQ27
DDRB_SDQ28
Place near to SO-DIMM connector. 31 VSS
VSS
VSS
VSS
188
Layout Note: DDR4 support Even Parity check in DRAMs. 152 66 35 189
Check voltage tolerance of A16_RAS# DQ28 67 DDRB_SDQ29 36 VSS VSS 192
Place near JDIMM2 VREF_DQ at the DIMM socket +1.2V MEM_MB_ACT# 114 DQ29 79 DDRB_SDQ30 39 VSS VSS 193
<7> MEM_MB_ACT# ACT# DQ30 DDRB_SDQ31 VSS VSS
80 40 196
2
RD250 1 RS@ 2 0_0402_5% DDRB_PARITY 143 DQ31 76 DDRB_SDQS3 43 VSS VSS 197 2
PARITY DQS3(T) DDRB_SDQS3 <7> VSS VSS
RD245 2 1 1K_0402_1% DDRB_ALERT# 116 74 DDRB_SDQS3# 44 201
CRB use 0.1uF x12 (6 pop,6 unpop),180pF x1,100uF x2 MEM_MB_EVENT# ALERT# DQS3#(C) DDRB_SDQS3# <7> VSS VSS
134 47 202
<7> MEM_MB_EVENT# MEM_MB_RST# EVENT# DDRB_SDQ32 DDRB_SDQ[39..32] <7> VSS VSS
108 174 48 205
+1.2V <7> MEM_MB_RST# RESET# DQ32 DDRB_SDQ33 VSS VSS
@EMC@ 2 1 173 51 206
CD73 .1U_0402_16V7K DQ33 187 DDRB_SDQ34 52 VSS VSS 209
APU_SMB_DATA0 254 DQ34 186 DDRB_SDQ35 56 VSS VSS 210
<9,13> APU_SMB_DATA0 APU_SMB_CLK0 SDA DQ35 DDRB_SDQ36 VSS VSS
253 170 57 213
<9,13> APU_SMB_CLK0 SCL DQ36 DDRB_SDQ37 VSS VSS
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
169 60 214
DDRB_SA2 166 DQ37 183 DDRB_SDQ38 61 VSS VSS 217
1 1 1 1 1 1 DDRB_SA1 SA2 DQ38 DDRB_SDQ39 VSS VSS
CD86
CD67
CD78
CD93
CD71
CD81
260 182 64 218

DDRB_SA0 256 SA1 DQ39 179 DDRB_SDQS4 65 VSS VSS 222
SA0 DQS4(T) 177 DDRB_SDQS4# DDRB_SDQS4 <7> 68 VSS VSS 223
2 2 2 2 2 2 DQS4#(C) DDRB_SDQS4# <7> VSS VSS
69 226
DDRB_SDQ40 DDRB_SDQ[47..40] <7> VSS VSS
92 195 72 227
91 CB0_NC DQ40 194 DDRB_SDQ41 73 VSS VSS 230
+1.2V 104 CB6_NC DQ46 204 DDRB_SDQ47 86 VSS VSS 243
97 CB7_NC DQ47 200 DDRB_SDQS5 89 VSS VSS 244
DQS8(T) DQS5(T) DDRB_SDQS5# DDRB_SDQS5 <7> VSS VSS
95 198 90 247
DQS8#(C) DQS5#(C) DDRB_SDQS5# <7> VSS VSS
93 248
DDRB_SDQ48 DDRB_SDQ[55..48] <7> VSS VSS
216 94 251
<7> DDRB_SDM[7..0] DDRB_SDM0 DQ48 DDRB_SDQ49 VSS VSS
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
12 215 98 252
DDRB_SDM1 33 DM0#/DBI0# DQ49 228 DDRB_SDQ50 VSS VSS
1 1 1 1 1 1 DDRB_SDM2 DM1#/DBI1# DQ50 DDRB_SDQ51
CD82
CD90
CD96
CD77
CD68
CD88
54 229 262 261

DDRB_SDM3 75 DM2#/DBI2# DQ51 211 DDRB_SDQ52 GND GND
DDRB_SDM4 178 DM3#/DBI3# DQ52 212 DDRB_SDQ53
2 2 2 2 2 2 DDRB_SDM5 199 DM4#/DBI4# DQ53 224 DDRB_SDQ54 LOTES_ADDR0070-P009A
DDRB_SDM6 220 DM5#/DBI5# DQ54 225 DDRB_SDQ55
DDRB_SDM7 DM6#/DBI6# DQ55 DDRB_SDQS6 CONN@
241 221
DM7#/DBI7# DQS6(T) DDRB_SDQS6# DDRB_SDQS6 <7>
96 219
3 DM8#/DBI8# DQS6#(C) DDRB_SDQS6# <7> 3
DDRB_SDQ56 DDRB_SDQ[63..56] <7>

237
+1.2V DQ56 236 DDRB_SDQ57
DQ57 249 DDRB_SDQ58
DQ58 250 DDRB_SDQ59
DQ59 232 DDRB_SDQ60
DQ60 233 DDRB_SDQ61
DQ61 DDRB_SDQ62
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
180P_0402_50V8J
2 2 2 2 2 245
DQ62 DDRB_SDQ63
CD91
CD94
CD97
CD66
CD85
246
DQ63 242 DDRB_SDQS7
DQS7(T) DDRB_SDQS7# DDRB_SDQS7 <7>
240
1 1 1 1 1 DQS7#(C) DDRB_SDQS7# <7>
LOTES_ADDR0070-P009A
CONN@ Layout Note:
Place near JDIMM2.258
CRB use 4.7uF x1,0.1uF x1
+0.6VS
Layout Note: Layout Note:
Place near JDIMM2.257,259 Place near JDIMM2.255
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CD70
CD74
CD92
CD72
CRB use 0.1uF x2,180pF x1 CRB use 1uF x1
+2.5V +3VS 2 2 2 2
4 4
10U_0603_6.3V6M
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1 1 1 1
CD79
CD83
CD75
CD95
2 2 2 2

DDR4_SO-DIMM
Custom
C5V08/D5PR8_LA-E903PR1A 1.A

A B C D E
5 4 3 2 1
PEG_HTX_C_GRX_P[0..7] PEG_GTX_C_HRX_P[0..7]
<6> PEG_HTX_C_GRX_P[0..7] <6> PEG_GTX_C_HRX_P[0..7]
PEG_HTX_C_GRX_N[0..7] PEG_GTX_C_HRX_N[0..7]
<6> PEG_HTX_C_GRX_N[0..7] <6> PEG_GTX_C_HRX_N[0..7]
D D
UV1B @
symbol2
PEG_HTX_C_GRX_P0 DIS@ 1 2 CV312 0.22U_0402_16V7K PEG_HTX_GRX_P0 AT41 AV35 PEG_GTX_HRX_P0 DIS@ 1 2 CV1 0.22U_0402_16V7K PEG_GTX_C_HRX_P0
PEG_HTX_C_GRX_N0 DIS@ 1 2 CV306 0.22U_0402_16V7K PEG_HTX_GRX_N0 AT40 PCIE_RX0P PCIE_TX0P AU35 PEG_GTX_HRX_N0 DIS@ 1 2 CV2 0.22U_0402_16V7K PEG_GTX_C_HRX_N0
PCIE_RX0N PCIE_TX0N
PEG_HTX_C_GRX_P1 DIS@ 1 2 CV308 0.22U_0402_16V7K PEG_HTX_GRX_P1 AR41 AU38 PEG_GTX_HRX_P1 DIS@ 1 2 CV3 0.22U_0402_16V7K PEG_GTX_C_HRX_P1
PEG_HTX_C_GRX_N1 DIS@ 1 2 CV305 0.22U_0402_16V7K PEG_HTX_GRX_N1 AR40 PCIE_RX1P PCIE_TX1P AU39 PEG_GTX_HRX_N1 DIS@ 1 2 CV4 0.22U_0402_16V7K PEG_GTX_C_HRX_N1
PCIE_RX1N PCIE_TX1N
PEG_HTX_C_GRX_P2 DIS@ 1 2 CV307 0.22U_0402_16V7K PEG_HTX_GRX_P2 AP41 AR37 PEG_GTX_HRX_P2 DIS@ 1 2 CV5 0.22U_0402_16V7K PEG_GTX_C_HRX_P2
PEG_HTX_C_GRX_N2 DIS@ 1 2 CV309 0.22U_0402_16V7K PEG_HTX_GRX_N2 AP40 PCIE_RX2P PCIE_TX2P AR38 PEG_GTX_HRX_N2 DIS@ 1 2 CV6 0.22U_0402_16V7K PEG_GTX_C_HRX_N2
PCIE_RX2N PCIE_TX2N
PEG_HTX_C_GRX_P3 DIS@ 1 2 CV313 0.22U_0402_16V7K PEG_HTX_GRX_P3 AM41 AN37 PEG_GTX_HRX_P3 DIS@ 1 2 CV7 0.22U_0402_16V7K PEG_GTX_C_HRX_P3
PEG_HTX_C_GRX_N3 DIS@ 1 2 CV304 0.22U_0402_16V7K PEG_HTX_GRX_N3 AM40 PCIE_RX3P PCIE_TX3P AN38 PEG_GTX_HRX_N3 DIS@ 1 2 CV8 0.22U_0402_16V7K PEG_GTX_C_HRX_N3
PCIE_RX3N PCIE_TX3N
PEG_HTX_C_GRX_P4 T1DIS@ 1 2 CV2710 0.22U_0402_16V7K PEG_HTX_GRX_P4 AL41 AL37 PEG_GTX_HRX_P4 T1DIS@ 1 2 CV2715 0.22U_0402_16V7K PEG_GTX_C_HRX_P4
PEG_HTX_C_GRX_N4 T1DIS@ 1 2 CV2707 0.22U_0402_16V7K PEG_HTX_GRX_N4 AL40 PCIE_RX4P PCIE_TX4P AL38 PEG_GTX_HRX_N4 T1DIS@ 1 2 CV2708 0.22U_0402_16V7K PEG_GTX_C_HRX_N4
PCIE_RX4N PCIE_TX4N
PEG_HTX_C_GRX_P5 T1DIS@ 1 2 CV2711 0.22U_0402_16V7K PEG_HTX_GRX_P5 AK41 AJ37 PEG_GTX_HRX_P5 T1DIS@ 1 2 CV2713 0.22U_0402_16V7K PEG_GTX_C_HRX_P5
PEG_HTX_C_GRX_N5 T1DIS@ 1 2 CV2709 0.22U_0402_16V7K PEG_HTX_GRX_N5 AK40 PCIE_RX5P PCIE_TX5P AJ38 PEG_GTX_HRX_N5 T1DIS@ 1 2 CV2703 0.22U_0402_16V7K PEG_GTX_C_HRX_N5
PCIE_RX5N PCIE_TX5N
PEG_HTX_C_GRX_P6 T1DIS@ 1 2 CV2717 0.22U_0402_16V7K PEG_HTX_GRX_P6 AJ41 AG37 PEG_GTX_HRX_P6 T1DIS@ 1 2 CV2705 0.22U_0402_16V7K PEG_GTX_C_HRX_P6
PEG_HTX_C_GRX_N6 T1DIS@ 1 2 CV2714 0.22U_0402_16V7K PEG_HTX_GRX_N6 AJ40 PCIE_RX6P PCIE_TX6P AG38 PEG_GTX_HRX_N6 T1DIS@ 1 2 CV2712 0.22U_0402_16V7K PEG_GTX_C_HRX_N6
PCIE_RX6N PCIE_TX6N
PEG_HTX_C_GRX_P7 T1DIS@ 1 2 CV2704 0.22U_0402_16V7K PEG_HTX_GRX_P7 AH41 AE37 PEG_GTX_HRX_P7 T1DIS@ 1 2 CV2716 0.22U_0402_16V7K PEG_GTX_C_HRX_P7
PEG_HTX_C_GRX_N7 T1DIS@ 1 2 CV2706 0.22U_0402_16V7K PEG_HTX_GRX_N7 AH40 PCIE_RX7P PCIE_TX7P AE38 PEG_GTX_HRX_N7 T1DIS@ 1 2 CV2702 0.22U_0402_16V7K PEG_GTX_C_HRX_N7
PCIE_RX7N PCIE_TX7N
C CLK_PEG_VGA AV33 AV41 PLT_RST_VGA# C

<10> CLK_PEG_VGA CLK_PEG_VGA# PCIE_REFCLKP PERSTB
<10> CLK_PEG_VGA# AU33
PCIE_REFCLKN AC41 PX_EN1 @
PX_EN T218
For BACO mode(AMD PowerXpress) use, NC if not use
RV371 DIS@
200_0402_1%
AU41 1 2
PCIE_ZVSS
REV 0.91
2160896088A1R16M_FCBGA769P-NH
+3VSDGPU
B B
UV2
MC74VHC1G08DFT2G_SC70-5
5
DIS@
1
P
<9,28,29,30> APU_PCIE_RST# IN1 PLT_RST_VGA#
4
2 O
<9> PE_GPIO0 IN2
G
1
3
1
RV4
RV370 100K_0402_5%
2.2K_0402_5% DIS@
DIS@
2
2
A A

R17M-P1-50/70_(1/9)_PCIE
Custom 1.A
5 4 3 2 1
5 4 3 2 1
+3VSDGPU
+3VSDGPU
SCL use 47k, CRB use 4.7k
2
AMD Confirm List_1027 use PU-47k
+3VSDGPU RV409
10K_0402_5%
1
10mA UV1E @ DIS@ DV1 DIS@ RV1640
RV507 RV508 AM31 symbol5 W40 GPIO_0 RB751V-40_SOD323-2 0_0402_5%
1
47K_0402_5% 47K_0402_5% VDD_33 GPIO_0 AA40 VGA_AC_BATT 2 1 2 RS@ 1
1 GPIO_1 GPIO_2 GPU_ACIN <24>
DIS@ DIS@ DIS@ AA35
GPIO_2
5
CV26 +3VSDGPU
2
1U_0402_6.3V6K
G
3 4 VGA_SMB_DA3 2 AA34 VGA_AC_BATT
<8,24> EC_SMB_DA2 GPIO_5_REG_HOT_AC_BATT GPIO_6_TACH
S
U35 RV1631 2 @ 1 10K_0201_5%
QV1A GPIO_6_TACH +1.8VALW
GPIO_8 GPIO_8_ROMSO
2
DMN66D0LDW-7_SOT363-6 AP25 RV1644 1 DIS@ 2 33_0402_5%
D GPIO_8_ROMSO AM25 GPIO_9 RV1645 1 DIS@ 2 33_0402_5% GPIO_9_ROMSI @ UV3 D
G
DIS@ VGA_SMB_CK3 GPIO_10 GPIO_10_ROMSCK
5
6 1 GPIO_9_ROMSI AM27 RV1646 1 DIS@ 2 33_0402_5% NL17SZ07DFT2G_SC70-5
<8,24> EC_SMB_CK2 GPIO_10_ROMSCK GPIO_11
S
W41 1
P
QV1B GPIO_11 Y40 GPIO_12 4 NC
DMN66D0LDW-7_SOT363-6 GPIO_12 Y41 GPIO_13 Y 2
GPIO_13 A APU_PROCHOT# <8,24,44,45>
G
DIS@ AU21
GPIO_14_HPD2 AA41 GPIO_15
3
Vgs = 1.2~2.0 V GPIO_15 U34 SA00004BV00
GPIO_16_8P_DETECT R37
GPIO_17_THERMAL_INT AV25
GPIO_18_HPD3 R38 GPIO_19_CTF DV2 DIS@
GPIO_19_CTF AB40 GPIO_20 RB751V-40_SOD323-2
AC35 GPIO_20 AB41 GPIO_21_PCC 2 1 GPU_PROCHOT#
AC34 SCL GPIO_21 AP27 GPIO_22 RV1647 1 DIS@ 2 33_0402_5% GPIO_22_ROMCSb
SDA GPIO_22_ROMCSB W37 GPIO_29
VGA_SMB_CK3 AW40 GPIO_29 W38
VGA_SMB_DA3 AW41 SMBCLK GPIO_30 BA38
SMBDAT GENERICA AV29
GENERICB AU31
GENERICC AV31
GENERICD AU25
GPU_SVC RV155 1 DIS@ 2 0_0402_5% AU17 GENERICE_HPD4 AV23
<48> GPU_SVC GPU_SVD RV156 1 DIS@ 2 0_0402_5% AV17 GPIO_SVC GENERICF_HPD5 AM29
+1.8VSDGPU +1.8VSDGPU <48> GPU_SVD GPU_SVT RV157 1 DIS@ 2 0_0402_5% AR17 GPIO_SVD GENERICG
<48> GPU_SVT GPIO_SVT AV21 +3VSDGPU +3VSDGPU
SCL PU-1k AN34 HPD1
CRB PU-10k/PD-1uF AP31 DDCVGACLK
AMD Confirm List_1027 use PU-1k DDCVGADATA UV56 @
GPIO_22_ROMCSb 1 8
10K_0402_5%
10K_0402_5%
10K_0402_5%
GPIO_8_ROMSO CS# VCC

1 DIS@ 2
2 DIS@ 1
2 DIS@ 1
2 7
1K_0402_5%
1K_0402_5%
3 DO(IO1) HOLD#(IO3) 6 GPIO_10_ROMSCK

RV84
RV87
RV410
RV412
RV413
WP#(IO2) CLK GPIO_9_ROMSI 1

@
4 5 DIS@
AV40 PEG_CLKREQ#_R RV153 2 @ 1 0_0402_5% GND DI(IO0) CV2721
TEST_PG CLKREQB PEG_CLKREQ# <9>
AY13 AU40 WAKEB GD25Q40CTIGR_SOIC_8P 0.1U_0201_10V6K
1
GPU_SVC TEST_PG_BACO BA13 TEST_PG WAKEB 2

GPU_SVD TEST_PG TEST_PG_BACO
SA0000AE400
RV368 2 @ 1 10K_0402_5% S IC FL 4M GD25Q40CTIGR SOP 8P SPI
GPU_SVT TEST_PG_BACO
AC40 Follow CRB material
1U_0402_6.3V6K
1U_0402_6.3V6K
DIGON
10K_0402_5%
10K_0402_5%
10K_0402_5%
1 1
2
1 DIS@ 2
AC37
K41 BL_ENABLE AC38
RV89
RV88
RV411
CV314
CV315
RSVD#K41 BL_PWM_DIM
@
R34
C 2 2 RSVD#R34 C
W34 HSYNC
HSYNC W35 VSYNC
1
VSYNC
AG34
SWAPLOCKA AE34
SWAPLOCKB AR29
GENLK_CLK AP29
GENLK_VSYNC +3VSDGPU
Boot-VID Code
REV 0.91
2
2160896088A1R16M_FCBGA769P-NH @
Voltage RV91
SVC SVD Selected (V) 10K_0402_5%
1
GPIO_21_PCC 1 2
0 0 1.1 2 RV90 @ 1K_0402_1%
GPU_PROCHOT# <48>
@
0 1 1.0 CV2718
0.1U_0201_10V6K
1 0 0.9 1
1 1 0.8 Peak Current Control (PCC) CKT

Reversed
+3VSDGPU +1.8VSDGPU +3VSDGPU

B B
+3VSDGPU
1
RV502 RV152 RV162
@ 10K_0201_5% @ 10K_0201_5% 4.7K_0402_5%
@
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
2
1
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
GPIO_19_CTF WAKEB
@
@
RV416
RV414
RV418
RV420
RV422
RV424
RV426
RV429
RV432
RV434
RV436
RV438
RV440
VDD_33 SCL can leave nc
1
2
GPIO_0 TX_HALF_SWING[0:disable,1:enable] DIS@ RV430

GPIO_2 BIF_GEN3_EN_A[0:disable,1:enable] RV151 4.7K_0402_5%
GPIO_11 ROM_CONFIG_[0]/MemoryAperture 10K_0201_5% @
GPIO_12 ROM_CONFIG_[1]/MemoryAperture
2
GPIO_13 ROM_CONFIG_[2]/MemoryAperture
GPIO_15 Reserved [PD for default]
GPIO_20 TX_DEEMPH_EN[0:disable,1:enable]
GPIO_29 BIF_VGA_DIS[0:VGA,1:Headless]
HSYNC Special Usage[1] GPUdefault
VSYNC Special Usage[0] GPUdefault
GPIO_8 BIF_CLK_PM_EN[0:disable,1:enable]
GPIO_9 Reserved [PD for production]
GPIO_22 BIOS_ROM_EN[0:disable,1:enable]
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
@
@
RV417
RV415
RV419
RV421
RV423
RV425
RV427
RV428
RV431
RV433
RV435
RV437
RV439
2
A A

R17M-P1-50/70_(2/9)_MSIC-1
Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C5V08/D5PR8_LA-E903PR1A 1.A
5 4 3 2 1
5 4 3 2 1
+3VSDGPU
+1.8VSDGPU
@
JTAG_TDI_GPU 8 1
JTAG_TDO_GPU 7 2
JTAG_TMS_GPU 6 3
10K_0201_5%
10K_0201_5%
1 DIS@ 2
1 DIS@ 2
JTAG_TCK_GPU 5 4
RV468
RV467
RPV34
UV1A @ 10K_0804_8P4R_5%
RV101 33_0201_5% symbol1
1 DIS@ 2 AA38 AF41 JTAG_TDO_GPU +3VSDGPU
1 DIS@ 2 AA37 BP_0 JTAG_TDO AD40 JTAG_TDI_GPU
RV100 33_0201_5% BP_1 JTAG_TDI AD41 JTAG_TMS_GPU
JTAG_TMS AE41 JTAG_TCK_GPU JTAG_TRSTB_GPU RV369 2 DIS@ 1 10K_0201_5%
JTAG_TCK RV1630 2 @ 1 10K_0201_5%
D JTAG_TESTEN_GPU D
RV469 1 DIS@ 2 B2 AE40
10K_0402_5% TEST6 TESTEN AF40 JTAG_TRSTB_GPU
JTAG_TRSTB
+3VSDGPU
REV 0.91
2160896088A1R16M_FCBGA769P-NH JTAG_TESTEN_GPU RV470 2 @ 1 5.1K_0201_1%

RV471 2 DIS@ 1 1K_0201_5%
UV1F @
symbol6 BA39 XTALIN XTALOUT RV503 2 @ 1 0_0402_5% XTALOUT_R +1.8VSDGPU
XTALIN
RV20 DIS@
1M_0402_5%
XTALIN RV504 2 @ 1 0_0402_5% XTALIN_R SI_SS_SEL RV154 1 DIS@ 2 5.1K_0402_1%
YV1 DIS@
SJ10000UI00 RV505 1 @ 2 5.1K_0402_1%
27MHZ_10PF_XRCGB27M000F2P18R0
ESR:40ohm (Max)
3 1
AY39 XTALOUT 3 1
XTALOUT 1 NC NC
DIS@ 1
CV450 DIS@
18P_0402_50V8J 4 2 CV451
2 18P_0402_50V8J
AV15 1 @ 2
C PLLCHARZ_L AU15 1 T229 C
@
PLLCHARZ_H T230
+1.8VSDGPU
REV 0.91 AY38
ANALOGIO DIS@
UV4
1
XTALOUT_R 3 2 XTALIN_R LV7
2160896088A1R16M_FCBGA769P-NH RV83 XOUT XIN/CLKIN BLM15BD121SN1D_0402
@ 16.2K_0402_1% RV506 1 1 DIS@ 2
0_0402_5% VDD
XTALIN_100M
0.1U_0201_10V6K
CV2723
10U_0603_6.3V6M
2 DIS@ 1 4 1 1
SSCLK1/REFCLK/FSEL/SSONb/OE
2
CV449 DIS@
DNI
5 SI_SS_SEL
SSCLK2/OE/SSONb/PD 2 @ 2
6
VSS
SI51214-A1FAGMR_TDFN6_1P2X1P4
SA0000A4K00
S IC SI51214-A1FAGMR TDFN 6P CLK GEN
RV464 V4G_S@ RV462 V4G_S@ RV460 V4G_S@
B B
+1.8VSDGPU
S RES 1/20W 5.1K +-1% 0201 S RES 1/20W 5.1K +-1% 0201 S RES 1/20W 5.1K +-1% 0201
SD000008900 SD000008900 SD000008900
AUD_PORT_CONN[2:0] RV464 V4G_H@ RV462 V4G_H@ RV459 V4G_H@
UV1K @ 111: No usable endpoints
symbol11 110: One usable endpoint
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
101: Two usable endpoints
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
2 DIS@ 1
1
L40 DBGDATA_0
DBGDATA_0 DBGDATA_1 100: Three usable endpoints
L41 011: Four usable endpoints
DBGDATA_1 DBGDATA_2
@
@
M40
RV456
RV453
RV457
RV459
RV461
RV463
RV465
RV442 010: Five usable endpoints

DBGDATA_2 M41 DBGDATA_3 001: Six usable endpoints
DBGDATA_3 DBGDATA_4
N40 000: All endpoints are usable SD000008900 SD000008900 SD000008900
DBGDATA_4
2
2
N41 DBGDATA_5
DBGDATA_5 P40 DBGDATA_6 DBGDATA_0 AUD_PORT_CONN[0] BOARD_CONFIG[2:0] RV464 V2G_S@ RV461 V2G_S@ RV460 V2G_S@
DBGDATA_6 P41 DBGDATA_7 DBGDATA_1 AUD_PORT_CONN[1] 000:SAM 256Mx32
DBGDATA_7 R40 DBGDATA_8 1 @ DBGDATA_2 AUD_PORT_CONN[2] 001:HYN 256Mx32
DBGDATA_8 DBGDATA_9 1 T221 DBGDATA_3 010:SAM 128Mx32
R41 @ BOARD_CONFIG[0]
DBGDATA_9 DBGDATA_101 T222 DBGDATA_4 011:HYX 128Mx32
T40 @ BOARD_CONFIG[1] 100:MIC 256Mx32
DBGDATA_10 T41 DBGDATA_111 T223 DBGDATA_5 BOARD_CONFIG[2]
@ 101:
DBGDATA_11 DBGDATA_121 T224 DBGDATA_6
U40 @ SMBUS_ADDR[0] 110: S RES 1/20W 5.1K +-1% 0201 S RES 1/20W 5.1K +-1% 0201 S RES 1/20W 5.1K +-1% 0201
DBGDATA_12 DBGDATA_131 T225 DBGDATA_7 111:
U41 @ SMBUS_ADDR[1] SD000008900 SD000008900 SD000008900
DBGDATA_13 DBGDATA_141 T226
V40 @
DBGDATA_14 DBGDATA_151 T227 DBGDATA_[7:6]
V41 @ RV464 V2G_H@ RV461 V2G_H@ RV459 V2G_H@
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
5.1K_0201_1%
DBGDATA_15 T228
1
2 DIS@ 1
00: 0× 40
01: 0× 41
REV 0.91 10: 0× 42
@
@
RV455
RV454
RV458
RV460
RV462
RV464
RV466
RV441
11: 0× 43
2160896088A1R16M_FCBGA769P-NH
2
SD000008900 SD000008900 SD000008900
RV463 V4G_M@ RV462 V4G_M@ RV460 V4G_M@
A A
SD000008900 SD000008900 SD000008900

R17M-P1-50/70_(3/9)_MSIC-2
Custom 1.A
5 4 3 2 1
5 4 3 2 1
UV1C @ UV1D @
<19> MA0_D[0..31] MA1_D[0..31] <19> <20> MB0_D[0..31] MB1_D[0..31] <20>
symbol3 symbol4
MA0_D0 L34 B27 MA1_D0 MB0_D0 C2 AH1 MB1_D0
MA0_D1 L37 DQA0_0 DQA1_0 A27 MA1_D1 MB0_D1 C1 DQB0_0 DQB1_0 AH2 MB1_D1
MA0_D2 L38 DQA0_1 DQA1_1 B26 MA1_D2 MB0_D2 D2 DQB0_1 DQB1_1 AJ2 MB1_D2
MA0_D3 J35 DQA0_2 DQA1_2 A26 MA1_D3 MB0_D3 D1 DQB0_2 DQB1_2 AK1 MB1_D3
MA0_D4 G37 DQA0_3 DQA1_3 A24 MA1_D4 MB0_D4 F1 DQB0_3 DQB1_3 AL2 MB1_D4
MA0_D5 E38 DQA0_4 DQA1_4 B23 MA1_D5 MB0_D5 G2 DQB0_4 DQB1_4 AM1 MB1_D5
MA0_D6 E35 DQA0_5 DQA1_5 A23 MA1_D6 MB0_D6 G1 DQB0_5 DQB1_5 AM2 MB1_D6
D MA0_D7 DQA0_6 DQA1_6 MA1_D7 MB0_D7 DQB0_6 DQB1_6 MB1_D7 D
D35 B22 H2 AN2
MA0_D8 H41 DQA0_7 DQA1_7 B20 MA1_D8 MB0_D8 K2 DQB0_7 DQB1_7 AR1 MB1_D8
MA0_D9 H40 DQA0_8 DQA1_8 A20 MA1_D9 MB0_D9 K1 DQB0_8 DQB1_8 AR2 MB1_D9
MA0_D10 G41 DQA0_9 DQA1_9 B19 MA1_D10 MB0_D10 L2 DQB0_9 DQB1_9 AT1 MB1_D10
MA0_D11 G40 DQA0_10 DQA1_10 A19 MA1_D11 MB0_D11 L1 DQB0_10 DQB1_10 AT2 MB1_D11
MA0_D12 E40 DQA0_11 DQA1_11 B17 MA1_D12 MB0_D12 N2 DQB0_11 DQB1_11 AV2 MB1_D12
MA0_D13 D41 DQA0_12 DQA1_12 A16 MA1_D13 MB0_D13 P2 DQB0_12 DQB1_12 AW1 MB1_D13
MA0_D14 D40 DQA0_13 DQA1_13 B16 MA1_D14 MB0_D14 P1 DQB0_13 DQB1_13 AW2 MB1_D14
MA0_D15 C41 DQA0_14 DQA1_14 A15 MA1_D15 MB0_D15 R2 DQB0_14 DQB1_14 AY3 MB1_D15
MA0_D16 C40 DQA0_15 DQA1_15 B15 MA1_D16 MB0_D16 R1 DQB0_15 DQB1_15 BA3 MB1_D16
MA0_D17 B39 DQA0_16 DQA1_16 A14 MA1_D17 MB0_D17 T2 DQB0_16 DQB1_16 AY4 MB1_D17
MA0_D18 A39 DQA0_17 DQA1_17 B14 MA1_D18 MB0_D18 T1 DQB0_17 DQB1_17 BA4 MB1_D18
MA0_D19 B38 DQA0_18 DQA1_18 B13 MA1_D19 MB0_D19 U2 DQB0_18 DQB1_18 AY5 MB1_D19
MA0_D20 B36 DQA0_19 DQA1_19 A11 MA1_D20 MB0_D20 W1 DQB0_19 DQB1_19 BA7 MB1_D20
MA0_D21 A36 DQA0_20 DQA1_20 B11 MA1_D21 MB0_D21 W2 DQB0_20 DQB1_20 AY7 MB1_D21
MA0_D22 B35 DQA0_21 DQA1_21 A10 MA1_D22 MB0_D22 Y1 DQB0_21 DQB1_21 AY8 MB1_D22
MA0_D23 A35 DQA0_22 DQA1_22 B10 MA1_D23 MB0_D23 Y2 DQB0_22 DQB1_22 BA8 MB1_D23
MA0_D24 B33 DQA0_23 DQA1_23 B8 MA1_D24 MB0_D24 AB2 DQB0_23 DQB1_23 AR4 MB1_D24
MA0_D25 B32 DQA0_24 DQA1_24 A7 MA1_D25 MB0_D25 AC1 DQB0_24 DQB1_24 AR5 MB1_D25
MA0_D26 A32 DQA0_25 DQA1_25 B7 MA1_D26 MB0_D26 AC2 DQB0_25 DQB1_25 AU4 MB1_D26
MA0_D27 B31 DQA0_26 DQA1_26 A6 MA1_D27 MB0_D27 AD1 DQB0_26 DQB1_26 AU7 MB1_D27
MA0_D28 A30 DQA0_27 DQA1_27 A4 MA1_D28 MB0_D28 AF1 DQB0_27 DQB1_27 AN8 MB1_D28
MA0_D29 B29 DQA0_28 DQA1_28 B4 MA1_D29 MB0_D29 AF2 DQB0_28 DQB1_28 AV11 MB1_D29
MA0_D30 B28 DQA0_29 DQA1_29 A3 MA1_D30 MB0_D30 AG1 DQB0_29 DQB1_29 AU11 MB1_D30
MA0_D31 A28 DQA0_30 DQA1_30 B3 MA1_D31 MB0_D31 AG2 DQB0_30 DQB1_30 AP11 MB1_D31
DQA0_31 DQA1_31 DQB0_31 DQB1_31
<19> MA0_A[0..8] MA1_A[0..8] <19> <20> MB0_A[0..8] MB1_A[0..8] <20>
MA0_A0 G25 E15 MA1_A0 MB0_A0 R5 AE7 MB1_A0
MA0_A1 H25 MAA0_0 MAA1_0 H15 MA1_A1 MB0_A1 R8 MAB0_0 MAB1_0 AE8 MB1_A1
MA0_A2 E27 MAA0_1 MAA1_1 G13 MA1_A2 MB0_A2 N7 MAB0_1 MAB1_1 AG5 MB1_A2
MA0_A3 D27 MAA0_2 MAA1_2 D13 MA1_A3 MB0_A3 N4 MAB0_2 MAB1_2 AG4 MB1_A3
MA0_A4 D29 MAA0_3 MAA1_3 H11 MA1_A4 MB0_A4 L8 MAB0_3 MAB1_3 AJ4 MB1_A4
MA0_A5 H27 MAA0_4 MAA1_4 H13 MA1_A5 MB0_A5 N8 MAB0_4 MAB1_4 AG8 MB1_A5
MA0_A6 H23 MAA0_5 MAA1_5 H17 MA1_A6 MB0_A6 U8 MAB0_5 MAB1_5 AC8 MB1_A6
MA0_A7 E23 MAA0_6 MAA1_6 G17 MA1_A7 MB0_A7 U7 MAB0_6 MAB1_6 AC5 MB1_A7
C MA0_A8 D25 MAA0_7 MAA1_7 D15 MA1_A8 MB0_A8 R4 MAB0_7 MAB1_7 AE4 MB1_A8 C
H29 MAA0_8 MAA1_8 E11 L5 MAB0_8 MAB1_8 AJ8
MAA0_9 MAA1_9 MAB0_9 MAB1_9
MA0_WCK01 D33 A22 MA1_WCK01 MB0_WCK01 H1 AP1 MB1_WCK01

<19> MA0_WCK01 MA0_WCK01# E33 WCKA0_0 WCKA1_0 B21 MA1_WCK01# MA1_WCK01 <19> <20> MB0_WCK01 MB0_WCK01# J2 WCKB0_0 WCKB1_0 AP2 MB1_WCK01# MB1_WCK01 <20>
<19> MA0_WCK01# WCKA0B_0 WCKA1B_0 MA1_WCK01# <19> <20> MB0_WCK01# WCKB0B_0 WCKB1B_0 MB1_WCK01# <20>
MA0_WCK23 A34 A8 MA1_WCK23 MB0_WCK23 AB1 AN4 MB1_WCK23

<19> MA0_WCK23 MA0_WCK23# WCKA0_1 WCKA1_1 MA1_WCK23# MA1_WCK23 <19> <20> MB0_WCK23 MB0_WCK23# WCKB0_1 WCKB1_1 MB1_WCK23# MB1_WCK23 <20>
B34 B9 AA2 AN5
<19> MA0_WCK23# WCKA0B_1 WCKA1B_1 MA1_WCK23# <19> <20> MB0_WCK23# WCKB0B_1 WCKB1B_1 MB1_WCK23# <20>
MA0_EDC0 G38 B24 MA1_EDC0 MB0_EDC0 F2 AL1 MB1_EDC0

<19> MA0_EDC0 MA0_EDC1 EDCA0_0 EDCA1_0 MA1_EDC1 MA1_EDC0 <19> <20> MB0_EDC0 MB0_EDC1 EDCB0_0 EDCB1_0 MB1_EDC1 MB1_EDC0 <20>
F41 A18 M2 AU2
B37 B12 V1 BA6
A31 B6 AD2 AV7
<19> MA0_EDC3 EDCA0_3 EDCA1_3 MA1_EDC3 <19> <20> MB0_EDC3 EDCB0_3 EDCB1_3 MB1_EDC3 <20>
MA0_DBI#0 J38 B25 MA1_DBI#0 MB0_DBI#0 E2 AK2 MB1_DBI#0

<19> MA0_DBI#0 MA0_DBI#1 DDBIA0_0 DDBIA1_0 MA1_DBI#1 MA1_DBI#0 <19> <20> MB0_DBI#0 MB0_DBI#1 DDBIB0_0 DDBIB1_0 MB1_DBI#1 MB1_DBI#0 <20>
F40 B18 M1 AV1
<19> MA0_DBI#1 MA0_DBI#2 DDBIA0_1 DDBIA1_1 MA1_DBI#2 MA1_DBI#1 <19> <20> MB0_DBI#1 MB0_DBI#2 DDBIB0_1 DDBIB1_1 MB1_DBI#2 MB1_DBI#1 <20>
A38 A12 V2 AY6
<19> MA0_DBI#2 MA0_DBI#3 B30 DDBIA0_2 DDBIA1_2 B5 MA1_DBI#3 MA1_DBI#2 <19> <20> MB0_DBI#2 MB0_DBI#3 AE2 DDBIB0_2 DDBIB1_2 AV9 MB1_DBI#3 MB1_DBI#2 <20>
<19> MA0_DBI#3 DDBIA0_3 DDBIA1_3 MA1_DBI#3 <19> <20> MB0_DBI#3 DDBIB0_3 DDBIB1_3 MB1_DBI#3 <20>
MA0_ADBI H21 H19 MA1_ADBI MB0_ADBI W8 AA8 MB1_ADBI

<19> MA0_ADBI ADBIA0 ADBIA1 MA1_ADBI <19> <20> MB0_ADBI ADBIB0 ADBIB1 MB1_ADBI <20>
MA0_CS# H31 E7 MA1_CS# MB0_CS# G5 AL8 MB1_CS#

<19> MA0_CS# CSA0B_0 CSA1B_0 MA1_CS# <19> <20> MB0_CS# CSB0B_0 CSB1B_0 MB1_CS# <20>
MA0_CAS# D23 D17 MA1_CAS# MB0_CAS# U4 AC4 MB1_CAS#

<19> MA0_CAS# MA0_RAS# CASA0B CASA1B MA1_RAS# MA1_CAS# <19> <20> MB0_CAS# MB0_RAS# CASB0B CASB1B MB1_RAS# MB1_CAS# <20>
D21 D19 W4 AA4
B
<19> MA0_RAS# MA0_WE# G29 RASA0B RASA1B D11 MA1_WE# MA1_RAS# <19> <20> MB0_RAS# MB0_WE# L4 RASB0B RASB1B AJ7 MB1_WE# MB1_RAS# <20> B
<19> MA0_WE# WEA0B WEA1B MA1_WE# <19> <20> MB0_WE# WEB0B WEB1B MB1_WE# <20>
MA0_CKE G21 E19 MA1_CKE MB0_CKE W5 AA7 MB1_CKE

<19> MA0_CKE CKEA0 CKEA1 MA1_CKE <19> <20> MB0_CKE CKEB0 CKEB1 MB1_CKE <20>
MA0_CLK E31 D7 MA1_CLK MB0_CLK G4 AL5 MB1_CLK
<19> MA0_CLK MA0_CLK# CLKA0 CLKA1 MA1_CLK# MA1_CLK <19> <20> MB0_CLK MB0_CLK# CLKB0 CLKB1 MB1_CLK# MB1_CLK <20>
D31 D9 J4 AL4
<19> MA0_CLK# CLKA0B CLKA1B MA1_CLK# <19> <20> MB0_CLK# CLKB0B CLKB1B MB1_CLK# <20>
RV39 1 DIS@ 2 120_0402_1% K15 K17 MA_VREFD RV1633 1 DIS@ 2 120_0402_1% R10 U10 MB_VREFD
MEM_CALRA MVREFDA MEM_CALRB MVREFDB
MA_VRAMRST#_G L32 MB_VRAMRST#_G AM11

DRAM_RSTA REV 0.91 DRAM_RSTB
REV 0.91
2160896088A1R16M_FCBGA769P-NH 2160896088A1R16M_FCBGA769P-NH
+1.35VSDGPU
+1.35VSDGPU
1
RV36 RV37 RV1641 RV1642
1
49.9_0402_1% 10_0402_1% DIS@ 49.9_0402_1% 10_0402_1%
1 DIS@ 2 2 DIS@ 1 MA_VRAMRST#_G RV32 1 DIS@ 2 2 DIS@ 1 MB_VRAMRST#_G DIS@
<19> MA_VRAMRST# <20> MB_VRAMRST#
40.2_0402_1% RV1635
40.2_0402_1%
2
1
1
1 1 1 1
2
DIS@ DIS@ @ MA_VREFD DIS@ DIS@ @
CV96 RV38 CV97 CV2720 RV1643 CV2719 MB_VREFD
120P_0402_50V8J 5.1K_0402_1% 68P_0402_50V8J 120P_0402_50V8J 5.1K_0402_1% 68P_0402_50V8J
1
2 2 DIS@ 2 2
1 DIS@
2
1
RV35 CV486 DIS@ 1 DIS@
100_0402_1% 1U_0402_6.3V6K RV1634 CV487
100_0402_1% 1U_0402_6.3V6K
2
2
A
2 A
2
Place close to GPU (within 25mm) Place close to GPU (within 25mm)
and place componment within (5mm) close to each other and place componment within (5mm) close to each other

R17M-P1-50/70_(4/9)_MEM
Custom 1.A
5 4 3 2 1
5 4 3 2 1
MA0_D[0..31]
<18> MA0_D[0..31]
<18> MA0_A[0..8]
MA0_A[0..8]
A0 Channel A1 Channel
MA1_D[0..31]
<18> MA1_D[0..31]
MA1_A[0..8]
<18> MA1_A[0..8]
UV1001 @ MF=0 UV1002 @ MF=1
MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
A4 MA0_D6 A4 MA1_D7
MA0_EDC0 C2 DQ24 DQ0 A2 MA0_D7 MA1_EDC0 C2 DQ24 DQ0 A2 MA1_D5
<18> MA0_EDC0 MA0_EDC1 EDC0 EDC3 DQ25 DQ1 MA0_D5 <18> MA1_EDC0 MA1_EDC1 EDC0 EDC3 DQ25 DQ1 MA1_D6
C13 B4 C13 B4
<18> MA0_EDC1 MA0_EDC2 EDC1 EDC2 DQ26 DQ2 MA0_D4 <18> MA1_EDC1 MA1_EDC3 EDC1 EDC2 DQ26 DQ2 MA1_D4
R13 B2 R13 B2
+1.35VSDGPU <18> MA0_EDC2 MA0_EDC3 EDC2 EDC1 DQ27 DQ3 MA0_D2 +1.35VSDGPU <18> MA1_EDC3 MA1_EDC2 EDC2 EDC1 DQ27 DQ3 MA1_D3
R2 E4 Byte 0 R2 E4 Byte 0
<18> MA0_EDC3 EDC3 EDC0 DQ28 DQ4 MA0_D0 <18> MA1_EDC2 EDC3 EDC0 DQ28 DQ4 MA1_D2
E2 E2
DQ29 DQ5 F4 MA0_D1 DQ29 DQ5 F4 MA1_D0
D RV79 MA0_DBI#0 D2 DQ30 DQ6 F2 MA0_D3 RV1637 MA1_DBI#0 D2 DQ30 DQ6 F2 MA1_D1 D
<18> MA0_DBI#0 MA0_DBI#1 DBI0# DBI3# DQ31 DQ7 MA0_D10 <18> MA1_DBI#0 MA1_DBI#1 DBI0# DBI3# DQ31 DQ7 MA1_D8
60.4_0402_1% D13 A11 60.4_0402_1% D13 A11
MA0_CLK <18> MA0_DBI#1 MA0_DBI#2 DBI1# DBI2# DQ16 DQ8 MA0_D9 MA1_CLK <18> MA1_DBI#1 MA1_DBI#3 DBI1# DBI2# DQ16 DQ8 MA1_D10
1 DIS@ 2 P13 A13 1 DIS@ 2 P13 A13
<18> MA0_DBI#2 MA0_DBI#3 DBI2# DBI1# DQ17 DQ9 MA0_D11 <18> MA1_DBI#3 MA1_DBI#2 DBI2# DBI1# DQ17 DQ9 MA1_D9
P2 B11 P2 B11
<18> MA0_DBI#3 DBI3# DBI0# DQ18 DQ10 MA0_D8 <18> MA1_DBI#2 DBI3# DBI0# DQ18 DQ10 MA1_D11
RV80 B13 RV1636 B13
60.4_0402_1% MA0_CLK J12 DQ19 DQ11 E11 MA0_D15 Byte 1 60.4_0402_1% MA1_CLK J12 DQ19 DQ11 E11 MA1_D12 Byte 1
MA0_CLK# <18> MA0_CLK MA0_CLK# CK DQ20 DQ12 MA0_D12 MA1_CLK# <18> MA1_CLK MA1_CLK# CK DQ20 DQ12 MA1_D13
1 DIS@ 2 J11 E13 1 DIS@ 2 J11 E13
<18> MA0_CLK# MA0_CKE CK# DQ21 DQ13 MA0_D14 <18> MA1_CLK# MA1_CKE CK# DQ21 DQ13 MA1_D15
J3 F11 J3 F11
<18> MA0_CKE CKE# DQ22 DQ14 MA0_D13 <18> MA1_CKE CKE# DQ22 DQ14 MA1_D14
F13 F13
DQ23 DQ15 U11 MA0_D23 DQ23 DQ15 U11 MA1_D31
MA0_A2 H11 DQ8 DQ16 U13 MA0_D21 MA1_A4 H11 DQ8 DQ16 U13 MA1_D30
MA0_A5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 MA0_D22 MA1_A3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 MA1_D28
MA0_A4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MA0_D20 MA1_A2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MA1_D29
MA0_A3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 MA0_D19 Byte 2 MA1_A5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 MA1_D25 Byte 3
BA3/A3 BA1/A5 DQ12 DQ20 N13 MA0_D18 BA3/A3 BA1/A5 DQ12 DQ20 N13 MA1_D26
DQ13 DQ21 M11 MA0_D16 DQ13 DQ21 M11 MA1_D24
MA0_A7 K4 DQ14 DQ22 M13 MA0_D17 MA1_A0 K4 DQ14 DQ22 M13 MA1_D27
MA0_A1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MA0_D24 MA1_A6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MA1_D16
MA0_A0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MA0_D26 MA1_A7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MA1_D17
MA0_A6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MA0_D25 MA1_A1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MA1_D19
MA0_A8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MA0_D27 MA1_A8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MA1_D18
A12/RFU/NC DQ3 DQ27 N4 MA0_D28 Byte 3 A12/RFU/NC DQ3 DQ27 N4 MA1_D21 Byte 2
A5 DQ4 DQ28 N2 MA0_D29 A5 DQ4 DQ28 N2 MA1_D22
U5 VPP/NC DQ5 DQ29 M4 MA0_D31 +1.35VSDGPU U5 VPP/NC DQ5 DQ29 M4 MA1_D20
VPP/NC DQ6 DQ30 M2 MA0_D30 VPP/NC DQ6 DQ30 M2 MA1_D23
DQ7 DQ31 DQ7 DQ31
RV134 2 DIS@ 1 1K_0402_1% J1 +1.35VSDGPU RV131 2 DIS@ 1 1K_0402_1% J1 +1.35VSDGPU
RV474 2 DIS@ 1 1K_0402_1% J10 MF RV475 2 DIS@ 1 1K_0402_1% J10 MF
RV123 1 DIS@ 2 120_0402_1% J13 SEN B1 RV132 1 DIS@ 2 120_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
MA0_ADBI J4 VDDQ M1 MA1_ADBI J4 VDDQ M1
<18> MA0_ADBI MA0_RAS# ABI# VDDQ <18> MA1_ADBI MA1_CAS# ABI# VDDQ
G3 P1 G3 P1
<18> MA0_RAS# MA0_CS# RAS# CAS# VDDQ <18> MA1_CAS# MA1_WE# RAS# CAS# VDDQ
G12 T1 G12 T1
<18> MA0_CS# MA0_CAS# CS# WE# VDDQ <18> MA1_WE# MA1_RAS# CS# WE# VDDQ
L3 G2 L3 G2
<18> MA0_CAS# MA0_WE# CAS# RAS# VDDQ <18> MA1_RAS# MA1_CS# CAS# RAS# VDDQ
L12 L2 L12 L2
<18> MA0_WE# WE# CS# VDDQ <18> MA1_CS# WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
MA0_WCK01# D5 VDDQ H3 MA1_WCK01# D5 VDDQ H3
Can NC For GDDR5 Spec. <18> MA0_WCK01# MA0_WCK01 WCK01# WCK23# VDDQ <18> MA1_WCK01# MA1_WCK01 WCK01# WCK23# VDDQ
D4 K3 Can NC For GDDR5 Spec. D4 K3
<18> MA0_WCK01 WCK01 WCK23 VDDQ <18> MA1_WCK01 WCK01 WCK23 VDDQ
M3 M3
C MA0_WCK23# VDDQ MA1_WCK23# VDDQ C
P5 P3 P5 P3
<18> MA0_WCK23# MA0_WCK23 WCK23# WCK01# VDDQ <18> MA1_WCK23# MA1_WCK23 WCK23# WCK01# VDDQ
+1.35VSDGPU P4 T3 +1.35VSDGPU P4 T3
<18> MA0_WCK23 WCK23 WCK01 VDDQ <18> MA1_WCK23 WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
RV52 1 DIS@ 2 2.37K_0402_1% VREFD1_A0 VREFD1_A0 A10 VDDQ E10 RV486 1 DIS@ 2 2.37K_0402_1% VREFD1_A1 VREFD1_A1 A10 VDDQ E10
RV53 1 DIS@ 2 5.49K_0402_1% VREFD2_A0 U10 VREFD VDDQ N10 RV487 1 DIS@ 2 5.49K_0402_1% VREFD2_A1 U10 VREFD VDDQ N10
VREFC_A0 J14 VREFD VDDQ B12 VREFC_A1 J14 VREFD VDDQ B12
DIS@ VREFC VDDQ D12 DIS@ VREFC VDDQ D12
CV394 1 2 1U_0402_6.3V6K VDDQ F12 CV407 1 2 1U_0402_6.3V6K VDDQ F12
VDDQ H12 VDDQ H12
MA_VRAMRST# J2 VDDQ K12 MA_VRAMRST# J2 VDDQ K12
<18> MA_VRAMRST# RESET# VDDQ RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
+1.35VSDGPU VDDQ T12 +1.35VSDGPU VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
RV478 1 DIS@ 2 2.37K_0402_1% VREFD2_A0 K1 VSS VDDQ B14 RV482 1 DIS@ 2 2.37K_0402_1% VREFD2_A1 K1 VSS VDDQ B14
RV479 1 DIS@ 2 5.49K_0402_1% B5 VSS VDDQ D14 RV483 1 DIS@ 2 5.49K_0402_1% B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
DIS@ L5 VSS VDDQ M14 DIS@ L5 VSS VDDQ M14
CV403 1 2 1U_0402_6.3V6K T5 VSS VDDQ P14 CV405 1 2 1U_0402_6.3V6K T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
D10 VSS VDDQ D10 VSS VDDQ
G10 VSS G10 VSS
L10 VSS A1 L10 VSS A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
+1.35VSDGPU T10 VSS VSSQ E1 +1.35VSDGPU T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
K14 VSS VSSQ R1 K14 VSS VSSQ R1
RV480 1 DIS@ 2 2.37K_0402_1% VREFC_A0 +1.35VSDGPU VSS VSSQ U1 RV484 1 DIS@ 2 2.37K_0402_1% VREFC_A1 +1.35VSDGPU VSS VSSQ U1
RV481 1 DIS@ 2 5.49K_0402_1% VSSQ H2 RV485 1 DIS@ 2 5.49K_0402_1% VSSQ H2
G1 VSSQ K2 G1 VSSQ K2
DIS@ L1 VDD VSSQ A3 DIS@ L1 VDD VSSQ A3
CV404 1 2 1U_0402_6.3V6K G4 VDD VSSQ C3 CV406 1 2 1U_0402_6.3V6K G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
B B
P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12
VSSQ E12 VSSQ E12
VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
H5GC4H24AJR-R0C_BGA170 H5GC4H24AJR-R0C_BGA170
Decoupling Caps for single-sided Decoupling Caps for Clamshell

1x 10uF /per DRAM 1x 10uF /per Clamshell DRAM
8x 0.1uF /per DRAM
+1.35VSDGPU +1.35VSDGPU +1.35VSDGPU
CV238
CV242
CV243
CV247
CV248
CV392
CV396
CV397
CV398
CV414
CV415
CV416
CV417
CV418
CV419
CV420
CV421
CV155
CV157
CV158
CV198
CV210
CV211
CV213
CV230
CV233
CV235
CV465
CV460
CV461
CV462
CV463
CV464
CV466
CV467
CV468
CV452
CV453
CV454
CV455
CV456
CV457
CV458
CV459
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A A
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
R17M-P1-50/70_(5/9)_CH A
Custom
5 4 3 2 1
5 4 3 2 1
MB0_D[0..31]
<18> MB0_D[0..31]
<18> MB0_A[0..8]
MB0_A[0..8]
B0 Channel B1 Channel
MB1_D[0..31]
<18> MB1_D[0..31]
MB1_A[0..8]
<18> MB1_A[0..8]
UV1003 @ MF=0 UV1004 @ MF=1
MF=0 MF=1 MF=1 MF=0 MF=0 MF=1 MF=1 MF=0
A4 MB0_D15 A4 MB1_D7
MB0_EDC1 C2 DQ24 DQ0 A2 MB0_D14 MB1_EDC0 C2 DQ24 DQ0 A2 MB1_D5
<18> MB0_EDC1 MB0_EDC0 EDC0 EDC3 DQ25 DQ1 MB0_D12 <18> MB1_EDC0 MB1_EDC1 EDC0 EDC3 DQ25 DQ1 MB1_D6
C13 B4 C13 B4
<18> MB0_EDC0 MB0_EDC2 EDC1 EDC2 DQ26 DQ2 MB0_D13 <18> MB1_EDC1 MB1_EDC2 EDC1 EDC2 DQ26 DQ2 MB1_D4
R13 B2 R13 B2
+1.35VSDGPU <18> MB0_EDC2 MB0_EDC3 EDC2 EDC1 DQ27 DQ3 MB0_D10 +1.35VSDGPU <18> MB1_EDC2 MB1_EDC3 EDC2 EDC1 DQ27 DQ3 MB1_D3
R2 E4 Byte 1 R2 E4 Byte 0
<18> MB0_EDC3 EDC3 EDC0 DQ28 DQ4 MB0_D9 <18> MB1_EDC3 EDC3 EDC0 DQ28 DQ4 MB1_D2
E2 E2
DQ29 DQ5 F4 MB0_D11 DQ29 DQ5 F4 MB1_D0
D RV473 MB0_DBI#1 D2 DQ30 DQ6 F2 MB0_D8 RV1638 MB1_DBI#0 D2 DQ30 DQ6 F2 MB1_D1 D
<18> MB0_DBI#1 MB0_DBI#0 DBI0# DBI3# DQ31 DQ7 MB0_D0 <18> MB1_DBI#0 MB1_DBI#1 DBI0# DBI3# DQ31 DQ7 MB1_D8
60.4_0402_1% D13 A11 60.4_0402_1% D13 A11
MB0_CLK <18> MB0_DBI#0 MB0_DBI#2 DBI1# DBI2# DQ16 DQ8 MB0_D1 MB1_CLK <18> MB1_DBI#1 MB1_DBI#2 DBI1# DBI2# DQ16 DQ8 MB1_D10
1 DIS@ 2 P13 A13 1 DIS@ 2 P13 A13
<18> MB0_DBI#2 MB0_DBI#3 DBI2# DBI1# DQ17 DQ9 MB0_D3 <18> MB1_DBI#2 MB1_DBI#3 DBI2# DBI1# DQ17 DQ9 MB1_D9
P2 B11 P2 B11
<18> MB0_DBI#3 DBI3# DBI0# DQ18 DQ10 MB0_D2 <18> MB1_DBI#3 DBI3# DBI0# DQ18 DQ10 MB1_D11
RV472 B13 RV1639 B13
60.4_0402_1% MB0_CLK J12 DQ19 DQ11 E11 MB0_D6 Byte 0 60.4_0402_1% MB1_CLK J12 DQ19 DQ11 E11 MB1_D12 Byte 1
MB0_CLK# <18> MB0_CLK MB0_CLK# CK DQ20 DQ12 MB0_D5 MB1_CLK# <18> MB1_CLK MB1_CLK# CK DQ20 DQ12 MB1_D13
1 DIS@ 2 J11 E13 1 DIS@ 2 J11 E13
<18> MB0_CLK# MB0_CKE CK# DQ21 DQ13 MB0_D7 <18> MB1_CLK# MB1_CKE CK# DQ21 DQ13 MB1_D15
J3 F11 J3 F11
<18> MB0_CKE CKE# DQ22 DQ14 MB0_D4 <18> MB1_CKE CKE# DQ22 DQ14 MB1_D14
F13 F13
DQ23 DQ15 U11 MB0_D23 DQ23 DQ15 U11 MB1_D20
MB0_A2 H11 DQ8 DQ16 U13 MB0_D21 MB1_A4 H11 DQ8 DQ16 U13 MB1_D22
MB0_A5 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 MB0_D22 MB1_A3 K10 BA0/A2 BA2/A4 DQ9 DQ17 T11 MB1_D21
MB0_A4 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MB0_D20 MB1_A2 K11 BA1/A5 BA3/A3 DQ10 DQ18 T13 MB1_D23
MB0_A3 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 MB0_D19 Byte 2 MB1_A5 H10 BA2/A4 BA0/A2 DQ11 DQ19 N11 MB1_D16 Byte 2
BA3/A3 BA1/A5 DQ12 DQ20 N13 MB0_D18 BA3/A3 BA1/A5 DQ12 DQ20 N13 MB1_D19
DQ13 DQ21 M11 MB0_D16 DQ13 DQ21 M11 MB1_D17
MB0_A7 K4 DQ14 DQ22 M13 MB0_D17 MB1_A0 K4 DQ14 DQ22 M13 MB1_D18
MB0_A1 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MB0_D24 MB1_A6 H5 A8/A7 A10/A0 DQ15 DQ23 U4 MB1_D25
MB0_A0 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MB0_D26 MB1_A7 H4 A9/A1 A11/A6 DQ0 DQ24 U2 MB1_D24
MB0_A6 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MB0_D25 MB1_A1 K5 A10/A0 A8/A7 DQ1 DQ25 T4 MB1_D26
MB0_A8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MB0_D27 MB1_A8 J5 A11/A6 A9/A1 DQ2 DQ26 T2 MB1_D27
A12/RFU/NC DQ3 DQ27 N4 MB0_D28 Byte 3 A12/RFU/NC DQ3 DQ27 N4 MB1_D29 Byte 3
A5 DQ4 DQ28 N2 MB0_D29 A5 DQ4 DQ28 N2 MB1_D31
U5 VPP/NC DQ5 DQ29 M4 MB0_D31 +1.35VSDGPU U5 VPP/NC DQ5 DQ29 M4 MB1_D30
VPP/NC DQ6 DQ30 M2 MB0_D30 VPP/NC DQ6 DQ30 M2 MB1_D28
DQ7 DQ31 DQ7 DQ31
RV116 2 DIS@ 1 1K_0402_1% J1 +1.35VSDGPU RV117 2 DIS@ 1 1K_0402_1% J1 +1.35VSDGPU
RV476 2 DIS@ 1 1K_0402_1% J10 MF RV477 2 DIS@ 1 1K_0402_1% J10 MF
RV120 1 DIS@ 2 120_0402_1% J13 SEN B1 RV121 1 DIS@ 2 120_0402_1% J13 SEN B1
ZQ VDDQ D1 ZQ VDDQ D1
VDDQ F1 VDDQ F1
MB0_ADBI J4 VDDQ M1 MB1_ADBI J4 VDDQ M1
<18> MB0_ADBI MB0_RAS# ABI# VDDQ <18> MB1_ADBI MB1_CAS# ABI# VDDQ
G3 P1 G3 P1
<18> MB0_RAS# MB0_CS# RAS# CAS# VDDQ <18> MB1_CAS# MB1_WE# RAS# CAS# VDDQ
G12 T1 G12 T1
<18> MB0_CS# MB0_CAS# CS# WE# VDDQ <18> MB1_WE# MB1_RAS# CS# WE# VDDQ
L3 G2 L3 G2
<18> MB0_CAS# MB0_WE# CAS# RAS# VDDQ <18> MB1_RAS# MB1_CS# CAS# RAS# VDDQ
L12 L2 L12 L2
<18> MB0_WE# WE# CS# VDDQ <18> MB1_CS# WE# CS# VDDQ
B3 B3
VDDQ D3 VDDQ D3
VDDQ F3 VDDQ F3
MB0_WCK01# D5 VDDQ H3 MB1_WCK01# D5 VDDQ H3
Can NC For GDDR5 Spec. <18> MB0_WCK01# MB0_WCK01 WCK01# WCK23# VDDQ <18> MB1_WCK01# MB1_WCK01 WCK01# WCK23# VDDQ
D4 K3 Can NC For GDDR5 Spec. D4 K3
<18> MB0_WCK01 WCK01 WCK23 VDDQ <18> MB1_WCK01 WCK01 WCK23 VDDQ
M3 M3
C MB0_WCK23# VDDQ MB1_WCK23# VDDQ C
P5 P3 P5 P3
<18> MB0_WCK23# MB0_WCK23 WCK23# WCK01# VDDQ <18> MB1_WCK23# MB1_WCK23 WCK23# WCK01# VDDQ
+1.35VSDGPU P4 T3 +1.35VSDGPU P4 T3
<18> MB0_WCK23 WCK23 WCK01 VDDQ <18> MB1_WCK23 WCK23 WCK01 VDDQ
E5 E5
VDDQ N5 VDDQ N5
RV498 1 DIS@ 2 2.37K_0402_1% VREFD1_B0 VREFD1_B0 A10 VDDQ E10 RV492 1 DIS@ 2 2.37K_0402_1% VREFD1_B1 VREFD1_B1 A10 VDDQ E10
RV499 1 DIS@ 2 5.49K_0402_1% VREFD2_B0 U10 VREFD VDDQ N10 RV493 1 DIS@ 2 5.49K_0402_1% VREFD2_B1 U10 VREFD VDDQ N10
VREFC_B0 J14 VREFD VDDQ B12 VREFC_B1 J14 VREFD VDDQ B12
DIS@ VREFC VDDQ D12 DIS@ VREFC VDDQ D12
CV413 1 2 1U_0402_6.3V6K VDDQ F12 CV410 1 2 1U_0402_6.3V6K VDDQ F12
VDDQ H12 VDDQ H12
MB_VRAMRST# J2 VDDQ K12 MB_VRAMRST# J2 VDDQ K12
<18> MB_VRAMRST# RESET# VDDQ RESET# VDDQ
M12 M12
VDDQ P12 VDDQ P12
+1.35VSDGPU VDDQ T12 +1.35VSDGPU VDDQ T12
VDDQ G13 VDDQ G13
H1 VDDQ L13 H1 VDDQ L13
RV494 1 DIS@ 2 2.37K_0402_1% VREFD2_B0 K1 VSS VDDQ B14 RV488 1 DIS@ 2 2.37K_0402_1% VREFD2_B1 K1 VSS VDDQ B14
RV495 1 DIS@ 2 5.49K_0402_1% B5 VSS VDDQ D14 RV489 1 DIS@ 2 5.49K_0402_1% B5 VSS VDDQ D14
G5 VSS VDDQ F14 G5 VSS VDDQ F14
DIS@ L5 VSS VDDQ M14 DIS@ L5 VSS VDDQ M14
CV411 1 2 1U_0402_6.3V6K T5 VSS VDDQ P14 CV408 1 2 1U_0402_6.3V6K T5 VSS VDDQ P14
B10 VSS VDDQ T14 B10 VSS VDDQ T14
D10 VSS VDDQ D10 VSS VDDQ
G10 VSS G10 VSS
L10 VSS A1 L10 VSS A1
P10 VSS VSSQ C1 P10 VSS VSSQ C1
+1.35VSDGPU T10 VSS VSSQ E1 +1.35VSDGPU T10 VSS VSSQ E1
H14 VSS VSSQ N1 H14 VSS VSSQ N1
K14 VSS VSSQ R1 K14 VSS VSSQ R1
RV496 1 DIS@ 2 2.37K_0402_1% VREFC_B0 +1.35VSDGPU VSS VSSQ U1 RV490 1 DIS@ 2 2.37K_0402_1% VREFC_B1 +1.35VSDGPU VSS VSSQ U1
RV497 1 DIS@ 2 5.49K_0402_1% VSSQ H2 RV491 1 DIS@ 2 5.49K_0402_1% VSSQ H2
G1 VSSQ K2 G1 VSSQ K2
DIS@ L1 VDD VSSQ A3 DIS@ L1 VDD VSSQ A3
CV412 1 2 1U_0402_6.3V6K G4 VDD VSSQ C3 CV409 1 2 1U_0402_6.3V6K G4 VDD VSSQ C3
L4 VDD VSSQ E3 L4 VDD VSSQ E3
C5 VDD VSSQ N3 C5 VDD VSSQ N3
R5 VDD VSSQ R3 R5 VDD VSSQ R3
C10 VDD VSSQ U3 C10 VDD VSSQ U3
R10 VDD VSSQ C4 R10 VDD VSSQ C4
D11 VDD VSSQ R4 D11 VDD VSSQ R4
G11 VDD VSSQ F5 G11 VDD VSSQ F5
L11 VDD VSSQ M5 L11 VDD VSSQ M5
B B
P11 VDD VSSQ F10 P11 VDD VSSQ F10
G14 VDD VSSQ M10 G14 VDD VSSQ M10
L14 VDD VSSQ C11 L14 VDD VSSQ C11
VDD VSSQ R11 VDD VSSQ R11
VSSQ A12 VSSQ A12
VSSQ C12 VSSQ C12
VSSQ E12 VSSQ E12
VSSQ N12 VSSQ N12
VSSQ R12 VSSQ R12
170-BALL VSSQ U12 170-BALL VSSQ U12
VSSQ H13 VSSQ H13
SGRAM GDDR5 VSSQ K13 SGRAM GDDR5 VSSQ K13
VSSQ A14 VSSQ A14
VSSQ C14 VSSQ C14
VSSQ E14 VSSQ E14
VSSQ N14 VSSQ N14
VSSQ R14 VSSQ R14
VSSQ U14 VSSQ U14
VSSQ VSSQ
H5GC4H24AJR-R0C_BGA170 H5GC4H24AJR-R0C_BGA170
Decoupling Caps for single-sided Decoupling Caps for Clamshell

8x 0.1uF /per DRAM
+1.35VSDGPU +1.35VSDGPU +1.35VSDGPU
CV445
CV440
CV441
CV442
CV443
CV444
CV446
CV447
CV448
CV432
CV433
CV434
CV435
CV436
CV437
CV438
CV439
CV422
CV423
CV424
CV425
CV426
CV427
CV428
CV429
CV430
CV431
CV481
CV482
CV480
CV485
CV477
CV483
CV484
CV479
CV478
CV469
CV470
CV471
CV472
CV473
CV474
CV475
CV476
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
A A
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
R17M-P1-50/70_(6/9)_CH B
Custom
5 4 3 2 1
5 4 3 2 1
UV1G @ UV1H @
D symbol7 symbol8 D
AY32 AY22
TX2P_DPB0P TX2P_DPD0P
BA32 BA22
TX2M_DPB0N TX2M_DPD0N
AY31 AY21
BA31 BA21
AY30 AY20
BA30 BA20
AY28 AY19
TXCBP_DPB3P TXCDP_DPD3P
BA28 BA19
TXCBM_DPB3N TXCDM_DPD3N
AY11
AUX1P
BA11
AUX1N
AM21 AY10
DDCAUX3P DDC1CLK
AP21 BA10
DDCAUX3N DDC1DATA
C C
UV1O @
symbol15
AY18
TX2P_DPE0P AY36 AY27
BA18 TX5P_DPA0P TX5P_DPC0P
TX2M_DPE0N BA36 BA27
AY16 TX5M_DPA0N TX5M_DPC0N
TXCEP_DPE3P AY33 AY24
BA14 TXCAP_DPA3P TXCCP_DPC3P
TXCEM_DPE3N BA33 BA24
TXCAM_DPA3N TXCCM_DPC3N
AP19
AUX2P
AM19
BA12 AUX2N
B AUX_ZVSS B
2
AU27 DIS@
DDCAUX5P RV372 AR23 AV19
AV27 150_0402_1% DDCAUX4P DDC2CLK
DDCAUX5N AP23 AU19
REV 0.91
1
DDCAUX4N REV 0.91 DDC2DATA

REV 0.91
2160896088A1R16M_FCBGA769P-NH 2160896088A1R16M_FCBGA769P-NH 2160896088A1R16M_FCBGA769P-NH
Data Book:need
config even if not
use display function
A A

R17M-P1-50/70_(7/9)_DISPLAY
Custom 1.A
5 4 3 2 1
5 4 3 2 1
+VGA_CORE SCL:22u x2, 1u x4 +VDDCI
SCL:22u x8, 1u x7 R17M-P1-50/70:45A,25W UV1I @ VDDCI+VDD_08:128b/12A,64b/7.5A UV1L @

N13 symbol9 L13 symbol12
N15 VDDC#0 VDDCI#0 L17 A2 J39
N21 VDDC#1 VDDCI#1 L21 A5 VSS#0 VSS#58 J40
CV62
CV323
CV324
CV325
CV326
CV327
CV328
CV329
CV330
CV317
CV318
CV319
CV320
CV321
CV322
CV334
CV333
CV332
CV331
CV336
CV335
N23 VDDC#2 VDDCI#2 L25 A9 VSS#1 VSS#59 J41
1 1 1 1 1 1 1 1 1 1 1
2
2
N29 VDDC#3 VDDCI#3 L29 A13 VSS#2 VSS#60 K21
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
N31 VDDC#4 VDDCI#4 N11 A17 VSS#3 VSS#61 K25
DIS@
DIS@
R13 VDDC#5 VDDCI#5 U11 A21 VSS#4 VSS#62 K29
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
1
2 2 2 2 2 2 2 R15 VDDC#6 VDDCI#6 AA11 2 2 2 2 A25 VSS#5 VSS#63 K40
D R21 VDDC#7 VDDCI#7 AE11 A29 VSS#6 VSS#64 L3 D
R23 VDDC#8 VDDCI#8 A33 VSS#7 VSS#65 L7
R29 VDDC#9 A37 VSS#8 VSS#66 L11
R31 VDDC#10 A40 VSS#9 VSS#67 L15
U13 VDDC#11 B1 VSS#10 VSS#68 L19
U15 VDDC#12 B40 VSS#11 VSS#69 L23
U21 VDDC#13 B41 VSS#12 VSS#70 L27
U23 VDDC#14 C5 VSS#13 VSS#71 L31
W13 VDDC#17 C11 VSS#16 VSS#74 N1
W23 VDDC#20 C17 VSS#19 VSS#77 N17
W29 VDDC#21 C19 VSS#20 VSS#78 N19
W31 VDDC#22 C21 VSS#21 VSS#79 N25
AA13 VDDC#23 C23 VSS#22 VSS#80 N27
AA29 VDDC#27 C31 VSS#26 VSS#84 R3
AA31 VDDC#28 C33 VSS#27 VSS#85 R7
AC13 VDDC#29 C35 VSS#28 VSS#86 R11
AC23 VDDC#32 E1 VSS#31 VSS#89 R25
AE13 VDDC#35 E9 VSS#34 VSS#92 R35
AE15 VDDC#36 E13 VSS#35 VSS#93 R39
AE21 VDDC#37 E17 VSS#36 VSS#94 U1
AG13 VDDC#41 E39 VSS#40 VSS#98 U19
AG15 VDDC#42 E41 VSS#41 VSS#99 U25
AG21 VDDC#43 G3 VSS#42 VSS#100 U27
AJ13 VDDC#47 G19 VSS#46 VSS#104 W3
C VDDC#49 VSS#48 VSS#106 C
AJ17 G27 W11
AJ25 VDDC#53 J1 VSS#52 VSS#110 W27
AJ27 VDDC#54 J3 VSS#53 VSS#111 W39
AJ29 VDDC#55 J5 VSS#54 VSS#112 AA1
AJ31 VDDC#56 J34 VSS#55 VSS#113 AA3
AL13 VDDC#57 J37 VSS#56 VSS#114
AL15 VDDC#58 VSS#57
AL17 VDDC#59 REV 0.91
AL19 VDDC#60
AL21 VDDC#61 2160896088A1R16M_FCBGA769P-NH
AL23 VDDC#62
AL25 VDDC#63 C3
AL27 VDDC#64 FB_VMEMIO AV13 GPU_VDDCI_SEN
VDDC#65 FB_VDDCI GPU_VDDC_SEN GPU_VDDCI_SEN <48>
AL29 AR13
VDDC#66 FB_VDDC GPU_VSS_SEN_L GPU_VDDC_SEN <48> UV1M @
AL31 AU13
VDDC#67 FB_VSS GPU_VSS_SEN_L <48>
REV 0.91 symbol13
AA5 AN40
2160896088A1R16M_FCBGA769P-NH AA10 VSS#115 VSS#171 AN41
AA17 VSS#116 VSS#172 AP13
AA19 VSS#117 VSS#173 AP17
AA25 VSS#118 VSS#174 AR3
AC3 VSS#122 VSS#178 AR21
0.24uH,<0.15mohm AC7 VSS#123 VSS#179 AR25
+1.35VSDGPU CRB no use, reserve first +1.8VSDGPU AC11 VSS#124 VSS#180 AR27
AC17 VSS#125 VSS#181 AR31
UV1N @ RV1632 AC19 VSS#126 VSS#182 AR35
SCL:22u x2, 1u x10 128b/14A,64b/8A symbol14 1A SCL:1u x3 0_0805_5% AC25 VSS#127 VSS#183 AR39
K11 AM15 1 DIS@ 2 AC27 VSS#128 VSS#184 AU1
K13 VMEMIO#0 VDD_18#0 AP15 AC39 VSS#129 VSS#185 AU3
K19 VMEMIO#1 VDD_18#1 AR15 AE1 VSS#130 VSS#186 AU9
CV347
CV348
CV337
CV338
CV339
CV340
CV341
CV342
CV343
CV344
CV345
CV346
CV349
CV350
CV351
K23 VMEMIO#2 VDD_18#2 AE3 VSS#131 VSS#187 AU23
1 1 1 1 1 1 1 1 1 1 VMEMIO#3 1 1 1 VSS#132 VSS#188
2
K27 AE5 AU29

DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
K31 VMEMIO#4 AE10 VSS#133 VSS#189 AW3
L10 VMEMIO#5 AE17 VSS#134 VSS#190 AW5
22U_0603_6.3V6M
22U_0603_6.3V6M
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2 2 2 2 2 2 2 2 2 2 N10 VMEMIO#6 2 2 2 AE19 VSS#135 VSS#191 AW7

W10 VMEMIO#7 +VDDCI AE25 VSS#136 VSS#192 AW9
B B
AC10 VMEMIO#8 AE27 VSS#137 VSS#193 AW11
AG10 VMEMIO#9 Merge to VDDCI SCL:1u x7 AE32 VSS#138 VSS#194 AW13
VMEMIO#10 AC32 AE35 VSS#139 VSS#195 AW15
VDD_08#0 AG32 AE39 VSS#140 VSS#196 AW17
VDD_08#1 AG35 AG3 VSS#141 VSS#197 AW19
CV352
CV353
CV354
CV355
CV356
CV357
CV358
VDD_08#2 AJ32 AG7 VSS#142 VSS#198 AW21
VDD_08#3 1 1 1 1 1 1 1 VSS#143 VSS#199
AJ34 AG11 AW23
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
DIS@
VDD_08#4 AL34 AG17 VSS#144 VSS#200 AW25
VDD_08#5 AG19 VSS#145 VSS#201 AW27
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
W32 2 2 2 2 2 2 1U_0402_6.3V6K 2 AG25 VSS#146 VSS#202 AW29

VDD_08 AG27 VSS#147 VSS#203 AW31
AG39 VSS#148 VSS#204 AW33
AM23 AG40 VSS#149 VSS#205 AW35
VSS AM17 AG41 VSS#150 VSS#206 AW37
VSS AJ1 VSS#151 VSS#207 AW39
REV 0.91
AJ3 VSS#152 VSS#208 AY1
2160896088A1R16M_FCBGA769P-NH AJ10 VSS#154 VSS#210 AY9
AL3 VSS#158 VSS#214 AY29
AL32 VSS#162 VSS#218 BA2
AN1 VSS#165 VSS#221 BA17
+1.8VSDGPU AN7 VSS#167 VSS#223 BA29
CV316 DIS@ UV1J @ VSS#170 VSS#226
1U_0402_6.3V6K 13mA symbol10
1 2 AM13 N35 REV 0.91
TSVDD DPLUS
DG:Thermal Die Temperature 2160896088A1R16M_FCBGA769P-NH
J8
TEMPIN0 N34
SCL:No need to implement. DMINUS
A J7 A
TEMPINRETURN
U38 GPIO_28_FDO Fan Drive Out option
N38 GPIO_28_FDO
TS_A
2
REV 0.91 RV21

@ 10K_0201_5%
2160896088A1R16M_FCBGA769P-NH
1

R17M-P1-50/70_(8/9)_PWR/GND
Custom
5 4 3 2 1
5 4 3 2 1
PCIE_RST_L APU_PCIE_RST#
APU AND PLT_RST_VGA# PERSTB
AGPIO71 PE_GPIO0 GATE GPU
EGPIO93 PE_GPIO1
D D
Delay 2ms
AND
GATE
+3VS +3VSDGPU
Power Up VGA_ON
PWR SW 1
Ready within 20ms
+1.8VALW +1.8VSDGPU
VGA_ON
DL SW 2
Delay 3ms
VGA_ON
+3VSDGPU
Delay 3ms
+1.8VSDGPU
Delay +3VSDGPU 7ms
VGA_ON_B B+ +VGA_CORE
+3VSDGPU
AND VGA_ON_B
PWM 3 DGPU_PWROK
VGA_ON GATE Delay +3VSDGPU 7ms
+VGA_CORE
Driver
+VDDCI
C
+VDDCI 3 C
B+ +1.35VSDGPU
DGPU_PWROK DGPU_PWROK
LD O 4
+1.35VSDGPU
For AMD R17M-P1-50/70 VRAM Only AMD GPU PN
Memory ID/Vendor/Size Memory PN R3(ABO!) A0 Memory PN R3(ABO!) A1 Memory PN R3(ABO!) B0 Memory PN R3(ABO!) B1 R17M-P1-50 PN R1(ROH)
UV1 RX540@
000 UV1001 V4G_S@ UV1002 V4G_S@ UV1003 V4G_S@ UV1004 V4G_S@
SAMSUNG
256M x32 S IC 216-0905018 A1 R17M-P1-50 FCBGA 769P 0FA
S IC D5 256M32 K4G80325FB-HC03 FBGA ABO! S IC D5 256M32 K4G80325FB-HC03 FBGA ABO! S IC D5 256M32 K4G80325FB-HC03 FBGA ABO! S IC D5 256M32 K4G80325FB-HC03 FBGA ABO! SA0000ALV10
SA000094R30 SA000094R30 SA000094R30 SA000094R30
R17M-P1-70 PN R1(ROH)
B
001 UV1001 V4G_H@ UV1002 V4G_H@ UV1003 V4G_H@ UV1004 V4G_H@ B
UV1 RX550@
HYNIX
256M x32
S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO! S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO! S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO! S IC D5 256M32 H5GC8H24MJR-T2C BGA ABO!
SA00009ZG20 SA00009ZG20 SA00009ZG20 SA00009ZG20
S IC 216-0905004 A1 R17M-P1-70 FCBGA 769P 0FA
SA0000ALX10
010 UV1001 V2G_S@ UV1002 V2G_S@ UV1003 V2G_S@ UV1004 V2G_S@
SAMSUNG R17M-G1-70 PN R1(ROH)

128M x32 UV1 RX560@
S IC D5 128M32 K4G41325FE-HC28 FBGA ABO! S IC D5 128M32 K4G41325FE-HC28 FBGA ABO! S IC D5 128M32 K4G41325FE-HC28 FBGA ABO! S IC D5 128M32 K4G41325FE-HC28 FBGA ABO!
SA00009TT30 SA00009TT30 SA00009TT30 SA00009TT30
011 UV1001 V2G_H@ UV1002 V2G_H@ UV1003 V2G_H@ UV1004 V2G_H@

S IC 216-0909004 A1 R17M-G1-70 FCBGA 0FA
SA0000APU00
HYNIX
128M x32
S IC D5 128M322.5G H5GC4H24AJR-T2C ABO! S IC D5 128M322.5G H5GC4H24AJR-T2C ABO! S IC D5 128M322.5G H5GC4H24AJR-T2C ABO! S IC D5 128M322.5G H5GC4H24AJR-T2C ABO!
SA000085V70 SA000085V70 SA000085V70 SA000085V70
100 UV1001 V4G_M@ UV1002 V4G_M@ UV1003 V4G_M@ UV1004 V4G_M@
MICRON
256M x32
S IC D5 256M32 MT51J256M32HF-60A ABO! S IC D5 256M32 MT51J256M32HF-60A ABO! S IC D5 256M32 MT51J256M32HF-60A ABO! S IC D5 256M32 MT51J256M32HF-60A ABO!
SA000096K30 SA000096K30 SA000096K30 SA000096K30
A A

R17M-P1-50/70_(9/9)_NOTE
1.A
5 4 3 2 1
5 4 3 2 1
+EC_VCC
R1564 EA@
1
+3VLP +EC_VCC L44 +EC_VCCA
JP2 @ FBM-11-160808-601-T_0603 +RTC_APU_R
1 2 1 2 R1562
1 2
Ra 100K_0402_5%
1
0.1U_0201_10V6K
C1255
0.1U_0201_10V6K
C1256
0.1U_0201_10V6K
C1257
0.1U_0201_10V6K
C1258
1000P_0402_50V7K
C1261
1000P_0402_50V7K
C1259
JUMP_43X39 2 15K_0402_1%
2
2 2 2 2 1 1 C1262 SD034150280 D Q91
0.1U_0201_10V6K AD_BID EC_RTCRST 2 2N7002K_SOT23-3
PVT For EA G
1
@ @ 1 S
1 1 1 1 2 2 2
R1564 C1269 R1563
Rb
3
ECAGND @ 10K_0402_5% 0.1U_0201_10V6K R1564 VX@ 10K_0402_5%
111
125
@
22
33
96
67
9
1
2
VCC0
VCC_LPC
VCC
VCC
VCC
VCC
AVCC
D D
33K_0402_1%
GATEA20 1 21 LAN_PWR_EN
<9> GATEA20 KBRST#_R GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_BEEP# LAN_PWR_EN <28> SD034330280
1 RS@ 2 2 23
<9> KBRST# KBRST#/GPIO01 BEEP#/GPIO10 FAN_PWM1 EC_BEEP# <34>
SERIRQ 3 26 PVT For VX
<10,33> SERIRQ LPC_FRAME# 4 SERIRQ EC_FAN_PWM/GPIO12 27 FAN_PWM2 FAN_PWM1 <35>
R3973 PWM Output
<9,10,33> LPC_FRAME# LPC_AD3 LPC_FRAME# AC_OFF/GPIO13 FAN_PWM2 <35>
0_0402_5% 5
<10,33> LPC_AD3 LPC_AD2 7 LPC_AD3
<10,33> LPC_AD2 LPC_AD1 LPC_AD2 BATT_TEMP
8 63
LPC_CLK0_EC <10,33> LPC_AD1 LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 VCIN1_BATT_DROP BATT_TEMP <39>
1 2 1 2 10 64
C1263 @EMC@ R1560 @EMC@
<10,33> LPC_AD0 LPC_AD0LPC & MISC VCIN1_BATT_DROP/AD1/GPIO39 65 ADP_I VCIN1_BATT_DROP <39>
LPC_CLK0_EC ADP_I/AD2/GPIO3A AD_BID ADP_I <39,40>
22P_0402_50V8J 10_0402_1% 12 AD Input 66
<9,10> LPC_CLK0_EC LPC_RST# 13 CLK_PCI_EC AD_BID/AD3/GPIO3B 75
<9,33> LPC_RST# EC_RST# 37 PCIRST#/GPIO05 AD4/GPIO42 76 LAN_WAKE#
EC_RST# <35> EC_RST# EC_SCI# EC_RST# AD5/GPIO43 LAN_WAKE# <28>
1 2 20
<9> EC_SCI# WLAN_ON 38 EC_SCI#/GPIO0E +3VS
C819 1000P_0402_50V7K
EMC@ <29> WLAN_ON CLKRUN#/GPIO1D
68 EC_MUTE# R1565 1 @ 2 10K_0402_5%
DA0/GPIO3C 70 TP_I2C_INT# R116 1 2 1K_0402_5%
LPC_RST# <33> KSI[0..7] DA Output EN_DFAN1/DA1/GPIO3D TP_SENOFF#
@
1 @ 2 KSI0 55 71
56 KSI0/GPIO30 DA2/GPIO3E 72 KBL_EN TP_SENOFF# <33>
R207 100K_0402_5% KSI1
KSI1/GPIO31 DA3/GPIO3F KBL_EN <33>
1 2 @EMC@ KSI2 57 +EC_VCC
C1279 100P_0402_50V8J KSI3 58 KSI2/GPIO32 83 EC_TYPEC_EN
KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A EC_TYPEC_EN <32> EC_SMB_DA1
KSI4 59 84 R1577 1 2 2.2K_0402_5%
KSI5 60 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B 85 EC_MUTE# EC_SMB_CK1 R1574 1 2 2.2K_0402_5%
61 KSI5/GPIO35 PSCLK2/GPIO4C 86 USB_EN EC_MUTE# <34> LID_SW#
KSI6 PS2 Interface R344 1 2 47K_0402_5%
KSI6/GPIO36 PSDAT2/GPIO4D TP_CLK USB_EN <31>
KSI7 62 87
<33> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <33>
TP_DATA <33> PS2
KSO0 39 88
KSO1 40 KSO0/GPIO20 TP_DATA/GPIO4F
KSO2 41 KSO1/GPIO21
KSO3 42 KSO2/GPIO22 97 USB_CB
KSO3/GPIO23 ENKBL/GPXIOA00 GPU_ACIN USB_CB <31>
KSO4 43 98
44 KSO4/GPIO24 WOL_EN/GPXIOA01 99 0.95VS_PWR_EN# GPU_ACIN <16> BATT_TEMP 1 2
KSO5
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 9022_PH1 0.95VS_PWR_EN# <25>
C1265 100P_0402_50V8J
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 9022_PH1 <39>
ACIN 1 2
KSO8 47 KSO7/GPIO27
KSO8/GPIO28 SPI Device Interface EC_RTCRST
C1266 100P_0402_50V8J
C KSO9 48 119 C
KSO10 49 KSO9/GPIO29 MISO/GPIO5B 120 BT_ON EC_RSMRST# R3907 1 @ 2 47K_0402_5%
KSO10/GPIO2A MOSI/GPIO5C TYPEC_3A_1P5A# BT_ON <29>
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 SYSON R1675 1 2 100K_0402_5%
KSO11/GPIO2B TYPEC_3A_1P5A# <32> 3V_EN
KSO12 51 128 R940 1 2 1M_0402_5%
KSO13 52 KSO12/GPIO2C SPICS#/GPIO5A
KSO14 53 KSO13/GPIO2D
KSO15 54 KSO14/GPIO2E 73 USB_CHARGE_2A
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 USB_CHARGE_2A <31>
KSO16 81 74 VGATE VGATE <44>
KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 BATT_4S
KSO17/GPIO49 GPIO50 90 BATT_BLUE_LED# BATT_4S <40>
BATT_CHG_LED#/GPIO52 CAPS_LED# BATT_BLUE_LED# <31>
91
EC_SMB_CK1 77 CAPS_LED#/GPIO53 92 PWR_LED# CAPS_LED# <33>
<39,40> EC_SMB_CK1 EC_SMB_DA1 EC_SMB_CLK1/GPIO44 GPIO PWR_LED#/GPIO54 BATT_AMB_LED# PWR_LED# <31>
78 93
<39,40> EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 BATT_AMB_LED# <31>
79 95 SYSON
<8,16> EC_SMB_CK2 EC_SMB_DA2 80 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 121 VR_ON SYSON <42>
<8,16> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 0.95_1.8VALW_PWREN VR_ON <44,45>
127
DPWROK_EC/GPIO59 0.95_1.8VALW_PWREN <43>
SM Bus
SLP_S3# 6 100 EC_RSMRST#
<9> SLP_S3# TP_I2C_INT# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 USB_SELCDP EC_RSMRST# <9>
<33> TP_I2C_INT# USB_CEN GPIO07 GPXIOA04 9022_VCIN USB_SELCDP <31>
15 102 9022_VCIN <39>
<31> USB_CEN TP_3V_EN 16 GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 103 EC_THERM
<33> TP_3V_EN WL_OFF# GPIO0A VCOUT1_PROCHOT#/GPXIOA06
17 104 MAINPWON
<29> WL_OFF# WLAN_WAKE# GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 MAINPWON <35,39,41>
18 105 BKOFF#
<29> WLAN_WAKE# CAM_EN 19 GPIO0C BKOFF#/GPXIOA08 106 LAN_GPO BKOFF# <27>
<27> CAM_EN AC_PRESENT/GPIO0D GPIO GPO GPXIOA09 3V_EN_R_EC LAN_GPO <28>
SPOK 25 107
<41> SPOK FAN_SPEED1 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 5V_393_EN
<35> FAN_SPEED1 FAN_SPEED2 29 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 5V_393_EN <25>
<35> FAN_SPEED2 EC_TX 30 FANFB1/GPIO15
<29> EC_TX EC_RX EC_TX/GPIO16
SYS_PWRGD_EC@1.8VALW <29> EC_RX
31
EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01
110 ACIN
ACIN <40>
SYS_PWRGD_EC 32 112 EC_ON EC_THERM 1 RS@ 2
EC can be OD pin <9> SYS_PWRGD_EC PWR_SUSP_LED# PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <41> APU_PROCHOT# <8,16,44,45>
for reduce Level shifter 34 114 ON/OFFBTN#
<31> PWR_SUSP_LED# NUM_LED# SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFFBTN# <33>
36 GPI 115 R1690
<33> NUM_LED# NUM_LED#/GPIO1A LID_SW#/GPXIOD04 LID_SW# <33>
116 SUSP# 0_0402_5%
SUSP#/GPXIOD05 117 SUSP# <25,40,42>
ENBKL
GPXIOD06 ENBKL <8>
118
PBTN_OUT# 122 PECI/GPXIOD07
<9> PBTN_OUT# SLP_S5# 123 PBTN_OUT#/GPIO5D 124
B <9> SLP_S5# PM_SLP_S4#/GPIO5E V18R/VCC_IO2 +EC_VCC B
AGND
GND
GND
GND
GND
GND
11
24
35
94
113
69
U44
KB9022QD_LQFP128_14X14 L43
FBM-11-160808-601-T_0603
2 1
ECAGND
20mil MAINPWON 1 2 3V_EN
3V_EN <41>
D2012 @
RB751V-40_SOD323-2
3V_EN_R_EC R3926 1 2 1K_0402_5%
SPOK 1 2 EC_RSMRST#
D2013 @
RB751V-40_SOD323-2
1 2 SYS_PWRGD_EC
D2014 @
RB751V-40_SOD323-2
A A

EC ENE-KB9022
C 1.A
5 4 3 2 1
A B C D E
+5VALW R3998 +5VALW_COM

VIN 5V and 3.3V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm 0_0402_5%
+3VS 2 1
U2
J7 JP@
1 14 +3VS_LS
+3VALW VIN1 VOUT1
1 2 2 13
C12 @ VIN1 VOUT1 JUMP_43X118
1
@
20mils 0.5A @
1 RS@ 2 3VS_ON 1U_0402_6.3V6K 3 12 1 2 C13 C2734 C2733
<24,40,42> SUSP# ON1 CT1
C10 0.1U_0201_10V6K 0.1U_0201_10V6K U2614 @ 0.1U_0201_10V6K
R1667 4 11 560P_0402_50V7K 2 1 2 5 1 1 2
+5VALW VBIAS GND IN OUT
0_0402_5%
1 RS@ 2 5VS_ON 5 10 1 2 2
ON2 CT2 C9 +5VS GND
R1668 6 9 330P_0402_50V7K J8 JP@ 5V_393_EN 4 3
+5VALW VIN2 VOUT2 +5VS_LS <24> 5V_393_EN EN OC
0_0402_5% 1 2 7 8
C11 @ VIN2 VOUT2 SY6288C20AAC_SOT23-5
1
1U_0402_6.3V6K 15 JUMP_43X118
1 GPAD 1
C14
EM5209VF_DFN14_3X2 0.1U_0201_10V6K
2
Q135 Q2513
+APU_CORE_NB AO3416L_SOT23-3 AO3416L_SOT23-3 +APU_CORE_FCH
VIN 1.8V and 1.5V (VBIAS=5V),IMAX(per channel)=6A,Rds=18mohm 1 3 3 1
D
D
S
1 1 1 1 1
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
+1.8VS C2618
C2668
C2667
C2621
C2620
U3
J9 JP@ 4.7U_0402_6.3V6M
G
G
2
2
1 14 +1.8VS_LS CORE_NB_GATE
+1.8VALW VIN1 VOUT1 2 2 2 2 2
R1669 1 2 2 13 1
0_0402_5% C24 @ VIN1 VOUT1 JUMP_43X79
SUSP# 1 RS@ 2 1.8VS_ON 1U_0402_6.3V6K 3 12 1 2 C26 Q2515 Q2514
ON1 CT1 C21 +0.775VALW AO3416L_SOT23-3 AO3416L_SOT23-3
0.1U_0201_10V6K
4 11 330P_0402_50V7K 2
+5VALW VBIAS GND 1 3 3 1
D
D
S
5 10 1 1
ON2 CT2 C2619 C2622
6 9 4.7U_0402_6.3V6M 4.7U_0402_6.3V6M
G
G
2
2
7 VIN2 VOUT2 8 0.775VALW_GATE
VIN2 VOUT2 2 2
15
GPAD
EM5209VF_DFN14_3X2 +5VALW_COM
+APU_CORE_NB U2608A +5VALW_COM
8
TLC3702IDRG4 SOIC 8P
SB00000ZN00 3 SA000088800
P
S TR AO4354 1N SOIC-8 + 1 1 2 CORE_NB_GATE 1 @ 2
+0.775MOS 2 O R3903 R3890
-
G
+0.95VALW U4 +0.95VS +5VALW_COM 1K_0402_5% 1K_0402_5%
AO4354 1N SOIC8
4
8 1 U2608B +5VALW_COM
8
1 7 2 TLC3702IDRG4 SOIC 8P
4.7U_0402_6.3V6M
C939
1U_0402_6.3V6K
6 3 C46 5 SA000088800
C940 1 1
P
4.7U_0402_6.3V6M 5 + 7 1 2 0.775VALW_GATE 1 @ 2
2 6 O R3902 R3891 2
-
G
2 1K_0402_5% 1K_0402_5%
4
2
2 @ 2
4
R3936 @
+5VALW 10K_0402_5%
1
1 2 0.95VS_GATE
R1674 1
4.7K_0402_5%
1
C16
D 0.1U_0201_10V6K
2 2 +5VALW_COM
<24> 0.95VS_PWR_EN#
G
S Q84
2
2N7002K_SOT23-3
3
+3VALW R2635 +0.775VALW

100K_0402_5%
6
1
D
R2634 2 G
100K_0402_5% Q2516B S
DMN66D0LDW-7_SOT363-6
1
3
+0.775MOS
1
S5_MUX_CTRL 5 G
D
<9> S5_MUX_CTRL
2
Q2516A S
DMN66D0LDW-7_SOT363-6 R2636
4
100K_0402_5%
1
RV406
3 0_0402_5% 3
2 @ 1
+3VALW
+1.8VALW TO +1.8VSDGPU
UV5
MC74VHC1G08DFT2G_SC70-5
5
RV807 DIS@
10K_0402_5% 1
P
IN1 VGA_ON
<9> PE_GPIO1
1 DIS@ 2 4 IMAX(per channel)=6A,Rds=18mohm
2 O
1 UV8
2
IN2 DIS@
1
RV913 CV2698 1 14
3
100K_0402_5% DIS@ CV626 0.1U_0201_10V6K 2 VIN1 VOUT1 13

@ 0.22U_0402_16V7K 2 VIN1 VOUT1
2 3 12
1
ON1 CT1
Vih 2.1V
Delay 2ms 4 11
+5VALW VBIAS GND
RV1629 33K_0402_5% 40mil(1.013A)
VGA_ON 1 DIS@ 2 5 10 DIS@ 1 2
+3VALW ON2 CT2 2200P_0402_50V7K CV622 +1.8VSDGPU
6 9 J2503 JP@
0.22U_0402_16V7K
+1.8VALW VIN2 VOUT2 +1.8VSDGPU_LS

UV6 @1 2 7 8 1 2
CV625 DIS@
MC74VHC1G08DFT2G_SC70-5 CV2699 1U_0402_6.3V6K VIN2 VOUT2 1 2

1 2
5
DIS@ 15 JUMP_43X39
VGA_ON GPAD
RV833 1 Vih 1.2V CV31 DIS@
P
IN1 4 VGA_ON_B
33K_0402_5%
O VGA_ON_B <48> Delay 3ms EM5209VF_DFN14_3X2 0.1U_0201_10V6K
1 DIS@ 2 2 2 1
+3VSDGPU IN2
G
1 2 DIS@
@
3
DIS@ CV2701 CV2722

0.22U_0402_16V7K Vih 2.1V 1U_0402_6.3V6K
2 Delay 7ms 1
+3VS TO +3VSDGPU
+3VS +3VSDGPU
4 20mil(10mA) 4
UV7 DIS@
5 1
IN OUT
1 1
CV620 2 CV621
4.7U_0402_6.3V6M GND 4.7U_0402_6.3V6M
DIS@ 4 3 DIS@
2 EN OC 2
SY6288C20AAC_SOT23-5
VGA_ON Security Classification Compal Secret Data Compal Electronics, Inc.

DC INTERFACE
Custom 1.A
A B C D E
5 4 3 2 1
+3VS +1.2V_HDMI +5VS_DISP

8 1 U73 W=40mils ZZZ
VIN VOUT
1
7 2 +5VS 3
NC ADJ R4012 OUT
6 3 4.99K_0402_1% 1 1
10U_0603_6.3V6M
+5VALW VDD PGOOD IN
1
5 4 2 C543 HDMI_ROYALTY
EN GND GND
2
9 0.1U_0201_10V6K ROYALTY HDMI W/LOGO+HDCP
C2738
PGND 2
RO0000003HM
10U_0603_6.3V6M
1
U1302 2 AP2330W-7_SC59-3 45@
1 1
1U_0402_6.3V6K
RT9041E-15GQW_WDFN8_2X2 R4013
10K_0402_1%
C2736
C2737
2 2
D D
2
+3VS
HDMI_CLK- R756 1 @ 2 0_0402_5% HDMI_R_CLK- For HDMI DDC Capacitance Leakage issue
Improve Intra-pair Skew on CLK+/-
+1.2V_HDMI
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
L2512
1 1 1 SM070003V00
2 1 2
D2016 EMC@
C2746
C2749 HDMI_HPD_CONN 6 3
C2744
C2745
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.01U_0402_16V7K
0.01U_0402_16V7K
1 1 1 1 1 0.01U_0402_16V7K 1
2 2 2 3 4 @ 3.3P_0402_50V8
I/O4 I/O2
1
U2615
C2739
C2740
C2748
HDMI_PRE 27 1 HCM1012GH900BP_4P 5 2
C2741
C2742
C2743
2 2 2 2 2 2 VDD12 VDD33 HDMI_CLK+ HDMI_R_CLK+ +5VS_DISP VDD GND

30 24 R765 1 @ 2 0_0402_5%
11 VDD12 VDD33
43 VDDA12
46 VDDRX12 23 HDMI_TX2+ HDMI_SCLK_R 4 1 HDMI_SDATA_R
15 VDDRX12 OUT_D2p 22 HDMI_TX2- HDMI_TX0- R769 1 @ 2 0_0402_5% HDMI_R_TX0- I/O3 I/O1
18 VDDTX12 OUT_D2n AZC199-04S.R7G SOT23
37 VDDTX12 20 HDMI_TX1+
POWERSWITCH OUT_D1p 19 HDMI_TX1- L2513
SM070003V00
SC300002900
OUT_D1n
2
C505 1 2 .1U_0402_16V7K 38 2 1
<8> APU_DP1_P0 IN_D2p HDMI_TX0+
C506 1 2 .1U_0402_16V7K 39 17 R4020
<8> APU_DP1_N0 IN_D2n OUT_D0p HDMI_TX0-
16 @ 150_0402_1%
C507 1 2 .1U_0402_16V7K 41 OUT_D0n 3 4
<8> APU_DP1_P1 IN_D1p HDMI_CLK+ D2017
C508 1 2 .1U_0402_16V7K 42 14 @EMC@
<8> APU_DP1_N1 IN_D1n OUT_CKp
1
HDMI_CLK- HDMI_R_CLK- 1 1 HDMI_R_CLK-
13 10 9
C509 1 2 .1U_0402_16V7K 44 OUT_CKn HCM1012GH900BP_4P
<8> APU_DP1_P2 IN_D0p HDMI_SDATA HDMI_TX0+ HDMI_R_TX0+ HDMI_R_CLK+ HDMI_R_CLK+
C510 1 2 .1U_0402_16V7K 45 33 HDMI_SDATA <8> R779 1 @ 2 0_0402_5% 2 2 9 8
<8> APU_DP1_N2 IN_D0n SDA_SRC/AUXN 34 HDMI_SCLK
SCL_SRC/AUXP HDMI_SDATA_R HDMI_SCLK <8> HDMI_R_TX0- HDMI_R_TX0-
C511 1 2 .1U_0402_16V7K 47 8 4 4 7 7
<8> APU_DP1_P3 IN_CKp SDA_SNK HDMI_SCLK_R
C512 1 2 .1U_0402_16V7K 48 7
<8> APU_DP1_N3 IN_CKn SCL_SNK HDMI_R_TX0+ HDMI_R_TX0+
5 5 6 6
HDMI_TX1- R781 1 @ 2 0_0402_5% HDMI_R_TX1-
C HDMI_DCIN_EN 3 40 HDMI_HPLUG 3 3 C
HDMI_EQ 5 DCIN_EN HPD_SRC 21 HDMI_HPD_CONN
HDMI_I2C_ADDR EQ HPD_SNK L2514
31 SM070003V00 8
I2C_ADDR
2
+3VS 2 1
10 R4021 L05ESDL5V0NA-4 SLP2510P8
25 RSV1 32 HDMI_ID @
NC HDMI_ID 150_0402_1% SC300002C00
2
26 9 3 4
R4004 RSV2 HDMI_CEC 12
R4006 should be placed close to REXT pin. CEC_EN
1
10K_0402_5% D2018 @EMC@
HCM1012GH900BP_4P HDMI_R_TX1- 1 1 HDMI_R_TX1-
R4006 1 2 4.99K_0402_1% 36 29 T4958 10 9
4 REXT CSCL 28 T4959 HDMI_TX1+ R782 1 @ 2 0_0402_5% HDMI_R_TX1+
PDB CSDA
1
RESET# RESET# 35 HDMI_R_TX1+ 2 2 9 8 HDMI_R_TX1+

Enhance Vswing 6 RESETB
+1.2V_HDMI PRE HDMI_R_TX2- HDMI_R_TX2-
1 2 49 4 4 7 7
C2747 TESTMODEB EPAD
1U_0402_6.3V6K HDMI_TX2- R783 1 @ 2 0_0402_5% HDMI_R_TX2- HDMI_R_TX2+ 5 5 6 6 HDMI_R_TX2+
2 PS8409AQFN48GTR2-A0 QFN 48P_6X6 3 3

L2515
SA0000AC300 SM070003V00
2
2 1 8
R4022
@ 150_0402_1% L05ESDL5V0NA-4 SLP2510P8
3 4
SC300002C00
1
HDMI_DCIN_EN HDMI_PRE
HCM1012GH900BP_4P
DC coupling enable; Internal pull up, 3.3V I/O. Output pre-emphasis setting;Internal pull-up 3.3V I/O
1
HDMI_TX2+ R794 1 @ 2 0_0402_5% HDMI_R_TX2+

@ L: DC coupling input L: Pre-emphasis =2.5dB
R4005 H: Default,AC coupling input R4007 H: Default, No Pre-emphasis
4.7K_0402_5% 4.7K_0402_5% HDMI connector
JHDMI1
2
HDMI_HPD_CONN 19
+5VS_DISP +3VS 18 HP_DET
+5VS_DISP +5V
17
B HDMI_SDATA_R 16 DDC/CEC_GND B
HDMI_SCLK_R 15 SDA
+3VS 14 SCL
13 Reserved
HDMI_R_CLK- 12 CEC
CK-
1
+3VS 11
CK_shield
1
@ HDMI_R_CLK+ 10
R4009 R4014 R4015 R4016 R4017 HDMI_R_TX0- 9 CK+
D0-
1
4.7K_0402_5% Receiver equalization setting(Internal 150K PD) 2K_0402_5% 2K_0402_5% 47K_0402_5% @ 47K_0402_5% @ 8
@
HDMI_ID enable ; Internal pull down;3.3V I/O HDMI_R_TX0+ 7 D0_shield
(*) L: programmable EQ for channel loss up to 5.3dB L: Default, HDMI ID enable
2
HDMI_EQ R4008 HDMI_R_TX1- 6 D0+

D1-
2
( ) H: programmable EQ for channel loss up to 10dB 4.7K_0402_5% H: HDMI ID disable 5
D1_shield
1
HDMI_SDATA_R HDMI_SDATA HDMI_R_TX1+ 4 20

( ) M: programmable EQ for channel loss up to 14dB D1+ GND
2
@ HDMI_ID HDMI_R_TX2- 3 21
R4010 2 D2- GND 22
4.7K_0402_5% HDMI_SCLK_R HDMI_SCLK HDMI_R_TX2+ 1 D2_shield GND 23
D2+ GND
2
CCM_C100042GR019M298ZL
CONN@
+3VS DC232003500
+3VS
1
C
1
2 1 @ 2 HDMI_HPLUG
@
I2C Slave Address select i on; I nt er nal pull do wn; 3. 3V I / O B R281 150K_0402_5%
R4011 L: Default, Slave address 0x10-0x2F. E Q18
3
1
4.7K_0402_5% H: Alternat i ve sal ve addr ess 0x90- 0x9F, 0x D0- 0x DF. HDMI_HPD MMBT3904_NL_SOT23-3
<8> HDMI_HPD
@ R283
2
1
HDMI_I2C_ADDR @ 365K_0402_1%
R915@
2
100K_0402_5%
A A
2
HDMI_HPD R4018 1 2 0_0402_5% HDMI_HPLUG

HDMI REDRIVER (PS8409)
Custom 1.A
5 4 3 2 1
5 4 3 2 1
LCD POWER CIRCUIT

+3VS +LCDVDD Place closed to JEDP1 LED PANEL Conn.
U8 W=60mils
1U_0402_6.3V6K +LCDVDD
C2656
5 1 W=60mils JEDP1
IN OUT 1
1 +INVPW R_B+ 1
2 1 1 2
GND 3 2
4 3 C368 4 3
2 EN OC 1 4
0.1U_0201_10V6K 5
SY6288C20AAC_SOT23-5 C367 2 2@ C419 INVTPW M 6 5
<8> INVTPW M 6
4.7U_0402_6.3V6M 0.1U_0201_10V6K BKOFF# 7
2@ <24> BKOFF# EDP_HPD 7
D 8 D
<8> ENVDD EDP_HPD <8> EDP_HPD 8
R364 1 2 100K_0402_5% +LCDVDD 9
10 9
INVTPW M R393 1 @ 2 100K_0402_5% 11 10
12 11
@EMC@ 13 12
+INVPW R_B+ C549 1 2 220P_0402_50V7K EDP_AUXN_C 14 13
@EMC@ EDP_AUXP_C 15 14
BKOFF# C528 1 2 220P_0402_50V7K 16 15
EDP_TXP0_C 17 16
W=60mils R280 1 @ 2 10K_0402_5% EDP_TXN0_C 18 17
19 18
EDP_TXP1_C 20 19
L11 EDP_TXN1_C 21 20
HCB2012KF-221T30_0805 22 21
W=60mils 1 2 EDP_TXP2_C 23 22
+19VB_GFX EDP_TXN2_C 23
1 1 24
24
68P_0402_50V8J
C365 @EMC@
1000P_0402_50V7K
C364 @EMC@
25
EDP_TXP3_C 26 25
SM01000EJ00 3000ma 26
EDP_TXN3_C 27
220ohm@100mhz 2 2 +3VALW +3VS +3VS_CAM 27
DCR 0.04 28
29 28
30 29
R110 1 2 0_0603_5% 31 30
32 31
33 32
W=20mils 34 33
U45 @ 35 34
+3VS_CAM USB20_N3_CAMERA 35
1U_0402_6.3V6K
C102
5 1 36 41
C IN OUT USB20_P3_CAMERA 37 36 G1 42 C
1 37 G2
0.1U_0201_10V6K
C375
1U_0402_6.3V6K
C2735
2 1 1 For Camera 38 43
@ GND DMIC_CLK_R 39 38 G3 44
<34> DMIC_CLK_R DMIC_DATA 39 G4
4 3 @ 40 45
2 EN OC <34> DMIC_DATA 40 G5
SY6288C20AAC_SOT23-5 2 2 ACES_50398-04041-001
CONN@
<8> EDP_TXP0
C371 1
C372 1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
EDP_TXP0_C
EDP_TXN0_C
SP010013I00
<8> EDP_TXN0 <24> CAM_EN
C373 1 2 .1U_0402_16V7K EDP_TXP1_C
<8> EDP_TXP1
3
C374 1 2 .1U_0402_16V7K EDP_TXN1_C
<8> EDP_TXN1 EDP_TXP2_C
C2695 1 2 .1U_0402_16V7K
<8>
<8>
EDP_TXP2
EDP_TXN2
C2696 1 2 .1U_0402_16V7K EDP_TXN2_C
EDP_TXP3_C
Place closed to JEDP1
C2698 1 2 .1U_0402_16V7K
<8> EDP_TXP3 EDP_TXN3_C
C2697 1 2 .1U_0402_16V7K D2015
<8> EDP_TXN3
@EMC@
YSLC05CH_SOT23-3
1
C370 1 2 .1U_0402_16V7K EDP_AUXP_C
<8> EDP_AUXP
C369 1 2 .1U_0402_16V7K EDP_AUXN_C
<8> EDP_AUXN
B B
R3963 1 @ 2 0_0402_5% USB20_P3_CAMERA

<10> USB20_P3
L2511
4 3
1 2
MCM1012B900F06BP_4P
EMC@
R3964 1 @ 2 0_0402_5% USB20_N3_CAMERA
<10> USB20_N3
0402_0-ohm Co-Layout with 0504_Choke
A A

eDP/Camera/DMIC
Custom 1.A
5 4 3 2 1
5 4 3 2 1
LDO mode
W=60mil RL1 2 LDO@ 1 0_0603_5% W=60mil
LAN-RTL8411B +LAN_VDD +3V_LAN
W=60mil
LL1 SWR@
300mA 1.4A
IDC=1200mA
+REGOUT 1 2
2.2UH_HPC252012NF-2R2M_20%
4.7U_0402_6.3V6M
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
1U_0402_6.3V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
0.1U_0201_10V6K
+3VALW +3V_LAN
0.1U_0201_10V6K
CL1
CL28 SWR@
1 Using for Switch mode 2 1 1 1 1 1 1 1 1 1 1 1 1
CL2
CL3
CL4
CL5
CL6
CL7
CL8
CL9
4.7U_0402_6.3V6M
CL10
CL11
CL12
CL13
RL2 The trace length from
SWR@
0_0805_5% Lx to PIN48 (REGOUT)
2 1 2 2 2 2 2 2 2 2 2 2 2 2
LDO@
1 2 and from C to Lx must
D 60mil
UL1
60mil
< 200mils.
D
5 1
IN OUT Using for Switch mode
Place near Pin 3,8,33,46 Place near Pin 20 Place near Pin 11,32,48
2 11/27: P/N change to SH00000RT00
GND The trace length
4 3 ( S COIL 2.2UH +-20% from C to
EN OC HPC252012NF-2R2M 1.3A)
2 PIN34,35(VDDREG)
SY6288C20AAC_SOT23-5 must < 200mils.
CL14 @
1U_0402_6.3V6K LAN_PWR_EN
1 LAN_PWR_EN <24>
UL2
reserve EC_PME# pull high 100K to +3VALW_EC
From EC Power Manahement/Isolation
ISOLATEB 31
High active. RL3 2 RS@ 1 0_0402_5% LAN_PME# 39 ISOLATEBPIN
<24> LAN_WAKE# LANWAKEB
EN threshold voltage min:1.2V Card Reader
RL8 1 2 10K_0402_5% 15 SD_D0 RL9 1 @ 2 0_0402_5% SD_D0_R
typ:1.6V max:2.0V +3V_LAN SD_D0/MS_D1 SD_D1 SD_D1_R
Current limit threshold 1.5~2.8A PCI-Express 14 RL4 1 @ 2 0_0402_5%
CLK_PCIE_LAN 23 SD_D1 16 SD_CLK RL10 1 2 10_0402_5% SD_CLK_R
<10> CLK_PCIE_LAN CLK_PCIE_LAN# REFCLK_P SD_CLK/MS_D0 SD_CMD SD_CMD_R
+3V_LAN Rising time must >0.5ms and <100ms <10> CLK_PCIE_LAN#
24 17 RL5 1 @ 2 0_0402_5%
REFCLK_N SD_CMD/MS_D2 18 SD_D3 RL6 1 @ 2 0_0402_5% SD_D3_R
APU_PCIE_RST# SD_D3/MS_D3 SD_D2 SD_D2_R 2
30 19 RL7 1 @ 2 0_0402_5%
<9,15,29,30> APU_PCIE_RST# LAN_CLKREQ# 29 PERSTBPIN SD_D2/MS_CLK 28 SD_WP
PU at PCH side CL16
<9> LAN_CLKREQ# CLKREQBPIN SD_WP/MS_BS
5P_0402_50V8C
CL17 1 2 .1U_0402_16V7K PCIE_ARX_C_DTX_P0 25 1
<6> PCIE_ARX_DTX_P0 PCIE_ARX_C_DTX_N0 HSOP @EMC@
CL15,CL17 close to UL2 CL15 1 2 .1U_0402_16V7K 26
<6> PCIE_ARX_DTX_N0 21 HSON 42 SD_CD#
<6> PCIE_ATX_C_DRX_P0 HSIP SD_CD# close to pin17
<6> PCIE_ATX_C_DRX_N0
22 43
HSIN MS_CD#
Transceiver Interface
LAN_MIDI0+ 1
LAN_MIDI0- 2 MDIP0
LAN_MIDI1+ MDIN0
C +3V_LAN LAN_MIDI1-
LAN_MIDI2+
4
5 MDIP1
MDIN1 AVDD33
48 +3V_LAN
Protect cotact Card contact
C
6 11
+3V_LAN LAN_MIDI2- MDIP2 AVDD33
SWR mode 7 12 1400mA
RL11 1 SWR@2 0_0402_5% LAN_MIDI3+ 9 MDIN2 DVDD33 32
MDIP3 DVDD33 Write protect Write Enable
1
LAN_MIDI3- 10
MDIN3
RL12 RL13 1 LDO@ 2 0_0402_5% ENSWREG
RL14
(Lock) (Unlock)
10K_0402_5%
LDO mode 1K_0402_5% XTLI 44 33
@
GPO XTLO_R 1 2 XTLO 45 CKXTAL1 Clock DVDD10 3
+LAN_VDD Card Uninsert Open Open Open
CKXTAL2 AVDD10
2
8 300mA
AVDD10 Card insert Close Open Close
Regulator and Reference
+REGOUT 36 20
35 REG_OUT EVDD10
+3VS +3V_LAN VDDREG
YL1 ENSWREG 34 800mA
46 ENSWREG_H 13
SJ10000UP00 +LAN_VDD AVDD10 Card_3V3 +CARD_3V3
1
25MHZ_10PF_XRCGB25M000F2P34R0 LAN_RST
RL15 2 RL16 1 47
XTLI 1 3 XTLO_R 1K_0402_5% 2.49K_0402_1% RSET 27 +VDD33_18
1 3 TP@ T4950 DV33/18
NC NC
0.1U_0201_10V6K
4.7U_0402_6.3V6M
CL21
1 1 41
LED0
2
ISOLATEB RL17 1 @ 2GPO 38 1 1 1

2 4 <24> LAN_GPO LED1/GPO
CL20
15P_0402_50V8J 15P_0402_50V8J 0_0402_5% 37 LEDs CL22
LED3
2
CL18 CL19 40 0.1U_0201_10V6K

2 2 RL18 TP@ T4951 LED_CR 49
for disable PHY TP@ T4952 E_Pad 2 2 2
15K_0402_5%
reserve 0 ohm
1
Place near Pin 27
RTL8411B-CGT_QFN48_6X6
B LAN Connector B
TL1 JRJ45
LAN_TERMAL1
Card Reader Connector
24 MCT1 12 +CARD_3V3
LAN_MIDI0+ 2 TCT1 MCT1 23 RJ45_MIDI0+ RJ45_MIDI3- 8 GND
LAN_MIDI0- TD1+ MX1+ RJ45_MIDI0- PR4- JSD1
3 22 11
TD1- MX1- RJ45_MIDI3+ 7 GND
4 21 MCT2 PR4+ 6
LAN_MIDI1+ 5 TCT2 MCT2 20 RJ45_MIDI1+ RJ45_MIDI1- 6 SD_CMD_R 3 VDD
LAN_MIDI1- TD2+ MX2+ RJ45_MIDI1- PR2- SD_CLK_R CMD
4.7U_0402_6.3V6M
CL23
0.1U_0201_10V6K
CL24
6 19 WP is Normal Open 7
TD2- MX2- RJ45_MIDI2- 5 5 CLK
PR3- 1 1 VSS1
7 18 MCT3 8
LAN_MIDI2+ 8 TCT3 MCT3 17 RJ45_MIDI2+ RJ45_MIDI2+ 4 VSS2
LAN_MIDI2- 9 TD3+ MX3+ 16 RJ45_MIDI2- PR3+ +3V_LAN +3VS SD_D0_R 9
TD3- MX3- RJ45_MIDI1+
IC side 2 2 SD_D1_R DAT0
3 10
B88069X9231T203_4P5X3P2-2
PR2+ DAT1
1
10 15 MCT4 CL25 SD_D2_R 1
LAN_MIDI3+ 11 TCT4 MCT4 14 RJ45_MIDI3+ RJ45_MIDI0- 2
40mil 10P_0402_50V8J
40mil RL21 RL20 SD_WP SD_D3_R 2 DAT2
LAN_MIDI3- 12 TD4+ MX4+ 13 RJ45_MIDI3- PR1- 10 LANGND 2 1 RJ45_GND 100K_0402_5% 100K_0402_5%@ CD/DAT3
TD4- MX4- RJ45_MIDI0+ 1 GND 12
MESC5V02BD03_SOT23-3
PR1+ GND
1
1
1 9 Close to Card Reader CONN 13
GND GND
2
3
D QL1 SD_WP# 11
W/P
4
3
2
1
CL26 GST5009-E SD_WP# 2 2N7002K_SOT23-3 SD_CD# 4

.1U_0402_16V7K SP050006B10 RPL1 SINGA_2RJ1660-000111F @ G CD
2
@EMC@
75_0804_8P4R_1% CONN@ JPL1 S TAITW_PSDATQ09GLBS1NN4H1

JP1
Place close to TCT pin DC234009H00 JUMP_43X118 Connector side CONN@

2
3
DVT:02/17
EMC@
SP011611110
5
6
7
8
DL1
LANGND
RJ45_GND RL19
1
SD_CLK_R 1 @EMC@2 0_0402_5% 1 2

CL27 @EMC@
10P_0402_50V8J
Close to JREAD1 for EMI
A A

LAN RTL8411-CG
Custom 1.A
5 4 3 2 1
A B C D E
Wireless LAN
+3VS 60mil +3VS_WLAN
KEY E +3VS_WLAN
JNGFF1
1 2 1 2
R212 3 GND_1 3.3VAUX_2 4
1 1 1 1 <10> USB20_P2 USB_D+ 3.3VAUX_4 1
0_0805_5% C458 @ 5 6
<10> USB20_N2 USB_D- LED1#
C459 C460 7 8
4.7U_0402_6.3V6M 0.1U_0201_10V6K 0.1U_0201_10V6K 9 GND_7 PCM_CLK 10
2 2 2 11 SDIO_CLK PCM_SYNC 12
13 SDIO_CMD PCM_OUT 14
15 SDIO_DAT0 PCM_IN 16
17 SDIO_DAT1 LED2# 18
19 SDIO_DAT2 GND_18 20
21 SDIO_DAT3 UART_W AKE 22
23 SDIO_W AKE UART_TX
+3VS_WLAN SDIO_RST
+3VALW @ 24
U2606 25 UART_RX 26
W=60mils GND_33 UART_RTS
1U_0402_6.3V6K
C2664
5 1 27 28
IN OUT <6> PCIE_ATX_C_DRX_P1 PET_RX_P0 UART_CTS E51TXD_P80DATA_R
1 29 30 R873 2 RS@ 1 0_0402_5%
<6> PCIE_ATX_C_DRX_N1 PET_RX_N0 CLink_RST E51RXD_P80CLK_R EC_TX <24>
2 31 32 R3955 2 RS@ 1 0_0402_5%
GND GND_39 CLink_DATA EC_RX <24>
@ 33 34
<6> PCIE_ARX_DTX_P1 PER_TX_P0 CLink_CLK
4 3 35 36 2 1
2 EN OC <6> PCIE_ARX_DTX_N1 PER_TX_N0 COEX3
37 38 R874 100K_0402_5%
SY6288C20AAC_SOT23-5 39 GND_45 COEX2 40
<10> CLK_PCIE_WLAN REFCLK_P0 COEX1
41 42 T4947 TP@
<10> CLK_PCIE_WLAN# REFCLK_N0 SUSCLK(32KHz) WL_RST#_R
43 44 R440 1 RS@ 2 0_0402_5%
GND_51 PERST0# BT_ON APU_PCIE_RST# <9,15,28,30>
45 46
<24> WLAN_ON <9> WLAN_CLKREQ# CLKREQ0# W _DISABLE2# WL_OFF# BT_ON <24>
47 48
<24> WLAN_WAKE# PEW AKE0# W _DISABLE1# WL_OFF# <24>
49 50
51 GND_57 I2C_DAT 52
R3807 53 RSVD/PCIE_RX_P1 I2C_CLK 54
2 1 10K_0402_5% 55 RSVD/PCIE_RX_N1 I2C_IRQ 56
2
NGFF WL+BT (KEY E) +3VS_WLAN
57
59
GND_63
RSVD/PCIE_TX_P1
RSVD_64
RSVD_66
58
60 2
61 RSVD/PCIE_TX_N1 RSVD_68 62
63 GND_69 RSVD_70 64
65 RSVD_71 3.3VAUX_72 66
67 RSVD_73 3.3VAUX_74
GND_75 68
69 GND1
GND2
BELLW_80152-3221
CONN@
SP070013E00
3 3
4 4

M.2 Key E (WLAN)
Custom 1.A
A B C D E
A B C D E F G H
SATA Re-Driver and cable HDD Conn.
G-Sensor (reserved) +3VS

+3VS
1
+3VS RZ1 GS@ +3VS
1
10K_0402_5% DVT_0203: remove JHDD1
1
UZ1 GS@ RZ3 1
RZ4 GS@ 1 CZ1 1 2 10U_0603_6.3V6M @ 10K_0402_5%
Vdd_IO
2
2.2K_0402_5% 8 GS@
1 2 APU_I2C1_SCL_G APU_I2C1_SCL_G 4 CS 14 CZ2 1 2 0.1U_0201_10V6K
SCLSPC Vdd
2
APU_I2C1_SDA_G 6
RZ5 GS@ RZ2 1 @ 2 10K_0402_5% 7 SDA/SDI/SDO G_INT#
+3VS SDO/SA0 G_INT#
2.2K_0402_5% RZ6 1 GS@ 2 10K_0402_5% 11 RZ7 1 GS@ 2 0_0402_5%
1 2 APU_I2C1_SDA_G +1.8VS 16 INT1 9 G_INT2 G_INT#_APU <9>
15 ADC1 INT2
13 ADC2 10 INT1/2 all High Active
ADC3 RES
2
NC
2
3 5
NC GND 12
G
APU_I2C1_SCL 1 6 APU_I2C1_SCL_G GND
<9> APU_I2C1_SCL
D
LIS3DHTR_LGA16_3X3
5
DMN63D8LDW-7_SOT363-6 GS@
QZ1B GS@
G
APU_I2C1_SDA 4 3 APU_I2C1_SDA_G LIS3DH

<9> APU_I2C1_SDA
S
DMN63D8LDW-7_SOT363-6 SA0 ->0, Address is 0011 000 (0x30h) JHDD2

QZ1A GS@ SA0 ->1, Address is 0011 001 (0x32h) 1
2 1
Vgs = 0.8~1.5 V 3 2
4 3
+3VS 4
5
5
B_EQ1
A_EQ2
A_EQ1
6
6
DEW
7
8 7
+3VS +5VS_HDD RO3 1 RS@ 2 0_0805_5% +5VS_HDD 9 8
CO14 +5VS 9
10
2 1 11 10
100mils G_INT2 JHDD_P9 11
UO2 Check INT pin RO4 1 @ 2 0_0402_5% 12
12
0.01U_0402_16V7K 13
20
19
18
17
16
PS8527CTQFN20GTR2A_TQFN20_4X4 13
10U_0603_6.3V6M
CO12
1 14
14
1
SA00007JU10 RDSATA_CRX_DTX_P0 CO4 2 1 0.01U_0402_16V7K RDSATA_CRX_C_DTX_P0 15
DEW
VDD2
B_EQ1
A_EQ2
A_EQ1
PAR@ CO13 RDSATA_CRX_DTX_N0 CO3 2 1 0.01U_0402_16V7K RDSATA_CRX_C_DTX_N0 16 15
2
0.1U_0201_10V6K 17 16 2
17
2
CO16 2 1 SATA_ATX_C_DRX_P0 0.01U_0402_16V7K 1 15 RDSATA_CTX_DRX_P0 2 @ RDSATA_CTX_DRX_N0 CO2 2 1 0.01U_0402_16V7K RDSATA_CTX_C_DRX_N0 18
<10> SATA_ATX_DRX_P0 SATA_ATX_C_DRX_N0 A_INP A_OUTP RDSATA_CTX_DRX_N0 RDSATA_CTX_DRX_P0 RDSATA_CTX_C_DRX_P0 18
<10> SATA_ATX_DRX_N0 CO17 2 1 0.01U_0402_16V7K 2 14 CO1 2 1 0.01U_0402_16V7K 19
3 A_INN A_OUTN 13 B_EQ2 20 19
CO18 2 1 SATA_ARX_C_DTX_N0 0.01U_0402_16V7K 4 GND1 B_EQ2 12 RDSATA_CRX_DTX_N0 close to CONN. 21 20
<10> SATA_ARX_DTX_N0 CO19 2 1 SATA_ARX_C_DTX_P0 0.01U_0402_16V7K 5 B_OUTN B_INN 11 RDSATA_CRX_DTX_P0 22 G1
<10> SATA_ARX_DTX_P0 21 B_OUTP B_INP 23 G2
GND2 G3
VDD1
REXT
24
B_DE
A_DE
+3VS G4
EN
ACES_50406-02071-001
RO10 1 @ 2 4.7K_0402_5% A_DE CONN@
6
7
8
9
10
RO15 1 @ 2 4.7K_0402_5% SP010016L00
A_EQ1 +3VS
RO13 1 @ 2 4.7K_0402_5% RO6 2 1 1
RO18 1 @ 2 4.7K_0402_5% +3VS 4.99K_0402_1% B_DE
A_DE CO15
RO14 1 @ 2 4.7K_0402_5% A_EQ2 RO5 1 @ 2 0.1U_0201_10V6K
RO19 1 PAR@ 2 4.7K_0402_5% 4.7K_0402_5% 2
RO11 1 @ 2 4.7K_0402_5% B_DE

RO16 1 @ 2 4.7K_0402_5% USE 8527 re-driver
UO2
RO12 1 @ 2 4.7K_0402_5% B_EQ1 SA00007JU10
RO17 1 PAR@ 2 4.7K_0402_5%
RO20 1 @ 2 4.7K_0402_5% B_EQ2

RO21 1 PAR@ 2 4.7K_0402_5%
SN75LVCP601RTJR_A.4_TQFN20_4X4
RO22 1 TI@ 2 4.7K_0402_5% DEW TI@
SA00003ZX00
3
SATA NGFF SSD Conn. 1
3
5
JSSD1
GND
GND
3P3VAUX
3P3VAUX
2
4
6
+3VS_SSD_NGFF
3
7 PERn3 DTx3 NC 8 LON/SAM:Pin10=Device_Active_Signal +3VS +3VS_SSD_NGFF

LON/SAM:Pin9=NC 9 PERp3 NC 10 SSD_LED# RM9
GND DAS/DSS# @ T245
11 12 0_0805_5%
13 PETn3 DRx3 3P3VAUX 14 1 RS@ 2
LON:Pin15=notch 15 PETp3 3P3VAUX 16
SAM:Pin12-19 notch 17 GND 3P3VAUX 18 CM141 1 1
10U_0603_6.3V6M
0.1U_0201_10V6K
19 PERn2 DTx2 3P3VAUX 20 CM13
21 PERp2 NC 22 + CS29
23 GND NC 24 150U_B2_6.3VM_R35M
25 PETn2 DRx2 NC 26 2 2 SGA00009M00
27 PETp2 NC 28 2
PCIE_ARX_DTX_N3 29 GND NC 30
<6> PCIE_ARX_DTX_N3 PCIE_ARX_DTX_P3 31 PERn1 DTx1 NC 32
<6> PCIE_ARX_DTX_P3 PERp1 NC
33 34 LON:If system didn't support DEVSLP, set Device Sleep Signal high and
PCIE_ATX_C_DRX_N3 35 GND NC 36 keep (from power on), device will ignore.
<6> PCIE_ATX_C_DRX_N3 PCIE_ATX_C_DRX_P3 PETn1 DRx1 NC DEVSLP1_R
37 38 RM21 1 @ 2 0_0402_5%
<6> PCIE_ATX_C_DRX_P3 PETp1 DEVSLP DEVSLP1 <10>
PCIE SSD 39 40
PCIE_ARX_DTX_N2 RM11 1 PCIE@ 2 0_0402_5% PCIE_ARX_R_DTX_N2 41 GND NC 42 RM20 1 2 0_0402_5%
<6> PCIE_ARX_DTX_N2 PCIE_ARX_DTX_P2 PCIE_ARX_R_DTX_P2 PERn0/SATA-B+ NC
RM12 1 PCIE@ 2 0_0402_5% 43 DTx0 44
<6> PCIE_ARX_DTX_P2 PERp0/SATA-B- NC
45 46 EMC@ CM15 1 2 100P_0402_50V8J
PCIE_ATX_C_DRX_N2 RM13 1 PCIE@ 2 0_0402_5% PCIE_ATX_R_DRX_N2 47 GND NC 48
<6> PCIE_ATX_C_DRX_N2 PCIE_ATX_C_DRX_P2 RM14 1 PCIE@ 2 0_0402_5% PCIE_ATX_R_DRX_P2 PETn0/SATA-A-DRx0 NC SSD_PCIE_RST#
49 50 RM18 1 @ 2 0_0402_5% APU_PCIE_RST# <9,15,28,29>
<6> PCIE_ATX_C_DRX_P2 PETp0/SATA-A+ PERST# SSD_CLKREQ#_R
51 52 RM5 1 @ 2 0_0402_5% SSD_CLKREQ# <9>
SATA@ 53 GND CLKREQ# 54
SATA_ARX_DTX_P1 CM7 1 2 0.01U_0402_16V7K 55 REFCLKN PEWake# 56
<10> SATA_ARX_DTX_P1 SATA_ARX_DTX_N1 REFCLKP NC
CM8 1 2 0.01U_0402_16V7K 57 58
<10> SATA_ARX_DTX_N1 GND NC
SATA SSD SATA@ SATA@
SATA_ATX_DRX_N1 CM9 1 2 0.01U_0402_16V7K
<10> SATA_ATX_DRX_N1 SATA_ATX_DRX_P1 CM10 1 2 0.01U_0402_16V7K
<10> SATA_ATX_DRX_P1
SATA@
LON/SAM:Pin61=GND 59 Pin67 Pin68 60 SUSCLK_SSD
NC @ T246
CLK_PCIE_SSD# 61 Pin69 Pin70 SUSCLK(32kHz) 62
<10> CLK_PCIE_SSD# CLK_PCIE_SSD PEDET(NC-PCIE/GND-SATA) 3P3VAUX +3VS_SSD_NGFF
4 63 Pin71 Pin72 64 4
<10> CLK_PCIE_SSD GND 3P3VAUX
65 Pin73 Pin74 66
RM22 1 2 0_0402_5% SSD_DET# 67 GND Pin75 3P3VAUX
<9> AGPIO8 GND 68
GND1 69
GND2
BELLW_80159-3221
CONN@
SSD_DET# Function
SP070018L00 Security Classification Compal Secret Data Compal Electronics, Inc.
1 PCIE SSD Device 2017/04/18 2019/04/18 Title
Issued Date Deciphered Date
HDD/SSD
0 SATA SSD Device Size Document Number R ev
Custom 1.A
A B C D E F G H
5 4 3 2 1
USB3.0 (Port 3) For ESD request C483

+5VALW
1U_0402_6.3V6K U25
+USB3_VCCA
80mils 2A
D15 EMC@ 1 2 5 1
USB3_ATX_L_DRX_P3 1 1 USB3_ATX_L_DRX_P3 IN OUT
10 9
2
USB3_ATX_C_DRX_N3 USB3_ATX_L_DRX_N3 USB3_ATX_L_DRX_N3 2 2 USB3_ATX_L_DRX_N3 GND
<10> USB3_ATX_DRX_N3
C482 1 2 R3968 1 RS@ 2 0_0402_5% 9 8
.1U_0402_16V7K USB_CHARGE_2A 4 3 R454 1 @ 2 0_0402_5%
USB3_ARX_L_DTX_P3 USB3_ARX_L_DTX_P3 <24> USB_CHARGE_2A EN OC USB_OC0# <9>
4 4 7 7
C484 1 2 USB3_ATX_C_DRX_P3 R3967 1 RS@ 2 0_0402_5% USB3_ATX_L_DRX_P3 SY6288C20AAC_SOT23-5
<10> USB3_ATX_DRX_P3 USB3_ARX_L_DTX_N3 USB3_ARX_L_DTX_N3 1
.1U_0402_16V7K 5 5 6 6
C612
D 3 3 0.1U_0201_10V6K D
USB3_ARX_DTX_N3 R3966 1 RS@ 2 0_0402_5% USB3_ARX_L_DTX_N3 2@
<10> USB3_ARX_DTX_N3 8
USB3_ARX_DTX_P3 R3965 1 RS@ 2 0_0402_5% USB3_ARX_L_DTX_P3
<10> USB3_ARX_DTX_P3
L05ESDL5V0NA-4 SLP2510P8
+USB3_VCCA
1 1
D2010 EMC@ CS25 + C487
6 3 USB20_P7_L 150U_B2_6.3VM_R35M
I/O4 I/O2 .1U_0402_16V7K
SGA00009M00 2
2 EMC@
+USB3_VCCA
USB20_P7_G 2 1 USB20_P7_L 5 2
USB3.0 Conn.
VDD GND JUSB1
1
USB20_N7_G 3 4 USB20_N7_L USB20_N7_L 2 VBUS
4 1 USB20_N7_L USB20_P7_L 3 D-
MCM1012B900F06BP_4P I/O3 I/O1 4 D+
L2508 AZC099-04S.R7G_SOT23-6 USB3_ARX_L_DTX_N3 5 GND
EMC@ SSRX-
USB3_ARX_L_DTX_P3 6 10
7 SSRX+ GND 11
USB3_ATX_L_DRX_N3 8 GND GND 12
USB3_ATX_L_DRX_P3 9 SSTX- GND 13
+3VLP SSTX+ GND
ACON_TARB5-9V1391
USB20_N7 RS96 1 NCHG@ 2 0_0402_5% USB20_N7_G
CONN@
1
USB20_P7 RS97 1 NCHG@ 2 0_0402_5% USB20_P7_G CHG@
C C
RS94 DC23300NH00
10K_0402_5%
USB Host Charger US10
2
USB_CB 8 1 USB_CEN
<24> USB_CB USB20_N7 CB CEN USB20_N7_G USB_CEN <24>
CB SELCDP 7 2
<10> USB20_N7 USB20_P7 TDM DM USB20_P7_G
6 3
<10> USB20_P7 TDP DP USB_SELCDP
0 X DCP(Dedicated Charging Port) +5VALW 5 4 USB_SELCDP <24>
VDD SELCDP 9
autodetect with mouse/keyboard wakeup 1 Thermal Pad
CS89
1 0 S0 charging with SDP(Standard Downstream Port) only 0.1U_0201_10V6K SLG55594AVTR_TDFN8_2X2
CHG@ SA00006L600
2 CHG@
1 1 S0 charging with CDP(Charging Downstream Port) or
SDP only
JUSB3
HPOUT_L_1 1
<34> HPOUT_L_1 HPOUT_R_1 1
2
<34> HPOUT_R_1 2
<34> SLEEVE SLEEVE 3
RING2 4 3
USB20_P0 USB20_P0_L <34> RING2 HP_PLUG# 4
2 1 5
<10> USB20_P0 <34> HP_PLUG# 5
6
GNDA 6
7
USB20_N0 3 4 USB20_N0_L 8 7
<10> USB20_N0 USB20_P0_L 9 8
MCM1012B900F06BP_4P USB20_N0_L 10 9
B 10 B
L2509 EMC@ 11
USB20_P1_L 12 11
USB20_P1 2 1 USB20_P1_L USB20_N1_L 13 12
<10> USB20_P1 13
14
BATT_AMB_LED# 15 14
USB20_N1 USB20_N1_L <24> BATT_AMB_LED# BATT_BLUE_LED# 15
3 4 <24> BATT_BLUE_LED# 16
<10> USB20_N1 PWR_SUSP_LED# 16
<24> PWR_SUSP_LED# 17
MCM1012B900F06BP_4P PWR_LED# 18 17
<24> PWR_LED# 18
L2510 EMC@ 19
USB_EN 20 19
<24> USB_EN 20
21
22 21
23 22
24 23
25 24
100mils 2.5A 26 25
+5VALW 26
GNDA 27
28 GND
GND
ACES_51522-02601-001
CONN@
SP01001AO00
A A

USB2.0/USB3.0
Custom 1.A
5 4 3 2 1
5 4 3 2 1
USB3.0 (Port 1) For ESD request
DS1 EMC@
USB3_ATX_C_DRX_N1 USB3_ATX_L_DRX_N1 CC2_VCONN 1 1 CC2_VCONN
<10> USB3_ATX_DRX_N1 CS1 1 2 RS1 1 RS@ 2 0_0402_5% 10 9
.1U_0402_16V7K
TBTA_SBU2 2 2 9 8 TBTA_SBU2
CS2 1 2 USB3_ATX_C_DRX_P1 RS2 1 RS@ 2 0_0402_5% USB3_ATX_L_DRX_P1
<10> USB3_ATX_DRX_P1 CC1_VCONN CC1_VCONN
.1U_0402_16V7K 4 4 7 7
TBTA_SBU1 5 5 6 6 TBTA_SBU1
3 3
D <10> USB3_ARX_DTX_N1
USB3_ARX_DTX_N1 RS3 1 RS@ 2 0_0402_5% USB3_ARX_L_DTX_N1
DS2
D
EMC@
USB20_P5 USB20_P5_L USB3_ATX_L_DRX_P1 1 USB3_ATX_L_DRX_P1
<10> USB20_P5
2 1 1 10 9
USB3_ARX_DTX_P1 RS4 1 RS@ 2 0_0402_5% USB3_ARX_L_DTX_P1
<10> USB3_ARX_DTX_P1 USB3_ATX_L_DRX_N1 2 USB3_ATX_L_DRX_N1
2 9 8
USB20_N5 3 4 USB20_N5_L
<10> USB20_N5 USB20_P5_L USB20_P5_L
4 4 7 7
MCM1012B900F06BP_4P
LS7 EMC@ USB20_N5_L 5 5 6 6 USB20_N5_L
SM070003Z00
3 3
USB3.0 (Port 2) 8
CS3 1 2 USB3_ATX_C_DRX_N2 RS5 1 RS@ 2 0_0402_5% USB3_ATX_L_DRX_N2

<10> USB3_ATX_DRX_N2
.1U_0402_16V7K
DS3 EMC@
1 2 USB3_ATX_C_DRX_P2 1 RS@ 2 0_0402_5% USB3_ATX_L_DRX_P2 USB3_ATX_L_DRX_N2 1 USB3_ATX_L_DRX_N2
<10> USB3_ATX_DRX_P2 CS4 RS6 1 10 9
.1U_0402_16V7K
USB3_ATX_L_DRX_P2 2 9
USB3_ATX_L_DRX_P2
2 8
USB3_ARX_L_DTX_N2 4 7
USB3_ARX_L_DTX_N2
4 7
USB3_ARX_L_DTX_P2 5 6
USB3_ARX_L_DTX_P2
5 6
3 3
8
USB3_ARX_DTX_N2 RS7 1 RS@ 2 0_0402_5% USB3_ARX_L_DTX_N2
<10> USB3_ARX_DTX_N2
USB3_ARX_DTX_P2 RS8 1 RS@ 2 0_0402_5% USB3_ARX_L_DTX_P2
<10> USB3_ARX_DTX_P2 DS4 EMC@
USB3_ARX_L_DTX_P1 1 USB3_ARX_L_DTX_P1
1 10 9
USB3_ARX_L_DTX_N1 2 9
USB3_ARX_L_DTX_N1
2 8
4 4 7 7
C 5 5
3 3
6 6
C
+5VALW +5VALW_CC +3VALW +3VALW_CC +5VALW_CC_VOUT 8
120mils 3A
JPS2 L05ESDL5V0NA-4 SLP2510P8
1 2 RS10 1 2 0_0402_5% 1
1 2 CS8
10U_0603_6.3V6M
0.1U_0201_10V6K
0.01U_0402_16V7K
JUMP_43X79 10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
1 1 1 1 1 1 1
@
+ CS90 + CS6 2
CS7
CS9
CS10
CS91
CS5
150U_B2_6.3VM_R35M 150U_B2_6.3VM_R35M
SGA00009M00 @ 2 2 @ SGA00009M00 2 2 2
2 2 +USB3_VCCC +USB3_VCCC
@ JPS1
1 2
1 2
JUMP_43X118 CC1_VCONN/CC2_VCONN 20mils JUSB4
+USB3_VCCC A1 B12
+5VALW_CC +5VALW_CC_VOUT GND GND
+3VALW_CC US1
30V 10mOhm
@ QS1 AON6405L 1P DFN USB3_ATX_L_DRX_P1 A2 B11 USB3_ARX_L_DTX_P1
RPS1 +3VALW_CC 120mils 3A 120mils 3A 1
120mils 3A USB3_ATX_L_DRX_N1 A3 SSTXP1 SSRXP1 B10 USB3_ARX_L_DTX_N1
100K_0804_8P4R_5% 2 14 2 CS11 2 1 0.47U_0402_25V6K SSTXN1 SSRXN1
1 8 CC_AUDIO# 3 IN1 OUT 15 5 3 A4 B9 CS12 1 2 0.47U_0402_25V6K
2 7 CC_POL# 4 IN1 OUT VBUS VBUS
6 CC_UFP# IN2 CC1_VCONN TBTA_SBU2
3
3 A5 B8
5 CC_LD_DET#
1
4 5 RS15 RS12 CS13 CC1 SBU2
4
AUX 1 CC_FAULT# +3VALW_CC 100K_0402_5% @ 1M_0402_5% 10U_0805_25V6K USB20_P5_L A6 B7 USB20_N5_L
RS37 0_0402_5% FAULTb 20 CC_LD_DET# @ DS5 USB20_N5_L A7 DP1 DN2 B6 USB20_P5_L
2
1 RS@ 2 CC_EN 6 LD_DETb MESC5V02BD03_SOT23-3 DN1 DP2
<24> EC_TYPEC_EN
2
EN TBTA_SBU1 CC2_VCONN
1
+3VALW_CC EMC@ A8 B5
RS42 SBU1 CC2
CC_CHG 7 11 CC1_VCONN @ 10K_0402_5% CS14 2 1 0.47U_0402_25V6K A9 B4 CS15 1 2 0.47U_0402_25V6K
RS13 1 2 100K_0402_5% CC_FAULT# TYPEC_3A_1P5A 8 CHG CC1 13 CC2_VCONN VBUS VBUS
1
CC_DEBUG# CHG_HI CC2 USB3_ARX_L_DTX_N2 USB3_ATX_L_DRX_N2
3
RS18 1 2 100K_0402_5% D A10 B3
2
RS20 1 2 100K_0402_5% CC_CHG 5 QS2B USB3_ARX_L_DTX_P2 A11 SSRXN2 SSTXN2 B2 USB3_ATX_L_DRX_P2

RS40 1 @ 2 0_0402_5% TYPEC_3A_1P5A 16 CC_DEBUG# G 2N7002KDW_SOT363-6 SSRXP2 SSTXP2
RS41 1 @ 2 0_0402_5% CC_EN CC_REF 10 DEBUGb 17 CC_AUDIO# @ A12 B1
REF AUDIOb CC_POL# GND GND
6
18 D S
4
POLb 19 CC_UFP# 2 QS2A

UFPb
B <24> TYPEC_3A_1P5A# RS38 1 RS@ 2 0_0402_5% TYPEC_3A_1P5A
RS39 1 2 100K_0402_1% 9
12 GND1
GND2 powerpad
21
G
S
2N7002KDW_SOT363-6
@
1
2
3
GND
GND
GND
GND
5
6
7
B
1
4 GND GND 8
GND GND
LOTES_AUSB0181-P001A
TPS25810RVCR_QFN20_4X3
DC021702230
CONN@
Note : 2017 BIOS SPEC define DC mode 30% stop charge
A A

Type-C (TPS25810)
Custom
5 4 3 2 1
ON/OFF BTN TP/B Conn.
+TP_VCC +TP_VCC +3VALW +TP_VCC +3VS
20mil 0.1A RP20
U13 I2C_DAT 1 8
I2C_CLK
4.7U_0402_6.3V6M
R534 1 5 2 7
100K_0402_5% 1 @ 2 OUT IN TP_I2C_INT#_APU 3 6
+3VS 1
C2563
1U_0402_6.3V6K
2 1 R463 0_0402_5% 2 4 5
+3VLP GND
C2562
2
C663 3 4 2.2K_0804_8P4R_5%
ON/OFFBTN# JTP1 0.1U_0201_10V6K 2 OC EN
<24> ON/OFFBTN# +TP_VCC
1 1 2 SY6288C20AAC_SOT23-5
1 2 TP_CLK @ 1
2 3 TP_DATA TP_I2C_INT# 2 1
3 4 R633
4 5 I2C_DAT <24> TP_3V_EN
10K_0402_5%
4 3 5 6 I2C_CLK
6 7 TP_I2C_INT#
Test Only 7 8 TP_SENOFF#
SWK1 EVT@ TP_SENOFF# <24>
SKRPABE010_4P 8 9
BOT 2 1 GND 10
GND TP_I2C_INT# <24> To EC
ACES_51524-00801-001
CONN@
TP_I2C_INT# 1 2
SP01001A910 +TP_VCC TP_I2C_INT#_APU <9> To APU
D22
RB751V-40_SOD323-2
1
R2507 R2509 +TP_VCC
4.7K_0402_5% 4.7K_0402_5%
5
2
2
VGS,on = 1.2~2.0V
G
I2C_CLK 4 3
TP_CLK APU_I2C3_SCL <9>
D
Q2509A @
TP_CLK <24>
2
TP_DATA DMN66D0LDW-7_SOT363-6
TP_DATA <24> To APU
G
I2C_DAT 1 6
APU_I2C3_SDA <9>
D
Q2509B @
Lid Switch (Hall Effect Switch) DMN66D0LDW-7_SOT363-6

R2622 1
R2623 1
2 0_0402_5%
2 0_0402_5%
PU at APU side.
Use 0ohm for BR/SR.
+3VLP
JLID1
1 KSI[0..7]
KSI[0..7] <24>
KB BackLight KB Conn.
LID_SW# 2 1
<24> LID_SW# 2
3 KSO[0..17]
3 KSO[0..17] <24>
4
4
5
6 GND
GND JKB2
ACES_51524-0040N-001 <24> CAPS_LED# R3982 1 2 1K_0402_5% 1
+5VS JKB1 1
CONN@ JBL1 R3983 1 @ 2 0_0402_5% 2
U1 1 30 R3984 1 @ 2 0_0402_5% 3 2
SP010022M00 5 1 +5VS_BL 2 1 29 GND2 +5VS
<24> NUM_LED# R3985 1 2 1K_0402_5% 4 3
IN OUT 3 2 28 GND1 5 4
2 4 3 ON/OFFBTN# 27 28 ON/OFFBTN# 6 5
GND 4 KSO0 26 27 KSO0 7 6
4 3 5 KSO1 25 26 KSO1 8 7
<24> KBL_EN EN OC GND 25 8
6 KSO2 24 KSO2 9
SY6288C20AAC_SOT23-5 GND KSO3 23 24 KSO3 10 9
ACES_51524-0040N-001 KSO4 22 23 KSO4 11 10
CONN@ KSO5 21 22 KSO5 12 11
1 21 12
KSO6 20 KSO6 13
SP010022M00
TPM C3 KSO7 19 20 KSO7 14 13
KSO8 18 19 KSO8 15 14
0.1U_0201_10V6K 18 15
2 KSO9 17 KSO9 16
KSO10 16 17 KSO10 17 16
KSO11 15 16 KSO11 18 17
+3VALW RW1 +3VALW_TPM +3VS RW2 +3VS_TPM KSO12 14 15 KSO12 19 18
0_0603_5% 0_0603_5% JBL2 KSO13 13 14 KSO13 20 19
1 RS@ 2 1 RS@ 2 1 KSO14 12 13 KSO14 21 20
+5VS_BL 2 1 KSO15 11 12 KSO15 22 21
2 11 22
10U_0603_6.3V6M
0.1U_0201_10V6K
CW2
10U_0603_6.3V6M
0.1U_0201_10V6K
CW4
0.1U_0201_10V6K
CW5
0.1U_0201_10V6K
CW6
1 1 1 1 1 1 3 KSO16 10 KSO16 23
3 10 23
CW1
CW3
4 KSO17 9 KSO17 24
4 KSI0 8 9 KSI0 25 24
5 KSI1 7 8 KSI1 26 25
2 TPM@ 2 TPM@
near pin5 2 TPM@ 2 2
TPM@ 2
TPM@ TPM@ 6 GND KSI2 6 7 KSI2 27 26 33
GND KSI3 5 6 KSI3 28 27 GND 34
ACES_51524-0040N-001 KSI4 4 5 KSI4 29 28 GND
CONN@ KSI5 3 4 KSI5 30 29
KSI6 2 3 KSI6 31 30
near pin10, 19, 24
SP010022M00 KSI7 1 2 KSI7 32 31
1 32
ACES_85201-2805
CONN@ ACES_50596-03201-P01
CONN@
SP01000GO00
BADD
SP010017J00
SELECTION
* 1 AEh(write), AFh(read)
UW1 TPM@
1 +3VALW_TPM
29 VSB
30 XOR_OUT/SDA/GPIO0 8
SCL/GPIO1 VDD1 +3VS_TPM
3 14
10K_0402_5%1 @ 2 RW3 TPM_BADD 6 GPX/GPIO2 VDD2 22
GPIO3/BADD VDD3
24 2
<10,24> LPC_AD0 LAD0/MISO NC1
21 7
<10,24> LPC_AD1 LAD1/MOSI NC2
18 10
<10,24> LPC_AD2 LAD2/SPI_IRQ# NC3
15 11
<10,24> LPC_AD3 LAD3 NC4 25
19 NC5 26
<9,10> LPC_CLK1 LCLK/SCLK NC6
20 31
<9,10,24> LPC_FRAME# LFRAME#/SCS# NC7
17
<9,24> LPC_RST# LRESET#/SPI_RST#/SRESET#
27 9
<10,24> SERIRQ 13 SERIRQ GND1 16
<10> CLKRUN# CLKRUN#/GPIO4/SINT# GND2
28 23
LPCPD# GND3 32
4 GND4 33
5 PP PGND 12
TEST Reserved
CLKRUN PH 10K to +3VS at APU side NPCT650ABBYX_QFN32_5X5
LPCPD# had internal PH SA00008EL40, S IC NPCT650AB1YX QFN 32P TPM1.2

SA00008ELB0, S IC NPCT650AB2YX QFN 32P TPM1.2 FW 5.81.2.1 Security Classification Compal Secret Data Compal Electronics, Inc.
SA00008ELC0, S IC NPCT650ABBYX QFN 32P TPM2.0 FW 1.3.1.0 Issued Date 2017/04/18 Deciphered Date 2019/04/18 Title
LPC_CLK1 RW4 1 2 33_0402_5% CW7 1 2 22P_0402_50V8J
KB/TP/TPM/LID
Custom 1.A
@EMC@ @EMC@ DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
A B C D E
HD Audio Codec +PVDD_HDA
SM01000EJ00 3000mA 220ohm@100mhz DCR 0.04 +5VS (output = 300 mA) +VDDA
40mil 40mil JPA1 40mil Int. Speaker Conn.
+VDDA
LA1 2 1 1
1 2
2 40mil SPK_R+
JSPK1
HCB2012KF-221T30_0805 2 1 SPKR+ EMC@1 LA2 2 PBY160808T-121Y-N_2P 1
1
1
SPK_R-
10U_0603_6.3V6M
CA1
0.1U_0201_10V6K
CA2
0.1U_0201_10V6K
CA3
.1U_0402_16V7K
CA4
2 JUMP_43X79 4.75V SPKR- EMC@1 LA3 2 PBY160808T-121Y-N_2P
SPK_L+
2
2
@ SPKL+ EMC@1 LA4 2 PBY160808T-121Y-N_2P 3
SPKL- EMC@1 LA5 2 PBY160808T-121Y-N_2P SPK_L- 4 3
2
1 @ +AVDD1_HDA 2 5 4
1 @EMC@ 6 G1
GND & GNDA moat EMI request for solve EMI noise, SM01000OW00. G2
GND GND
3
GND ACES_50278-00401-001
1 GND CONN@ 1
Place near Pin41 Place near Pin46
@EMC@ @EMC@
DA1 DA2 SP02000RR00
TVNST52302AB0_SOT523-3 TVNST52302AB0_SOT523-3
20mil
1
CA5 1 2 10U_0603_6.3V6M RA1 1 @ 2
GND +VDDA
10U_0603_6.3V6M
CA9
1
1
0.1U_0201_10V6K
CA8
Pin9 need to matching with SOC HDA CA6 2 1 0.1U_0201_10V6K 0_0603_5% GND GND
interface. +1.8VS_DVDDIO
RA2 2 @ 1 0_0402_5% Place near Pin9 @
+1.8VS
2
2
+3VS_DVDD GND & GNDA moat
20mil GNDA
RA5 2 @ 1 0_0402_5% Place near Pin26
+3VS
0.1U_0201_10V6K
1 1 +1.8VS_VDDA
CA11
CA10 RA6 2 @ 1 +1.8VS
1
1
0.1U_0201_10V6K
CA12
CA13
10U_0603_6.3V6M
10U_0603_6.3V6M 0_0402_5%
2 2
2
2 @
Place near Pin1 GND GNDA
41
46
26
40
1
9
UA1 Place near Pin40
PVDD1
PVDD2
AVDD1
AVDD2
DVDD
DVDD-IO
CA32 @EMC@
10P_0402_50V8J LINE1-L 22
1 2 DMIC_CLK LINE1-R 21 LINE1-L(PORT-C-L) 43 SPKL-
LINE1-R(PORT-C-R) SPK-OUT-L- 42 SPKL+
24 SPK-OUT-L+
23 LINE2-L(PORT-E-L) 45 SPKR+
2 LINE2-R(PORT-E-R) SPK-OUT-R+ 2
GND 44 SPKR-
RING2 17 SPK-OUT-R-
40mil SLEEVE 18 MIC2-L(PORT-F-L) /RING2
MIC2-R(PORT-F-R) /SLEEVE 32 HP_LEFT
Combo MIC HPOUT-L(PORT-I-L) HP_RIGHT
+MICBIAS 31 33
+MICBIAS LINE1-VREFO-L HPOUT-R(PORT-I-R)
30
LINE1-VREFO-R 10 HDA_SYNC_AUDIO
DMIC_DATA SYNC HDA_BITCLK_AUDIO HDA_SYNC_AUDIO <9>
2 6
<27> DMIC_DATA GPIO0/DMIC-DATA BCLK HDA_BITCLK_AUDIO <9>
1 2 DMIC_CLK 3
<27> DMIC_CLK_R GPIO1/DMIC-CLK 1 @EMC@2 1 2 CA15 @EMC@
RA34 EMC@ BLM15PX221SN1D GND
RA10 0_0402_5% 22P_0402_50V8J
EC_MUTE# 47 5 HDA_SDOUT_AUDIO
<24> EC_MUTE# HDA_RST#_AUDIO PDB SDATA-OUT HDA_SDIN0_AUDIO HDA_SDOUT_AUDIO <9>
11 8 1 RA33 2
<9> HDA_RST#_AUDIO RESETB SDATA-IN HDA_SDIN0 <9>
33_0402_5%
48
MONO_IN 12 SPDIF-OUT/GPIO2
10mil Close codec1
PCBEEP 16
HP_PLUG# RA13 2 200K_0402_1% SENSE_A 13 MONO-OUT
<31> HP_PLUG# SENSE A +MIC2_VREFO
RA14 2 1 100K_0402_1% 14
+3VS SENSE B
1 29 10U_0603_6.3V6M2 1 CA18 GND
37 MIC2-VREFO
CA19 35 CBP 7 10U_0603_6.3V6M2 1 CA20
CBN LDO3-CAP GNDA
2.2U_0402_6.3V6M 39
2 LDO2-CAP 27 10U_0603_6.3V6M2 1 CA21
LDO1-CAP GNDA
36
GND & GNDA moat +3VS_DVDD CPVDD 1 RA15 2
28 CODEC_VREF 100K_0402_5% 10mil
RA16 1 @ 2 0_0402_5% 20 VREF
+3VALW CPVREF 1 1
Headphone Out
0.1U_0201_10V6K
CA23
2.2U_0402_6.3V6M
CA24
15
10U_0603_6.3V6M2 1 CA22 19 JDREF 34 CPVEE
Pin20 GNDA MIC-CAP CPVEE
ALC283 : NC 1 @ 2 2
ALC255/256/233 : Power for combo jack depop 4
DVSS
+MIC2_VREFO
circuit at system shutdown mode 49 25 CA26
Thermal PAD AVSS1 38 2.2U_0402_6.3V6M
AVSS2 2
3 Pin4 3
ALC283 : DVSS ALC255-CG_MQFN48_6X6

Place near pin28
1
ALC255/256/233 : DC DET (For Japen customer only) SA000082700 GND
GND RA19 RA20
GNDA 2.2K_0402_5% 2.2K_0402_5%
GNDA
2
RA21 CA27 SLEEVE
SLEEVE <31>
DOS mode 22K_0402_5% .1U_0402_16V7K Pin15 RING2
BEEP#_R MONO_IN RING2 <31>
2 1 1 2
<24> EC_BEEP# ALC283 : Ref. Resistor for Jack Detect
ALC255/256/233 : Jack Detect for SPDIF-OUT and SPK-OUT port
2
RA22 1 10/20 vendor review change to 0.1uF.

100P_0402_50V8J
CA28 @EMC@
OS mode 22K_0402_5%
4.7K_0402_5%
RA23
2 1
<9> APU_SPKR
2
1
HP_LEFT RA24 1 @ 2 0_0603_5% HPOUT_L_1

HPOUT_L_1 <31>
HP_RIGHT RA27 1 @ 2 0_0603_5% HPOUT_R_1
HPOUT_R_1 <31>
GND
LINE1-L CA29 1 2 4.7U_0402_6.3V6M
LINE1-R CA30 1 2 4.7U_0402_6.3V6M
+MICBIAS DA5
2 2 RA29 1
GND & GNDA moat 4.7K_0402_5%
JPA2 JPA3 1
JUMP_43X39 JUMP_43X39
1 2 1 2 3 2 RA32 1
@ 1 2 @ 1 2 4.7K_0402_5%
BAT54A-7-F_SOT23-3
4 JPA4 JPA5 4
1 2 1 2
@ 1 2 @ 1 2
CA31 @EMC@ JPA6 JUMP_43X39

.1U_0402_16V7K 1 2
1 2 @ 1 2
JPA7 JUMP_43X39
RA25 1 @EMC@2 0_0402_5% 1 2 Security Classification Compal Secret Data Compal Electronics, Inc.
@ 1 2
2017/04/18 2019/04/18 Title
HD Audio Codec ALC255
GND GNDA GND GNDA AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.A
A B C D E
5 4 3 2 1
FAN Conn
80mil +5VS Screw Hole
RF1 1 RS@ 2 0_0603_5% +VCC_FAN1 PCB Fiducial Mark
+3VS
D +VCC_FAN2 D
RF7 1 RS@ 2 0_0603_5% H3 H4 H34 H10 H39 H33 H36 H37
1 2 H_3P0 H_3P0 H_3P0 H_6P0 H_6P4 H_2P5 H_7P3 H_7P3 FD1 FD2
1
@EMC@ CF2 CF1 RF2
1000P_0402_50V7K 4.7U_0402_6.3V6M 10K_0402_5% @ @
1
2 1
40mil
JFAN1 FIDUCIAL_C40M80 FIDUCIAL_C40M80
2
+VCC_FAN1 1
FAN_SPEED1 2 1 @ @ @ @ @ @ @ @ FD3 FD4
<24> FAN_SPEED1 FAN_PWM1 3 2
<24> FAN_PWM1 3 CPU Hole GPU Hole NGFF Stand-Off
4
5 4 @ @
G1
1
1 6 H13 H14 H15 H26 H27 H38 H29 H30 H5 H6 H31 H32
CF3 G2 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P8 H_3P2 H_3P2 H_4P0 H_4P0 H_4P0 H_4P0 FIDUCIAL_C40M80 FIDUCIAL_C40M80
1000P_0402_50V7K ACES_50278-00401-001
@EMC@ CONN@
2
SP02000RR00
1
@ @ @ @ @ @ @ @ @ @ @ @
+3VS
H23 H35 H25
1
H_2P7X2P0N H_2P7X2P0N H_2P0N
RF5
10K_0402_5%
40mil @ @ @
1
JFAN2
C 2 +VCC_FAN2 1 C
FAN_SPEED2 2 1
<24> FAN_SPEED2 FAN_PWM2 2
3
<24> FAN_PWM2 4 3
5 4
1 G1
CF10 6
1000P_0402_50V7K G2
@EMC@ ACES_50278-00401-001
2 CONN@
SP02000RR00
Reset Circuit +3VLP
R3925 1 @ 2 0_0402_5%
MAINPWON <24,39,41>
2
R349 R3924 1 RS@ 2 0_0402_5%
EC_RST# <24>
100K_0402_5%
6
BI_GATE# 2 G
D
BI_GATE PH to +RTCVCC at PWR side S Q2519B

DMN66D0LDW-7_SOT363-6
1
3
BI_GATE
1
5
D
G
<39> BI_GATE S C347

Q2519A 0.1U_0201_10V6K
4
DMN66D0LDW-7_SOT363-6 2
B B
Reset But t on BI SW
Reset But t on 3 SWG1 1
SWG2
BI_GATE 1 2 BI_GATE BI_S <39>
4 2
ATE-2-V-TR_4P
3 4
H : 3.8mm
SKRPABE010_4P
Release : Bat t er y Off
Push : Bat t er y ON
A A

FAN/BATT RESET_DEGUB SW
Custom 1.A
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 1
Request
Item Page# Date Owner Issue Description Solution Description Rev.
1 02/03 1. update SR PN
2. update VRAM strap (add MICRON)
3. R4000 --> @, R3999 --> RX560@, add R4002 for UMA@
4. QZ1 change to SB000013K00 1.0
D 5. H29,H30 change to H_3P2
D
6. CD11,CD12,CD13,CD14,CD15,CD24,CD27,CD28,R3979 change to VX@
7. change D103 to SC600000B00,add R4003
8. remove JHDD1
9. JPA8 change to JPS2
10.Q84,Q91,Q2511,QL1 change to SB00000PU10
2 02/22
1. Sync QL1 Symbol to Q84,Q91,Q2511
2. change SB00000PU10 to SB00000PU00
3. remove R4002 with UMA@, change R4002 to RX540@
4. add CV2722 and unpop at VGA_ON_B
5. update UV56 PCB Footprint to from SOP8207mil to SOP8-150mil
6. RO19 change to pop
7. CS25 change to B2 footprint (SGA00009M00) 1.0
8. Q91,R1563 change to pop
9. R1562 pop with 100k,R1564 pop with 12k for DVT Board ID
10.RV440,RV422 change to @, RV423,RV439 change to DIS@ (VBIOS in SBIOS)
11.Combine 02/22 Power
12.C794,C795 change to 4.7pF (SE07147AC80)
C 13.CL18,CL19 change to 15pF (SE071150J80),RL14 change to 1k (SD028100180) C
3 02/23 1. Change to 0-ohm Short : RV1632,RO3,RM9,R3924,R683,RD8,RD9,RD10,RD246,RD252,RD225,RD250,RV1640,RS37,RS38
2. RS20 change with 100k 1.0
3. RA34 change with bead (SM01000NY00)
4 02/24 1. CLRP1 change to 0603 footprint
2. UV56 change to @
3. RV1632 change to 0-ohm 1.0
4. Add R106 EMC@
5. Combine Power 02/24
5 03/01 1. 0-ohm short:R106,R107,R108,R3963,R3964,RS1,RS2,RS3,RS4,RS5,RS6,RS7,RS8

2. CV2723 add to @
3. update JUSB4 Symbol (DC021702230) 1.0
4. L2509,L2510 add to EMC@
6 03/03 1. CS90 add to pop, CS91 add to @, CS6 change to @

2. combine power 0303 1.0
B B
7 03/06 1. C2735 add to @ 1.0
1. R4002 add to UMA@

2. RO17,RO21 pop with PAR@
8 03/07 3. R1564 add to VX@ with 27k (SD034270280) 1.0
4. update board ID table for VX
5. update UV1 PN, add DAZ PN
9 03/08 1. CD20,CD84 change to VX@

2. CM15 pop with 100pF (SE071101J80) 1.0
3. RM22 change to VX@
9 03/09 1. RM22 change to pop 1.0
1. Add HDMI Redriver circuits (PS8409)

10 03/11 2. combine power 0310 1.0
3. L11 change to pop (remove NON2S@)
A A
1. add 35W APU PN
11 03/13 2. U2615 change to SA0000AC310 1.0
3. update PCB PN,DAZ PN
4. C2748 add to pop
HW PIR (1/2)
Custom 1.A
5 4 3 2 1
5 4 3 2 1
Version Change List ( P. I. R. List ) Page 2

Request
Item Page# Date Owner Issue Description Solution Description Rev.
12 03/17 1. R3979,CD11,CD12,CD13,CD14,CD15,CD27,CD28,CD24,CD20,CD84 change to pop without VX@.
1.0
D D
1. U4 change main source to S TR AO4354 1N SOIC-8 (SB00000ZN00)

13 04/10 2. Combine power schematic with 0407 1.A
14 04/11 1. L2512,L2513,L2514,L2515 add to pop with 90-ohm choke (SM070003V00) 1.A
1. R1564 change to 15k_0402_1% (SD034150280) for EA, 33K_0402_1% (SD034330280) for Vx

15 04/18 2. PCB change to Rev1A (DAZ21800201) 1.A
3. R4007 change to pop
1.A
C C
1.A
B B
A A

HW PIR (2/2)
Custom 1.A
5 4 3 2 1
A B C D
1 +19V_ADPIN +19V_VIN 1
EMI@ PL101
5A_Z120_25M_0805_2P
@ +19V_ADPIN 1 2
ACES_50299-00601-001
2
1
1 2 PR102 EMI@ PL102 PR103
2 3 5A_Z120_25M_0805_2P
3 4.7_1206_5% 4.7_1206_5%
1
4 1 2
7 4 5 EMI@ PC101 EMI@ PC102
1
1
8 G7 5 6 100P_0603_50V8 1000P_0603_50V7K
2
G8 6
2
2
PJP101 EMI@ EMI@
PC103 PC104
0.1U_0603_25V7K 0.1U_0603_25V7K
1
1
2 2
3 3
@ PR101
0_0603_5%
1 2
+3VLP +CHGRTC
4 4

DCIN
Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. C5V08/D5PR8_LA-E903PR10
A B C D
A B C D
PR201 100_0402_1%
1 2
EC_SMB_DA1 <24,40>
PR202 100_0402_1%
1 2
EC_SMB_CK1 <24,40>
+3VLP
PR203
6.49K_0402_1%
@ 1 2
PJP201 +3VLP
1
1
1
2 1 2
1
2 3 EC_SMB_DA1-1 BATT_TEMP <24> @ PC202
1
1
4 EC_SMB_CK1-1 PR204 1K_0402_1% 0.1U_0603_25V7K
4
2
5 BATT_TS
5
1
6 BATT_B/I @ PR205 @ PR206
6 7 10K_0402_1%
7 8
<45,47> @ PR207
100K_0402_1%
10K_0402_1%
2
8 9 +RTCVCC
GND 10 @ PU201
2
GND 1 8
VCC TMSNS1
1
CVILU_CI9908M2HR0-NH 2 7 2 1
PR208 GND RHYST1
1
100K_0402_5% MAINPWON 3 6 @ PR209
D <24,35,41> MAINPWON OT1 TMSNS2
1
47K_0402_1%
2
2 PQ201 4 5 @ PH201
<35> BI_GATE G LBSS139LT1G 1N SOT-23-3 OT2 RHYST2 100K_0402_1%_NCP15WF104F03RC
S G718TM1U_SOT23-8
2
+17.4V_BATT+ EMI@ PL201
5A_Z120_25M_0805_2P BI_S <35>
1 2
1
1 2
+17.4V_BATT @ PR212
EMI@ PL202 0_0402_5%
5A_Z120_25M_0805_2P
2
1
1
EMI@ PC201 @EMI@ PC203
1000P_0603_50V7K 1000P_0603_50V7K
2
For KB9022 For KB9012

2
OTP Active Recovery sense 20mΩ Active Recovery 2
VCIN0_PH(V) 92C, 1V 56C, 2.V SR 45W 58.5W, 0.61V 58.5W, 0.61V
PH202(ohm) 7.3092K 26.11K BR 65W 84.5W, 0.61V 84.5W, 0.61V
PH202 under CPU botten side :

CPU thermal protection at 96 degree C ( shutdown )
Recovery at 56 degree C +EC_VCCA
2013/10/02
Add for ENE9022 Battery Voltage drop detection. ADP_I <24,40>
3
Connect to ENE9022 pin64 AD1. 3
1
135W@PR211
PR210 65W@ 20K_0402_1%
PR211
Reserve for 2-cell design 16.9K_0402_1%
4.53K_0402_1%
2
<24> 9022_PH1
+19VB_5V
9022_VCIN <24>
1
PH202
1
@ PR213 100K_0402_1%_B25/50 4250K

80.6K_0402_1%
B value:4250K± 1%
2
@ PR214
2
0_0402_5%
1 2 VCIN1_BATT_DROP <24> @
T1
1
@
T2 PR215
1
10K_0402_1%
2
1
@ PC204 @ PR216
0_0402_5%
PR217
0.1U_0402_25V6 10K_0402_1%
2
1
2
4 4
ECAGND

BATTERY CONN / OTP
Custom 1.0
A B C D
A B C D
Protection for reverse input

max Power loss 0.22W for 90W, Isat: 4A
PQ301 Vgs = 20V (PR303 need change 10m ohm); DCR: 27mohm
1
2N7002KW _SOT323-3 D
2
Vds = 60V 0.12W for 65W system
G Id = 250mA CSR rating: 1W +19VB
S
VACP-VACN spec < 80.64mV
3
PR302 PR303
1M_0402_5% 3M_0402_5% Rds(on) typ=15.8mohm max
1 2 1 2
Vgs=20V Rds(on) typ=15.8mohm max
Vds=30V Vgs=20V
1
Need check the SOA for inrush ID= 10.5A (Ta=70C) Vds=30V 1
ID= 10.5A (Ta=70C)

+19V_VIN
+19V_P1 +19V_P2
1 1 PR304 +19VB_CHG
2 2 0.01_1206_1% @ PJ301 1
5 3 3 5 1 4 1 2 2
1 2 5 3
2200P_0402_25V7K
10U_0805_25V6K
10U_0805_25V6K
2 3 JUMP_43X79
2200P_0402_50V7K
0.1U_0402_25V6
0.1U_0402_25V6
0.1U_0402_25V6
PQ302 PQ304
4
EMI@ PC324
@EMI@ PC306
1
1
PC303
PC304
EMI@ PC305
0_0402_5% PQ303 AON7506_DFN33-8-5
0.01U_0402_50V7K
PC301
@ PR301
4
1
1
AON7506_DFN33-8-5 +19V_VIN
PC302
PC307
AON6366E_DFN5X6-8-5
2
2
VF = 0.5V
2
2
3
2
PD301 PR305
ACDRV_CHG_R 4.12K_0603_1%
BAS40CW _SOT323-3
0.1U_0402_25V6
BATDRV_CHG 1 2BATDRV_CHG_R
0.1U_0402_25V6
Rds(on) = 30mohm max
1
1
PC308
PC310
Vgs = 20V
1 1
1 2 PC311
10_1206_1%
0.047U_0402_25V7K Vds = 30V
PR306
2
PC309 1 2 BST_CHG_R ID = 7A (Ta=70C)
0.1U_0402_25V6 VF = 0.37V
5
2.2_0603_5%
PR307
PD302 PQ305
2
RB751V-40_SOD323-2 AON7506_DFN33-8-5
7X7X3 Power loss: 0.32W for 3.5A
VCC_CHG
@ PR308
Isat: 3.8A CSR rating: 1W
2
UG_CHG 1 2UG_CHG_R 4
VSRP-VSRN spec < 81.28mV
4.12K_0603_1%
4.12K_0603_1%
2 2
0_0402_5%
1
REGN_CHG
PC312 +17.4V_BATT
BST_CHG
PR309
PR310
UG_CHG
1 2
LX_CHG
PL302 PR311
3
2
1
1U_0603_25V6K 1 2 4.7UH_5.5A _20%_7X7X3_M 0.01_1206_1%
ACN_CHG
LX_CHG 1 2 LX_CHG_R1 4
2
PC313
1U_0603_25V6K 2 3
20
19
18
17
16
SRP_CHG_R
PU301 PQ306
1SRN_CHG_R
5
1
AON7506_DFN33-8-5
680P_0402_50V7K 4.7_1206_5%
VCC
PHASE
HIDRV
BTST
REGN
10U_0805_25V6K
10U_0805_25V6K
21
@EMI@ PC318 @EMI@ PR312

PAD
0.1U_0402_25V6
0.1U_0402_25V6
PC314
PC315
1
1
1 15 LG_CHG
ACN LODRV
PC316
PC317
2
1
4
2
ACP_CHG 2 14
ACP GND PR313
2
1
10_0603_1%
CMSRC_CHG 3 13 SRP_CHG
1 2 SRP_CHG_R
3
2
1
CMSRC SRP
1
PR314
2
BQ24735RGRR_QFN20_3P5X3P5 6.8_0603_1%
ACDRV_CHG 4 12 SRN_CHG
1 2 SRN_CHG_R
2
ACDRV SRN PC319
For 4S per cell 4.35V battery 1 2 5 11 BATDRV_CHG
0.1U_0603_16V7K
+3VLP ACOK BATDRV
PR315
ACDET
100K_0402_1%
IOUT
SDA
SCL
ILIM
ACDET_CHG
<24> ACIN
6
10
PR319
1
3
316K_0402_1% 3
PR316 ILIM_CHG 1 2
+3VLP
2M_0402_1%
100K_0402_1%
0.01U_0402_25V7K
ACDET_CHG
1
IOUT_CHG
PC320
PR318
2
1
PR321
422K_0402_1%
1
1 2
+19V_VIN
2
PR320
2
1_0402_5%
1 2
PQ307
PR322 LTC015EUBFS8TL_UMT3F
100K_0402_1%
1 2 2
2200P_0402_50V7K
<24> BATT_4S EC_SMB_CK1 <24,39>

66.5K_0402_1%
100P_0402_50V8J
1
1
1
PR323
PC321
PC322
3
EC_SMB_DA1 <24,39>
1
D
2
2 PQ308
<24,25,42> SUSP#
2
G 2N7002KW _SOT323-3
1 2
S ADP_I <24,39>
3
PR324
499_0402_1% PC323
2.2U_0402_6.3V6M
2
Close EC chip
4 4
Vin Dectector
Min. Typ Max.
L-->H 17.16V 17.63V 18.12V CZ@ PR320 change to 499ohm for prochot delay
H-->L 16.76V 17.22V 17.70V
VILIM = 20*ILIM*Rsr Issued Date 2017/04/18 Deciphered Date 2019/04/18 Title
ILIM = 3.3*100/(100+316)/20/0.01 CHARGER
= 3.966 A THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Custom 1.0
A B C D
A B C D E
1 1
+3VLP
PC401
1U_0402_10V6K
1 2
Output capacitor ESR need follow

@ PC402 @ PC403
100P_0402_50V8J 100P_0402_50V8J
below equation to make sure feed back
1 2 1 2 loop stability
ESR=20mV*L*fsw/2V
PR402 PR401
13.7K_0402_1% 30.9K_0402_1%
1 2 1 2
VFB=2V VFB=2V
PR403 PR404
20K_0402_1% 20K_0402_1% +19VB_5V
1 2 1 2 +19VB @ PJ401
JUMP_43X79
1 2
1 2
PR405 PR406
71.5K_0402_1% 107K_0402_1%
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
@ PJ402 1 2 1 2
+19VB JUMP_43X79
1
+19VB_3V
@EMI@ PC404
EMI@ PC405
PC406
PC422
1 2
2 1 2 2
CS2_3V
CS1_5V
+3VLP
FB_3V
FB_5V
POK need pull high, it
2
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
will pull high on VS

transfer circuit
1
1
@EMI@ PC407
EMI@ PC408
PC409
PC421
PU401
21
5
1
PR407 RT6575DGQW(2)_WQFN20_3X3
2
100K_0402_1%
CS2
FB2
LDO3
FB1
CS1
GND
1
PQ402 6 20 5V_EN PQ401
<24> 3V_EN EN2 EN1
AON7934_DFN3X3A8-10 AON7934_DFN3X3A8-10
7 19
<24> SPOK PGOOD VCLK
4
4
LX_3V 8 18 LX_5V
D1
D1
D1
G1
G1
D1
D1
D1
PL402 PC410 PR408 PHASE2 PHASE1 PR409 PC411 PL401
3.3UH_6.3A_20%_7X7X3_M 0.1U_0402_25V6 2.2_0603_5% 2.2_0603_5% 0.1U_0402_25V6 3.3UH_PCMB103T-3R3MS_9A_20%
2 1 LX_3V 10 9 1 2 BST_3V_R 1 2 BST_3V 9 17 BST_5V 1 2 BST_5V_R 1 2 9 10 LX_5V 2 1 +5VALWP
+3VALWP D1 D2/S1 BOOT2 BOOT1 D2/S1 D1
@EMI@ PR410
UG_3V UG_5V
4.7_1206_5%
680P_0603_50V8J 4.7_1206_5%
10 16
G2
G2
S2
S2
S2
S2
S2
S2
UGATE2 UGATE1
@EMI@ PR411
LGATE2
LGATE1
220U_6.3V_ESR18M_6.3X4.5
5
5
220U_6.3V_ESR18M_6.3X4.5
LDO5
BYP1
VIN
1 1
2
2
+ +
PC413
PC414
11
VIN_3/5V 12
13
14
15
680P_0603_50V8J
1
1
2 LG_3V LG_5V 2
@EMI@ PC416
@EMI@ PC417
3 PR412 3
2.2_1206_1%
+5VALWP
2
2
+19VB 1 2
+5VLP
1U_0603_25V6K
1
1
@ PC418
PC419
1U_0402_10V6K
2
Due to buyer command.

PC401,PC419 need change to SE00000QL10.
Because 0603 change to 0402, PVT need change footprint. @ PJ403
+3VALWP 1 2 +3VALW
PR413 1 2
2.2K_0402_5% JUMP_43X118
1 2
<24> EC_ON @ PR414
0_0402_5%
1 2
<24,35,39> MAINPWON
@ PJ404
+5VALWP 1 2 +5VALW
1 2
4 5V_EN JUMP_43X118 4
1M_0402_1%
4.7U_0402_6.3V6M
1
1
PR415
PC420
2

2
+3VALW/+5VALW
Custom 1.0
A B C D E
5 4 3 2 1
Pin19 need pull separate from +1.5VP.

If you have +1.5V and +0.75V sequence question, 0.75Volt +/- 5%
you can change from +1.5VP to +1.5VS. TDC 0.7A
@ PJ504
D 1 2 +19VB_1.5V PR501 Peak Current 1A D
+19VB 1 2 2.2_0603_5%
BST_1.5V_R BST_1.5V
2200P_0402_50V7K
10U_0805_25V6K
10U_0805_25V6K
JUMP_43X79 1 2
+1.2VP
0.1U_0402_25V6
0.1U_0402_25V6
1
1
EMI@ PC525
@EMI@ PC501
EMI@ PC502
PC503
PC504
UG_1.5V +0.6VSP
0.1U_0603_25V7K
2
2
LX_1.5V
10U_0603_6.3V6M
10U_0603_6.3V6M
5
1
PC505
PC506
PC507
AON7408L_DFN8-5
16
17
18
19
20
2
PU501
2
PHASE
BOOT
VTT
UGATE
VLDOIN
4 21
PAD
PQ501
LG_1.5V 15 1
LGATE VTTGND
1
2
3
14 2
PL503 PR502 PGND VTTSNS
1UH_6.6A_20%_5X5X3_M 25.5K_0402_1%
1 2 1 2 CS_1.5V 13 3
+1.2VP PC508 CS RT8207PGQW_WQFN20_3X3 GND
1
1U_0402_10V6K
1 2 12 4 VTTREF_1.5V
VDDP VTTREF
5
@EMI@ PR503 PR504
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
4.7_1206_5% PQ502 5.1_0603_5%

1
AON7506_DFN3X3-8-5 1 2 VDD_1.5V 11 5
+5VALW +1.2VP
1 2
VDD VDDQ
1
PC511
PC512
PC513
PC514
PC515
PC516
PGOOD
2
PC509
TON
2
1
C @EMI@ PC517 4 PR505 0.033U_0402_16V7K C
FB
S5
S3
2
680P_0402_50V7K PC510 2.2_0603_5%
2
1U_0402_10V6K
10
6
1
1
2
3
EN_0.75VSP
FB_1.5V
TON_1.5V
PR506
EN_1.5V
6.19K_0402_1%
+5VALW PR507 1 2 +1.2VP
470K_0402_1%
+19VB_1.5V 1 2
H/S AON7408 Rds(on) :typ:27mOhm, max:34mOhm
Idsm(TA=25)=7.5A, Idsm(TA=70)=5.5A
1
Mode Level +0.75VSP VTTREF_1.5V
S5 L off off L/S AON7506 Rds(on) :typ:13mOhm, max:15.8mOhm @ PR509 PR508 0.75*(1+6.19/10)=1.21
S3 L off on Idsm(TA=25)=12A, Idsm(TA=70)=10.5A 0_0402_5% 10K_0402_1%
S0 H on on <24> SYSON
1 2
2
Choke: 7x7x3
Note: S3 - sleep ; S5 - power off
1
Rdc=8mohm(Typ), 11mohm(Max) @ PC518
0.1U_0402_10V7K
2
Switching Frequency: 530kHz
Ipeak=11.5A
@ PR510
Iocp~13.8A 0_0402_5%
OVP: 110%~120% 1 2 @ PJ501
<24,25,40> SUSP#
VFB=0.75V, Vout=1.515V +1.2VP 1
1 2
2 +1.2V
1
JUMP_43X118
@ PC519
+5VALW 0.1U_0402_10V7K
2
B B
+3VALW
Due to buyer command. @ PJ502
1 2
PC508,PC510 need change to SE00000QL10. +0.6VSP 1 2 +0.6VS
@ PJ505 Because 0603 change to 0402, PVT need change footprint. JUMP_43X39
1
1 2 VIN_2.5V PC524
1 2
1
JUMP_43X39 1U_0402_6.3V6K
2
PC521
2
4.7U_0402_6.3V6M @ PJ503
1 2
+2.5VP 1 2 +2.5V
JUMP_43X39
PU502 G9661MF11U_SO8
@ PR515 4 5
0_0402_5% 3 VDD NC 6
SYSON 1 2 EN_2.5V 2 VIN VOUT 7 +2.5VP
GND
EN ADJ 8
22U_0603_6.3V6M
0.01U_0402_25V7K
1
PGOOD GND
1
0.1U_0402_16V7K
PC522
PR512
9
1
1
PC520
PC523
PR511
21.5K_0402_1%
Rup
2
1M_0402_5%
2
2
2
@ FB_2.5V
1
PR513
10K_0402_1%
Rdown
2
A A
Vout=0.8V* (1+(21.5/10)) = 2.52V 0.8%

+1.5VP/+0.75VSP
Custom 1.0
5 4 3 2 1
5 4 3 2 1
EN pin don't floating Module model information

If have pull down resistor at HW side, pls delete PR2
D SY8208D_V1.mdd D
+19VB @ PJ604 PU601

1 2 +19VB_VDDP 2 9 @ PR603 PC602 @EMI@ PR602 @EMI@ PC603
1 2 IN PG 0_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0603_50V7K
3 1 BST_VDDP 1 2 1 2 1 2SNB_VDDP 1 2
0.1U_0402_25V6
0.1U_0402_25V6
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
JUMP_43X79 IN BS
1
EMI@ PC620
@EMI@ PC604
4 6
EMI@ PC601
LDO_VDDP IN LX
2
5 19 PL602
PC605
PC622
IN LX .68UH_PCMC063T-R68MN_15.5A_20%
1
LX_VDDP
7
GND LX
20
FB_VDDP
1 2
+0.95VALWP
@ PR604 8 14
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
GND FB
0_0402_5%
330P_0402_50V7K
1
LDO_VDDP
@ PR601 18 17
(R1)
2
ILMT_VDDP 0_0402_5% GND VCC
PC606
PC607
PC608
PC609
PC610
PC611
1
1
<24> 0.95_1.8VALW_PWREN 1 2 11 10 PC612
PC613
2
EN NC
1
2.2U_0402_6.3V6M PR606
ILMT_VDDP 13 12 16K_0402_1%
2
@ PR605 ILMT NC
1
0_0402_5% 15 16
+3VALW
2
BYP NC
1
PR607 @ PC614
2
1M_0402_1% 0.22U_0402_10V6K PAD

21 PC609, PC610 from 47U_0603_6.3V6M change to
1
22U_0603_6.3V6M 2013/10/23
2
PC615 SY8288RAC_QFN20_3X3
2
1U_0402_6.3V6K
2
FB = 0.6V
@ PJ601
C BR@ PR609 1 2 +0.95VALW C
1 2
1
20K_0402_1% +0.95VALWP
SR@ PR609 JUMP_43X118
26.7K_0402_1%
(R2)
2
VFB=0.6V
Vout = 0.6V*(1+R1/R2)
SR Vout = 0.96V
BR Vout = 1.08V
1 2 0.95_1.8VALW_PWREN
FB=0.6V @ PR611
0.1U_0402_16V7K
0_0402_5%
1
Note:Iload(max)=3.5A PR612
1M_0402_5%
PC616
Note:Iload(max)=2.5A
2
PU602 @
9
1 PGND 8
FB SGND
2 7 PL603
@ PJ602 PG EN 1UH_2.8A_30%_4X4X2_F @ PJ603
+3VALWP 1 2IN_1.8VALW 3 6 LX_1.8VALW 1 2 +1.8VALWP 1 2
B 1 2 IN LX +1.8VALWP 1 2 +1.8VALW B
4 5
68P_0402_50V8J
JUMP_43X79 PGND NC JUMP_43X79

1
1
@EMI@ PR613
4.7_0603_5%
1
PC618
22U_0603_6.3V6M
22U_0603_6.3V6M
1
PC617
SY8003ADFC_DFN8_2X2 PR614
20K_0402_1%
Rup
PC619
PC623
2
22U_0603_6.3V6M
2
FB_1.8VALW
1
680P_0402_50V7K
FB=0.6V
@EMI@ PC621
1
Note:Iload(max)=3A PR615
Rdown
10K_0402_1%
2
Note:
When design Vin=5V, please stuff snubber Vout=0.6V* (1+Rup/Rdown)
to prevent Vin damage
A A

+0.95VALW/+1.8VALW
C 1.0
5 4 3 2 1
5 4 3 2 1
Av = PR766/PR769
Module model information 35W Core_OCP=70A, NB_OCP=21A, GFX_OCP=57A
= Gi/Rdroop 15W Core_OCP=44A, NB_OCP=21A, GFX_OCP=44A
<8,45> APU_VSS_SEN_L APU_CORE_SEN_H <8> RT8880C_CZ35W_V2A.mdd for IC portion
Gi = Rsense*Rimon*0.4/PR709
PC802
RT8880C_CZ35W_V2B.mdd for SW portion
1
0.01U_0402_50V7K Rimon (25 degree) = ( (RH704+PR742)//PR772 )+PR770
PR801 PR802
10_0402_5% 10_0402_5%
Rimona (25 degree)= ( (RH702+PR741)//PR721 )+PR740
2
1 2 1 2 +19VB_CPU
+APU_CORE
EMI@ PL801
5A_Z120_25M_0805_2P
1 2
+19VB
15W _CPU@ 15W _CPU@
PR806 +5VS +5VS PR807 PR803 EMI@ PL802
10U_0805_25V6K
10U_0805_25V6K
33U_25V_NC_6.3X4.5
33U_25V_NC_6.3X4.5
78.7K_0402_1% 97.6K_0402_1% 0_0603_5% 1 1 5A_Z120_25M_0805_2P
2ISEN2N_CPU
2ISEN2P_CPU
UG1_NB 1 2UG1_NB_R 1 2
1
+ +
PC803
PC804
PC820
BR@ PC904
35W_CPU@ PR843 0_0402_5%
15W_CPU@ PR844 0_0402_5%
35W_CPU@ PR845 0_0402_5%
15W_CPU@ PR846 0_0402_5%

D
1 2 LL(Rdroop)=2.079m D
2
PC801 @ 2 2
2
330P_0402_50V7K 35W _CPU@ PQ801
PR805 PR806 35W _CPU@ S TR AON6992 2N DFN5X6D APU_CORE_NB
G1
D1
10K_0402_1% 53.6K_0402_1% PR807 PR804 PC805 PL803
1 2 1 2 88.7K_0402_1% +19VB_CPU 2.2_0603_5%
BST1_NB
0.22U_0603_25V7K 0.22UH_24A_20%_ 7X7X4_M TDC 12A
1 2 1 2 BST1_NB1_R
1 2 7 1 4
+APU_CORE_NB Peak Current 17 A
1
D2/S1
ISENA1P_CPU_R 2
PC807 PC808 3 OCP current > 17A
1
470P_0402_50V8J 68P_0402_50V8J PR809
G2
@EMI@ PC811 @EMI@ PR808

S2
S2
S2
Load line -4mV/A
680P_0603_50V7K 4.7_1206_5%
1 2 1 2 LX1_NB
2.49K_0402_1%
CORE SW= 430KHz 1 2 1 2 FSW=450kHz
3
+5VS
LG1_NB
PC806 DCR 0.98mohm +/-5%
2
SNB_APU_NB
0.1U_0402_25V6
TYP MAX
ISEN2N_CPU_IC
ISEN2P_CPU_IC
H/S Rds(on) :11.7mohm , 14mohm
1
COMP_CPU
TONSET_CPU
ISEN1N_CPU
ISEN1P_CPU
L/S Rds(on) :2.7mohm , 3.3mohm
BST2_CPU
FB_CPU
UG2_CPU
+5VS
ISENA1N_CPU-1
PU801
Iocp_spikea = (3.19375 - 0.64)* PR755/ (2*DCR*Rimona)
13
12
11
10
ISENA1P_CPU
1
RT8880CGQW_WQFN52_6X6
Iocp_TDCA has relation between ocp_spikea and ∆ VSET1
TONSET
PWM3
BOOT2
UGATE2
VSEN
ISEN3N
ISEN1N
ISEN2N
COMP
FB
ISEN3P
ISEN1P
ISEN2P
53 ISENA1N_CPU 1 2
∆ VSET1 = +5VS*( PR788//PR784 ) GND +5VALW PR810
14 52 LX2_CPU
PR811 845_0402_1%
0.1U_0402_25V6
RGND PHASE2
1
2.2_0402_5%
PC812
IMON_CPU 15 51 LG2_CPU PVCC_CPU 1 2
IMON LGATE2
SVD_CPU and SVC_CPURC filter put CPU side. VREF_CPU 16 PVCC_CPU
2
50 @
SVT_CPU RC filter put controller side. V064 PVCC VCC_CPU 1 2
IMONA_CPU 17 49 LG1_CPU
PC813
2.2U_0603_10V6K
IMONA LGATE1
1
1U_0402_6.3V6K +1.8VS PR812
PC814
PC815
2.2U_0603_10V6K
1 2 18 48 LX1_CPU
10_0603_5% 35W _CPU@
VDDIO PHASE1 PR817 0_0603_5%
UG1_CPU UG2_CPU UG2_CPU_R
2
19 47 1 2
<8,45> APU_PWROK PWROK UGATE1 +19VB_CPU
APU_SVC 20 46 BST1_CPU
<8> APU_SVC SVC BOOT1
APU_SVD 21 45 LG1_NB
15W _CPU@
35W_CPU@ PC819
35W_CPU@ PC818
<8> APU_SVD SVD LGATEA1
PR816
35W_EMI@ PC822
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
1 2 APU_SVT 22 44 LX1_NB
28K_0402_1%
@EMI@ PC821
<8> APU_SVT_R SVT PHASEA1
1
UG1_NB
1
@ PR815 23 43 35W _CPU@ PQ802
0_0402_5% OFS UGATEA1 S TR AON6992 2N DFN5X6D
BST1_NB LX2_CPU
2
2
2
35W _CPU@ 24 42
2
C PR816 PR818 OFSA BOOTA1 C
G1
D1
SET1_CPU 25 41
15K_0402_1% 20.5K_0402_1% +5VS PR819 35W _CPU@ 35W _CPU@
SET1 PWMA2
15W _CPU@
PR821
SET2_CPU 26 40
88.7K_0402_1%
1 2 +19VB_CPU
PR820 2.2_0603_5% PC824 0.22U_0603_25V7K
BST2_CPU1 2 BST2_CPU_R1 2 7
APU_core
TDC 39A(1H2L)
1
5.11K_0402_1% SET2 TONSETA D2/S1
PGOODA
ISENA2N
ISENA1N
ISENA2P
ISENA1P
PGOOD
COMPA
35W _CPU@ 35W _CPU@ PL804
VSENA
Peak Current 55A
OCP_L
IBIAS
PR821 PR822 0.22UH_24A_20%_ 7X7X4_M
G2
S2
S2
S2
VCC
FBA
CORE_NB SW= 454 KHz 1 4 OCP current > 71A
EN
9.76K_0402_1% 7.32K_0402_1%
1 2 1 2
ISEN2P_CPU_R2 +APU_CORE Load line -2.1mV/A
3
100K_0402_1%_B25/50 4250K
@EMI@ PR824
4.7_1206_5%
27
28
1 IBIAS_CPU 29
COMPA_CPU 30
31
32
33
34
35
36
37
38
39
LG2_CPU
FSW=450kHz
100K_0402_1%_B25/50 4250K
Confirm HW side the pull high resistor
1
1
15W _CPU@ 35W _CPU@ 35W _CPU@
VGATE <24> DCR 0.98mohm +/-5%
VCC_CPU
FBA_CPU
ISENA1N_CPU
ISENA1P_CPU
PR825 PR825 PR823 PR826 2.26K_0603_1%
PH801
PH802
1 2 1 2
21.5K_0402_1% 16.9K_0402_1% 19.1K_0402_1% TYP MAX
VREF_CPU
APU_PROCHOT# <8,16,24,45> 1 2
+3VS SNB_APU
35W _CPU@ PC825 H/S Rds(on) :11.7mohm , 14mohm
2
1 2
0.1U_0402_25V6
Pull high at HW side PR828 100K_0402_5% L/S Rds(on) :2.7mohm , 3.3mohm
@EMI@ PC826
100K_0402_1%
680P_0603_50V7K
+5VS
0.47U_0402_6.3V6K
0.47U_0402_6.3V6K
VR_ON <24,45>
PR827
2
1
1
PC827
2
EN: high > 2V, Low < 0.8V
PC828
Can't be floating.
2
0.1U_0402_25V6
1
1
PC829 PC830 @ PR829
PC831
ISEN2N_CPU_R
ISEN2P_CPU
68P_0402_50V8J 470P_0402_50V8J 10K_0402_5%
1 2 1 2
2
@
2
Iocp_spike = (3.19375 - 0.64)* PR709/ (DCR*Rimon) 35W _CPU@ PR830
1.1K_0402_1%
ISEN2N_CPU 1 2
Iocp_TDC has relation between ocp_spike and ∆ VSET1 1 2 1 2
0.1U_0402_25V6
@ PC833
PC832
1
∆ VSET1 = +5VS*( PR788//PR784 ) PR831 PR832 330P_0402_50V7K
84.5K_0402_1% 10K_0402_1% 1 2
@
2
LL_NB(Rdroop)=3.992m
APU_VSS_SEN_L
PR833
SET1_CPU
10_0402_5% +19VB_CPU
PR834 PR835 1 2
+APU_CORE_NB
8.2K_0402_1% 124K_0402_1% PR838
1
1 2 1 2 0_0603_5%
UG1_CPU 1 2 UG1_CPU_R
PC838
10U_0805_25V6K
10U_0805_25V6K
PR836 PR837 VCC_CPU
2
B 470_0402_1% 33K_0402_1% 0.01U_0402_50V7K B
1
1 2 1 2 PQ803
PC839
PC840
APU_CORENB_SEN_H PQ804 15W _CPU@
<8>
S TR AON6992 2N DFN5X6D S TR AON6992 2N DFN5X6D
SET2_CPU
LX1_CPU
2
1
2
G1
D1
G1
D1
PR839 PC841 0.22UH_24A_20%_ 7X7X4_M
PL805
2.2_0603_5% 0.22U_0603_25V7K
BST1_CPU1 2 BST1_CPU_R
1 2 7 7 1 4
D2/S1 D2/S1
PR840 @EMI@
ISEN1P_CPU_R +APU_CORE
2 3
4.7_1206_5%
G2
G2
S2
S2
S2
S2
S2
S2
1
PR841
2.26K_0603_1%
3
1 2 1 2
LG1_CPU
PC842
SNB_APU2
1 2
0.1U_0402_25V6
@EMI@ PC843
680P_0603_50V7K
2
ISEN1N_CPU_R
ISEN1P_CPU
PR842
1.1K_0402_1%
ISEN1N_CPU 1 2
0.1U_0402_25V6
1
PC844
2
@
A A

RT8880CGQW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
5 4 3 2 1
5 4 3 2 1
<8,44> APU_VSS_SEN_L <8> APU_COREGFX_SEN_H

Av = PR766/PR769 Module model information
= Gi/Rdroop
1
BR@ PR901 BR@ PR902 BR@ PC901
RT8880C_CZ_GFX35W_V2A.mdd for IC portion
10_0402_5% 10_0402_5% 0.01U_0402_50V7K Gi = Rsense*Rimon*0.4/PR709
2
1 2 1 2
+APU_GFX RT8880C_CZ_GFX35W_V2B.mdd for SW portion
D Rimon (25 degree)= ( (RH704+PR742)//PR772 )+PR770 D
BR_15W_CPU@
PR903
78.7K_0402_1% +5VS +5VS BR_15W_CPU@
PR906 +19VB_GFX BR_EMI@ PL901
2ISEN2N_GFX
2ISEN2P_GFX
97.6K_0402_1% 5A_Z120_25M_0805_2P
LL(Rdroop)=2.04m 1 2
BR_35W_CPU@ PR933 0_0402_5%
BR_15W_CPU@ PR934 0_0402_5%
BR_35W_CPU@ PR935 0_0402_5%
BR_15W_CPU@ PR936 0_0402_5%

+19VB_CPU
1 2 BR@ PR904
0_0603_5% BR_EMI@ PL902
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
2200P_0402_50V7K
UG1_GFX 1 2 UG1_GFX_R
@ PC902 5A_Z120_25M_0805_2P
@EMI@ PC905
BR_EMI@ PC907
2
1
330P_0402_50V7K BR_35W_CPU@ 1 2
BR@ PC903
BR@ PC906
1
1
BR@ PR905 PR903 BR_35W_CPU@ PQ903
10K_0402_1% 71.5K_0402_1% PR906 BR_15W_CPU@ BR@ PQ901
LX1_GFX
2
1 2 1 2 88.7K_0402_1% S TR AON6992 2N DFN5X6D S TR AON6992 2N DFN5X6D
+19VB_GFX
2
1
2
1 2
G1
D1
G1
D1
BR@ PC908 BR@ PC909 BR@ PR907
470P_0402_50V8J 68P_0402_50V8J Fsw(max) =451KHz 2.2_0603_5%
BST1_GFX
1 2 1 2 1 2 BST1_GFX_R1 2 7 7
D2/S1 D2/S1 BR@ PL903
BR@ PC910 0.22UH_24A_20%_ 7X7X4_M
0.22U_0603_25V7K 1 4
G2
G2
S2
S2
S2
S2
S2
S2
TONSET_GFX
ISEN1P_GFX_R2 +APU_GFX
3
@EMI@ PR908
4.7_1206_5%
6
3
COMP_GFX
FB_GFX
ISEN1N_GFX
ISEN1P_GFX
1
BR@ PR909
BST2_GFX
UG2_GFX
+5VS 2.26K_0603_1%
+5VS LG1_GFX 1 2 1 2
BR@ PC911
1 2
SNB_GFX
BR@ PU901 0.1U_0402_25V6
@EMI@ PC912
13
12
11
10
680P_0603_50V7K
9
1
RT8880CGQW_WQFN52_6X6
TONSET
PWM3
BOOT2
UGATE2
VSEN
ISEN3N
ISEN1N
ISEN2N
COMP
FB
ISEN3P
ISEN1P
ISEN2P
2
SVD_GFX and SVC_GFX RC filter put CPU side. 53
GND
SVT_GFX RC filter put controller side. 14 52 LX2_GFX
BR@ PR910
+5VALW
RGND PHASE2 2.2_0402_5%

IMON_GFX 15 51 LG2_GFX PVCC_GFX 1 2
ISEN1N_GFX_R
IMON LGATE2 ISEN1P_GFX
VREF_GFX 16 50 PVCC_GFX
V064 PVCC VCC_GFX 1 2
17 49 LG1_GFX
BR@ PC913 BR@ PR912
1U_0402_6.3V6K +1.8VS IMONA LGATE1 BR@ PR911 1.1K_0402_1%
1 2 18 48 LX1_GFX ISEN1N_GFX 1 2
10_0603_5%
2.2U_0603_10V6K
2.2U_0603_10V6K
VDDIO PHASE1
1
BR@ PC914
BR@ PC915
19 47 UG1_GFX
0.1U_0402_25V6
<8,44> APU_PWROK PWROK UGATE1
PC916
GFX_SVC BST1_GFX
2
20 46
C
<8> GFX_SVC SVC BOOT1 C
GFX_SVD
2
21 45 @
<8> GFX_SVD SVD LGATEA1
1 2 GFX_SVT 22 44
BR_15W_CPU@ <8> GFX_SVT_R
PR916 SVT PHASEA1
28K_0402_1% @BR@ PR915 23 43
0_0402_5% OFS UGATEA1
2
BR_35W_CPU@ 24 42
PR916 OFSA BOOTA1
SET1_GFX 25 41
19.1K_0402_1% SET1 PWMA2 +5VS
SET2_GFX 26 40
1
BR_15W_CPU@ SET2 TONSETA
PGOODA
ISENA2N
ISENA1N
ISENA2P
ISENA1P
PGOOD
+19VB_GFX
COMPA
PR917
VSENA
OCP_L
IBIAS
5.11K_0402_1% BR_35W_CPU@
VCC
FBA
EN
PR917
7.87K_0402_1%
100K_0402_1%_B25/50 4250K
1 2
10U_0805_25V6K
10U_0805_25V6K
27
28
1 IBIAS_GFX 29
30
31
32
33
34
35
36
37
38
39
BR_35W_CPU@
Confirm HW side the pull high resistor BR_35W_CPU@
BR_35W_CPU@
1
PR918 0_0603_5%
PH901
<9> VDDGFX_PWRGD UG2_GFX 2 UG2_GFX_R
1
VCC_GFX
BR_35W_CPU@ 1
PC924
PC925
BR_15W_CPU@ PR919
PR919 18.7K_0402_1%
2
1
2
21.5K_0402_1% APU_PROCHOT# <8,16,24,44> 1 2 BR_35W_CPU@ PQ902
BR@
100K_0402_1%
+3VALW LX2_GFX
2
S TR AON6992 2N DFN5X6D
BR@ PR920
Pull high at HW side
G1
D1
+5VS BR@ PR921 BR_35W_CPU@ PL904
100K_0402_5% 0.22UH_24A_20%_ 7X7X4_M
VR_ON <24,44> BST2_GFX 1 2 BST2_GFX_R
1 2 7 1 4
D2/S1
1
PR924 @EMI@
ISEN2P_GFX_R2 +APU_GFX
BR@ PC927 2 EN: high > 2V, Low < 0.8V BR_35W_CPU@ PR922 BR_35W_CPU@ PC926 3
4.7_1206_5%
1
2.2_0603_5% 0.22U_0603_25V7K
G2
S2
S2
S2
0.47U_0402_6.3V6K Can't be floating.
0.1U_0402_25V6
2
1
@ PR923
PC929
1
10K_0402_5%
3
1 2 1 2
LG2_GFX
@ BR_35W_CPU@
2
PR925 BR_35W_CPU@
SNB_GFX2
1 2
2.26K_0603_1% PC928
0.1U_0402_25V6
@EMI@ PC930
680P_0603_50V7K
2
Iocp_spike = (3.19375 - 0.64)*PR709/ (DCR*Rimon) GFX_core
TDC 30A(1H2L)
Iocp_TDC has relation between ocp_spike and ∆ VSET1
Peak Current 45A
ISEN2N_GFX_R
∆ VSET1 = +5VS*( PR788//PR784 ) OCP current > 58.6A ISEN2P_GFX
Load line -2.1mV/A
FSW=450kHz BR_35W_CPU@
B DCR 0.98mohm +/-5% ISEN2N_GFX
PR926 1.1K_0402_1% B
TYP MAX 1 2
SET1_GFX
BR@ PR927 BR@ PR928 H/S Rds(on) :11.7mohm , 14mohm
0.1U_0402_25V6
1
8.2K_0402_1% 124K_0402_1%
L/S Rds(on) :2.7mohm , 3.3mohm
PC931
1 2 1 2
2
BR@ PR929 BR@ PR930 VCC_GFX @
470_0402_1% 33K_0402_1%
1 2 1 2
SET2_GFX
+3VALW
@
PJ904
1
+0.775VALWP 1 2 +0.775VALW
1 2
@
PJ903
1
2
2
PU902
VIN_0.775VALW 1
VIN NC
8 +3VALW
2 7
GND NC
1
PC933
1
4.7U_0402_6.3V6M 3 6 PC934
VREF VCNTL 1U_0402_6.3V6K
2
PR932 4 5
3.24K_0402_1% VOUT NC
9
2
TP
VREF_0.775VALW
G2992F1U
1
+0.775VALWP
1
PR931
1K_0402_1% PC932
1
0.1U_0402_16V7K
2
A PC935 A
2
10U_0603_6.3V6M
2
RT8880CGQW
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
5 4 3 2 1
A
B
C
D
@
PC9084
560U_D2_2VM_R4.5M
2
1
+
PC9085 PC9029 PC9001
220U_D2 SX_2VY_R9M 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1 2 1
2
1
+
near CPU
PC9086 PC9081 PC9056 PC9030 PC9002
220U_D2 SX_2VY_R9M 180P_0402_50V8J 0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
+
5
5
+APU_CORE
+APU_CORE
PC9057 PC9031 PC9003

0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
2
1
+
PC9087 PC9058 PC9032 PC9004
560U_D2_2VM_R4.5M 0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
PC9059 PC9033 PC9005

0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
180pF*1
220uF*2
560uF*1
2 1 2 1 2 1
PC9060 PC9034 PC9006
APU_CORE
0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
CPU back side

PC9061 PC9035 PC9007
0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
22uF*20+0.22uF*8
PC9062 PC9036 PC9008
0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
+APU_CORE
PC9063 PC9037 PC9009

0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
PC9038 PC9010
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
4
4
PC9088
220U_D2 SX_2VY_R9M
2
1
+
PC9039 PC9011
PC9064 22U_0603_6.3V6M 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1 2 1
2 1 2 1
PC9040 PC9012
near CPU
PC9082 PC9065 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
+
180P_0402_50V8J 0.22U_0402_10V6K 2 1 2 1
@ PC9089 2 1
220U_D2 SX_2VY_R9M PC9041 PC9013
PC9066 22U_0603_6.3V6M 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1 2 1
2 1
+APU_CORE_NB
PC9042 PC9014
PC9067 22U_0603_6.3V6M 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1 2 1
2 1
Issued Date
PC9043 PC9015
PC9068 22U_0603_6.3V6M 22U_0603_6.3V6M
180pF*1
220uF*1
0.22U_0402_10V6K 2 1 2 1
Security Classification
2 1
PC9044 PC9016
PC9069 22U_0603_6.3V6M 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1 2 1
2 1
APU_CORENB
3
3
PC9045 PC9017
PC9070 22U_0603_6.3V6M 22U_0603_6.3V6M
0.22U_0402_10V6K 2 1 2 1
22uF*17+0.22uF*8
2 1
+APU_CORE_NB
PC9018
PC9071 22U_0603_6.3V6M
2017/04/18
0.22U_0402_10V6K 2 1
2 1
PC9019
22U_0603_6.3V6M
2 1
PC9020
22U_0603_6.3V6M
2 1
Compal Secret Data

Deciphered Date
2
2
2019/04/18
2
1
+
@BR@ PC9090
CPU back side
560U_D2_2VM_R4.5M
BR@ PC9072 BR@ PC9046 BR@ PC9021

0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2
1
+
2 1 2 1 2 1 2 1
BR@ PC9091
560U_D2_2VM_R4.5M BR@ PC9083 BR@ PC9073 BR@ PC9047 BR@ PC9022
180P_0402_50V8J 0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
+APU_GFX
2 1 2 1 2 1
+APU_GFX
2
1
+
BR@ PC9092 BR@ PC9074 BR@ PC9048 BR@ PC9023

Title
Date:
220U_D2 SX_2VY_R9M 0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1
Custom
2
1
+
BR@ PC9075 BR@ PC9049 BR@ PC9024

BR@ PC9093 0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
220U_D2 SX_2VY_R9M 2 1 2 1 2 1
near CPU
+APU_GFX
BR@ PC9076 BR@ PC9050 BR@ PC9025

0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
Size Document Number
2 1 2 1 2 1
180pF*1
220uF*1
560uF*1
APU_GFX
BR@ PC9077 BR@ PC9051 BR@ PC9026

Tuesday, May 02, 2017
0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1
BR@ PC9078 BR@ PC9052 BR@ PC9027

0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1 2 1
1
1
22uF*18+0.22uF*9
BR@ PC9079 BR@ PC9053 BR@ PC9028

Sheet
0.22U_0402_10V6K 22U_0603_6.3V6M 22U_0603_6.3V6M

2 1 2 1 2 1
46
BR@ PC9080 BR@ PC9054

+APU_CORE Cap
0.22U_0402_10V6K 22U_0603_6.3V6M
Compal Electronics, Inc.
2 1 2 1
of
C5V08/D5PR8_LA-E903PR10
BR@ PC9055
22U_0603_6.3V6M
50
2 1
Rev
1.0
A
B
C
D
5 4 3 2 1
EN pin don't floating Module model information

If have pull down resistor at HW side, pls delete PR2
EA (C5V08): POP VGA_SY SY8208D_V1.mdd
VX (D5PR8): POP VGA_AOZ
D D
VGA_SY@
+19VB @ PJ1001 PU1001
1 2 +19VB_1.35V 2 9 @VGA_SY@ PR1001 VGA_SY@ PC1003 VGA_EMI@ PR1002 VGA_EMI@ PC1004
1 2 IN PG 0_0603_5% 0.1U_0603_25V7K 4.7_1206_5% 680P_0603_50V7K
VGA_SY_EMI@ PC1017
@VGA_SY_EMI@ PC1005
3 1 BST_1.35V 1 2 1 2 1 2SNUB_1.35V 1 2
VGA_SY_EMI@ PC1001
2200P_0402_50V7K
JUMP_43X79 IN BS
1
VGA_SY@ PC1006
VGA_SY@ PC1002
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
4 6
IN LX
chock 7*7*1.8
2
5 19 VGA@ PL1002
IN LX 0.68UH_PCMB061H-R68MS_9A_20%
LX_1.35V
7
GND LX
20
FB_1.35V
1 2
+1.35VSDGPUP
8 14
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
22U_0603_6.3V6M
GND FB
VGA@ PC1007
VGA@ PC1008
VGA@ PC1009
VGA@ PC1010
VGA@ PC1011
VGA@ PC1012
1
1
18 17 LDO_3V_1.35
@VGA@ PR1004
(R1)
330P_0402_50V7K
0_0402_5% GND VCC
VGA_SY@ PC1014
LDO_3V_1.35
1
1 2 1.35V_EN 11 10 VGA_SY@ PC1013
2
EN NC
1
<9,48> DGPU_PWROK 2.2U_0402_6.3V6M VGA_SY@ PR1006
C ILMT_1.35V 13 12 12.7K_0402_1% C
2
ILMT NC
1
2
1
15 16
+3VALW
2
BYP NC
1
@VGA_SY@ PR1003 VGA@ PR1007 @VGA@ PC1015
0_0402_5% 1M_0402_1% 0.22U_0402_10V6K 21
PAD
1
2
2
ILMT_1.35V VGA_SY@ PC1016 SY8288RAC_QFN20_3X3
2
1U_0402_6.3V6K
2
1
FB = 0.6V
@VGA_SY@ PR1005 @ PJ1002
0_0402_5% +1.35VSDGPUP 1 2 +1.35VSDGPU
1 2
2
1
JUMP_43X118
+5VS VGA_SY@ PR1009
VGA_AOZ@ PC1019 10K_0402_1%
VGA_AOZ@ PC1018 0.1U_0603_25V7K
1 2
(R2)
PR606 part count reduce 4.7U_0402_6.3V6M
2
1 2
VGA_AOZ@ PC1022
0.01UF_0402_25V7K
1 2
VFB=0.6V
B B
Vout=0.6V*(1+R1/R2)=1.362V
19
18
17
16
15
+19VB @ PJ1003 VGA_AOZ@ PU1002
1 2 +19VB_1.35V_AOZ
BST
SS
LX
VCC
PGND
1 2
VGA_AOZ_EMI@ PC1024
@VGA_AOZ_EMI@ PC1023
1 14 LX_1.35V
VGA_AOZ_EMI@ PC1020
2200P_0402_50V7K
JUMP_43X79 PGOOD LX
1
1
VGA_AOZ@ PC1021
VGA_AOZ@ PC1025
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
0.1U_0402_25V6
1.35V_EN 2 13
2
EN LX
3 12
PFM PGND
AOZ2260QI-10_QFN22_4X4
4 11
AGND PGND
1
VGA_AOZ@ PR1010
10K_0402_1% 5 10
FB PGND
1 2
6 9
TON PGND
LX
IN
1
A VGA_AOZ@ PR1008 VGA_AOZ@ A

6.98K_0402_1% PR1011
8
105K_0402_1%
VFB=0.8V
LX_1.35V
2
+1.35VSDGPUP 2017/04/18 2019/04/18 Title

2
Vout=0.6V*(1+R1/R2)=1.362V +19VB_1.35V_AOZ +GFX_CORE

Custom 1.0
5 4 3 2 1
5 4 3 2 1
VGA@ PC1401 VGA@ PR1405

330P_0402_50V7K 2K_0402_1% GPU_B1+
2 1 2 1 @ PJ1402
1 2
<22> GPU_VDDCI_SEN 1 2 +19VB
VGA@ PR1407 VGA@ PR1408 VGA@ PC1409 @ PR1409
40W_VGA@ PC1403
40W_VGA@ PC1404
PC1406
10U_0805_25V6K
10U_0805_25V6K
2200P_0402_50V7K
1K_0402_1% 37.4K_0402_1% 390P_0402_50V7K 32.4K_0402_1% JUMP_43X79
@EMI@ PC1405
0.1U_0402_25V6
D 2 1 2 1 2 1 2 1 D
GPU_UGATE3
1
1
40W_VGA_EMI@
VGA@ PR1401 @VGA@ PR1410 VGA@ PC1410 VGA@ PC1411
10_0402_1% 0_0402_5% 1000P_0402_50V7K 220P_0402_50V8J
2
2
2
2 1 1 2 2 1 2 1 2 1
+VDDCI
@ PC1412 VGA@ PR1411 40W _VGA@ PQ1401
VSUMP_NB
1000P_0402_50V7K 301_0402_1% S TR AON6992 2N DFN5X6D
1
VGA@ PR1412
2.61K_0402_1%
2 1
(DCR:0.98± 5 %
)
2
10K +-5% 0402 B25/50 4250K
0.01UF_0402_25V7K
40W _VGA@ PL1405
VGA@ PR1413
VGA@ PC1414
G1
D1
0.022U_0402_25V7K
2
2
40W _VGA@ PR1404 40W _VGA@ PC1407 0.22UH_24A_20%_ 7X7X4_M
VGA@PC1413
11K_0402_1%
2
2
2.2_0603_5% 0.22U_0603_25V7K 1 4
GPU_BOOT3 1 2 1 2 7 +VGA_CORE
1
D2/S1
1
40W _VGA@ PR1460 2 3

VGA@
PH1401
1 10K_0402_1% VGA_CORE
FCCM_NB GPU_ISEN3
1
1
VGA@ PR1414 @EMI@ PR1402 1 2
G2
S2
S2
S2
VSUMN_NB
2.37K_0402_1%
GPU_PHASE3
4.7_1206_5% TDC 15.75A
2 1 40W _VGA@ PR1461
Peak Current 22.5A
1 2
3
1
3.65K_0603_1%
@ PR1416 @ PC1423 VGA@ PR1415 VSUM+ 1 2 OCP current 31A
1 2
VGA@ PC1422 100_0402_1% 220P_0402_50V7K 41.2K_0402_1% @EMI@ PC1408
2 1 2 1 GPU_LGATE3
0.1U_0603_25V7K VGA@ PR1417 680P_0603_50V7K 40W _VGA@ PR1462
2
GPU_LGATE3
10K_0402_1% 1_0402_1%
GPU_PHASE3 TYP MAX
2
2 1 VSUM- 1 2
L/S Rds(on):1.2mohm ,2.3mohm
2
GPU_UGATE3
After rev1.1 must change to 133k
48
47
46
45
44
43
42
41
40
39
38
37
2
PU1401
2
VGA@ PR1418 GPU_B+
ISEN1_NB
ISUMP_NB
ISUMN_NB
VSEN_NB
FB_NB
COMP_NB
PGOOD_NB
FCCM_NB
PWM2_NB
LGATEX
PHASEX
UGATEX
133K_0402_1% VGA@ PC1424
1000P_0402_25V6K
GPU_BOOT3
1
VGA@ PR1421 VGA@ PR1422 1 36 @VGA@ PR1424 GPU_B+ @ PJ1401

+5VALW
1
27.4K_0402_1% 10.5K_0402_1% ISEN2_NB BOOTX 0_0603_5% 1 2

1 2 +19VB
2 1 2 1 2 35 2 1
NTC_NB VIN GPU_UGATE2
JUMP_43X79
GPU_BOOT2
VGA@ PH1402 3 34 Due to buyer command.
VGA_EMI@ PC1420
2200P_0402_50V7K
0.1U_0402_25V6K
IMON_NB BOOT2
1
470K_0402_5%_TSM0B474J4702RE
@EMI@ PC1419
PC1428,PC1429 need change to SE00000QL10.
10U_0805_25V6K
10U_0805_25V6K
2 1 4 33 GPU_UGATE2
VGA@ PC1427
VGA@ PC1417
VGA@ PC1418
<16> GPU_SVC SVC UGATE2 Because 0603 change to 0402, PVT need change footprint.
1
GPU_PHASE2 0.22U_0603_25V7K
2
5 32
<16> GPU_PROCHOT# VR_HOT_L PHASE2 VGA@ PQ1402
GPU_LGATE2
2
2
6 31 @VGA@ PR1428 S TR AON6992 2N DFN5X6D

<16> GPU_SVD SVD LGATE2
2
S IC ISL6277AHRZ-T QFN 48P 0_0603_5%
VGA@ PR1427 7 30 2 1
G1
D1
+1.8VSDGPU VDDIO VDDP +5VALW
100K_0402_1% VGA@ PR1425 VGA@ PC1425
C 8 29 2 1 2.2_0603_5% 0.22U_0603_25V7K C
<16> GPU_SVT GPU_BOOT2
1
@VGA@ PR1431 SVT VDD VGA@ PR1430 1 2 1 2 7

+3VS GPU_PWM3 D2/S1
10_0402_5%2 ENABLE 9 28 1_0603_5%
<25> VGA_ON_B ENABLE PWM_Y
VGA@ PC1428
VGA@ PC1429
1U_0402_16V6K
1U_0402_16V6K
DGPU_PWROK 10 GPU_LGATE1
1
VGA@ PR1433 27
(DCR:0.98± 5 %
)
G2
S2
S2
S2
133K_0402_1% PWROK LGATE1
1 2 11 26 GPU_PHASE1
VGA@ PL1403
3
IMON PHASE1
After rev1.1 must change to 133k GPU_UGATE1 GPU_PHASE2
0.22UH_24A_20%_ 7X7X4_M
VGA@ PC1434 2 1 12 25 1 4
NTC UGATE1
+VGA_CORE
PGOOD
1000P_0402_25V6K VGA@ PR1434
BOOT1
ISUMN
ISUMP
COMP
ISEN3
ISEN2
ISEN1
VSEN
1 2 10.5K_0402_1% VGA@ PR1420 2 3
RTN
FB2
10K_0402_1%
FB
TP
GPU_ISEN21
1
VGA@ PR1435 25W _VGA@PR1465 @EMI@ PR1419 2
0_0402_5% GPU_LGATE2
27.4K_0402_1% 4.7_1206_5%
13
14
15
16
17
18
19
20
21
22
23
24
49
2 1 1 2 VGA@ PR1423
+5VALW
VGA@ PR1436 3.65K_0603_1%
VSUM+ 1 2
GPU_ISEN3
GPU_ISEN2
GPU_ISEN1
VGA@ PH1403 40W _VGA@PC1436 100K_0402_1%
1 2
470K_0402_5%_TSM0B474J4702RE 0.22U_0402_6.3V6K 1 2 @EMI@ PC1426
GPU_BOOT1 +3VS
2 1 2 1 680P_0603_50V7K VGA@PR1426
1_0402_1%
VGA@ PC1437 DGPU_PWROK <9,47> VSUM- 1 2
2
0.22U_0402_6.3V6K
2 1
VGA@ PC1438
0.22U_0402_6.3V6K
2 1
VSUM+
1
VGA@ PC1439 VGA@ PR1440 VGA@ PC1440 @ PR1441 GPU_B+

VGA@ PR1439
2.61K_0402_1%
10K +-5% 0402 B25/50 4250K
1000P_0402_25V6K 301_0402_1% 180P_0402_50V8J 32.4K_0402_1%

Rdroop = 1.91K
0.047U_0603_25V7M
2 1 2 1 2 1 2 1
330P_0402_50V7K
0.22U_0603_25V7K
Ri = 768ohm
VGA@ PR1443
VGA@ PC1443
40W_VGA@ PC1444
VGA@ PC1446
2
25W _VGA@
Load Line = -0.9mV/A
11K_0402_1%
VGA_EMI@ PC1433
1 2
GPU_UGATE1
2
PR1446 VGA@ PR1447 VGA@ PC1445

VGA@ PH1404
2200P_0402_50V7K
1K_0402_1% 137K_0402_1% 390P_0402_50V7K
VGA@ PC1435
VGA@ PC1431
@EMI@ PC1432
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
1
1
1
2 1 2 1 2 1
1
25W _VGA@
1
PR1448 40W _VGA@
2
2
2
499_0402_1% PR1446 VGA@ PR1449 VGA@ PC1447
2
VSUM- 2 1 1.91K_0402_1% 2K_0402_1% 680P_0402_50V7K VGA@ PQ1403

2 1 2 1 S TR AON6992 2N DFN5X6D
2
1
@ PR1450 @ PC1449
G1
D1
VGA@ PC1448 100_0402_1%820P_0402_50V7K VGA@ PR1451 VGA@ PR1444 VGA@ PC1441
0.1U_0603_25V7K 2 1 2 1 10_0402_1% 2.2_0603_5% 0.22U_0603_25V7K
GPU_BOOT1
2
2 1 1 2 1 2 7
+VGA_CORE D2/S1
25W _VGA@
PC1444
40W _VGA@
PR1448
@VGA@ PR1452
0_0402_5% (DCR:0.98± 5 %
)
B 0.15U 25V K X7R 0603 634_0402_1% 1 2 GPU_VDDC_SEN <22> VGA@ PL1404 B
G2
S2
S2
S2
GPU_PHASE1
0.22UH_24A_20%_ 7X7X4_M
1 4
3
@VGA@ PR1453 +VGA_CORE
0.01UF_0402_25V7K
0_0402_5% VGA@ PR1438 2 3

1 2 GPU_VSS_SEN_L <22> 10K_0402_1%
GPU_ISEN11
1
@EMI@ PR1437 2
VGA@ PC1450
GPU_LGATE1
VGA@ PR1454 4.7_1206_5%
1
10_0402_1% VGA@PR1442
2 1
VSUM+
3.65K_0603_1%
1 2
VDDGFX
TDC 90A
2
1 2
@EMI@ PC1442
680P_0603_50V7K VGA@PR1445
1_0402_1%
Peak Current 100A
VSUM- 1 2 OCP current 120A
2
GPU_VDDCI
@ PJ1403
1 2
1 2 +19VB
UGATE_NB1
Due to buyer command. JUMP_43X79
VGA_EMI@ PC1460
PC1465 need change to SE00000QL10.
2200P_0402_50V7K
VGA@ PC1463
VGA@ PC1462
@EMI@ PC1461
10U_0805_25V6K
10U_0805_25V6K
0.1U_0402_25V6
Because 0603 change to 0402, PVT need change footprint.
1
2
2
VGA@ PQ1404
S TR AON6992 2N DFN5X6D
2
+5VS
G1
D1
2
VGA@ PC1466
0.22U_0603_16V7K 7
1
D2/S1
1
VGA@
PC1465
(DCR:4.3± 5%
) chock 7*7*1.8
G2
S2
S2
S2
1U_0402_10V6K
2
VGA@ PR1464 VGA@ PL1402
2.2_0603_5% 0.47UH_PCMB061H-R47MS_11A_20%
3
1 4
+VDDCI
2
2 3
UGATE_NB1
1
6 1
A VCC UGATE LGATE_NB1 A
FCCM_NB 7 2 BOOT_NB1
@EMI@ PR1463 VGA@ PR1403
FCCM BOOT 4.7_1206_5% 3.65K_0603_1%
GPU_PWM3 3 8 PHASE_NB1 VSUMP_NB 1 2
1 2
PWM PHASE
4 5 LGATE_NB1
VGA@ PR1406
9 GND LGATE @EMI@ PC1467 1_0402_1%
TP VSUMN_NB 1 2
680P_0603_50V7K
2
VGA@ PU1402
ISL6208BCRZ-T_QFN8_2X2
Title
<Title>
Size Document Number Rev

D C5V08/D5PR8_LA-E903PR10 1.0

5 4 3 2 1
A
B
C
D
5
5
+VGA_CORE
VGA@ PC1540
220U_D2 SX_2VY_R9M
+
2
1
@VGA@ PC1539
220U_D2 SX_2VY_R9M
+
2
1
@VGA@ PC1538
220U_D2 SX_2VY_R9M
2
1
+
@VGA@ PC1537
220U_D2 SX_2VY_R9M
+
2
1
VGA@ PC1501
220U_D2 SX_2VY_R9M
2
1
+
VGA@ PC1502
220U_D2 SX_2VY_R9M
2
1
+
@VGA@ PC1503
220U_D2 SX_2VY_R9M
+
2
1
VGA@ PC1504
220U_D2 SX_2VY_R9M
2
1
+
VGA@ PC1505
220U_D2 SX_2VY_R9M
2
1
+
@VGA@ PC1506
220U_D2 SX_2VY_R9M
2
1
+
4
4
VGA@ PC1517 VGA@ PC1507

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

+VGA_CORE
22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1

22U_0603_6.3V6M 22U_0603_6.3V6M
2 1 2 1
VGA@ PC1512
22U_0603_6.3V6M
2 1 2 1

2.2U_0402_6.3V6M 22U_0603_6.3V6M
2 1 2 1

2.2U_0402_6.3V6M 22U_0603_6.3V6M
2 1
VGA@ PC1515
22U_0603_6.3V6M
2 1
VGA@ PC1516
22U_0603_6.3V6M
2 1
+VDDCI
VGA@ PC1545
3
3
330U_D1_2VY_R9M
2
1
+
@VGA@ PC1546
22U_0603_6.3V6M
2 1
@VGA@ PC1547
22U_0603_6.3V6M
2 1
2
2
D
Title
Size
Date:
1
1
<Title>
Document Number
Tuesday, May 02, 2017

C5V08/D5PR8_LA-E903PR10
Sheet
49
of
50
Rev
1.0
A
B
C
D
5 4 3 2 1
Version change list (P.I.R. List) Page 1 of 1

for PWR
Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase
28 29
for EMI request for EMI request 02 pop PL301, PL403, PL501, PL901, PL902
01 30 33
D D
02 VSEN_GFX duplicate net name VSEN_GFX duplicate net name 01 PC1418 net name VSEN_GFX change to VSEN_VGA
2016/11/7
03 SPOK_5V to EC SPOK_5V to EC ，add SP OK_5 V net
PR410 change to 100K，
04 For B+ shape 好 APU_GFX input change to +19VB_APU from +19VB 2016/11/17
05 FAE suggest Add 3/5V input cap add PC421, pc422 2016/12/1
06 boost voltage is 12V boost voltage is 12V PR1603 change to 88.3K 2016/12/1
07 HW request HW request delete PC923, PR926,PC927, PR929,PC930 2016/12/1
08 follow BQ24735 module follow BQ24735 module PC321 change to 2200P from 0.22u 2016/12/12
09 機機機機 CPU肚肚機機 2 ， 560u F 放放放 PC9084 ，P C9 0 9 1改改 5 6 0u 2016/12/13
10 HW command PL1602 unpop PL1602 unpop 2017/02/02
VX:
delete PQ803 and PQ903 VX: PR211 change to 49.9k from 19.1k
PR405 change P/N. delete PL1602
11 Design change 2017/02/20
EA: EA: delete PC1024, PC1406, PL1602
delete PC1024, PC1406, PL1602
C C
Add PC9087
PR405 change P/N.
12 Add VDDCI output cap Add VDDCI output cap Add PC1545 220uF 2017/02/20
13 VDDCI ripple not meet spec. change VDDCI design PL1402 change to 0.47uH from 0.22uH
PR1414 change to 2.37k from 1.24k
PR1408 change to 37.4k from 137k 2017/02/23
PC1545 change to 330uF from 220uF
14 Follow ABO MOS pool Follow ABO MOS pool PQ502 change to AON7506 from SI7716 2017/02/23
PC1503, PC1537, PC1538, PC1539 PC1503, PC1537, PC1538, PC1539 2017/03/07

15 Follow ME and Thermal command change to unpop change to unpop
PC1505 change to pop PC1505 change to pop
16 Design change PC9084 change to unpop PC9084 change to unpop 2017/03/07
PR304 change to 0.01 ohm(SD00000K820) from 0.02 ohm PR304 change to 0.01 ohm(SD00000K820) from 0.02 ohm
17
B B
Design change PC820, PC904 change to SF000007700 from SF000007200 PC820, PC904 change to SF000007700 from SF000007200 2017/03/09
135W: PR211 SD034200280, S RES 1/16W 20K +-1% 0402 135W: PR211 SD034200280, S RES 1/16W 20K +-1% 0402
65W: PR211 SD034453180, S RES 1/16W 4.53K +-1% 0402 65W: PR211 SD034453180, S RES 1/16W 4.53K +-1% 0402
PR213, PR214, PR216, PC204 change to unpop
18 Design change Due to C5V08/D5PR8 no use 2 cell battery, Boost circuit change to unpop, total 19 parts 2017/03/10
boost circuit change to unpop
19 HW command boost circuit change to delete boost circuit change to delete

2017/03/10
20 採 c o mman d PC814, PC815, PC914, PC915 PC814, PC815, PC914, PC915 2017/03/14
change to SE000003H00 from SE00000GC00 change to SE000003H00 from SE00000GC00
PC401,PC419,PC508,PC510,PC1465 PC401,PC419,PC508,PC510,PC1465
21 change from SE080105K80 to SE00000QL10 change from SE080105K80 to SE00000QL10
PVT change: 採 c o mmand PC1428,PC1429 change from SE135105K80 to SE00000OU00 PC1428,PC1429 change from SE135105K80 to SE00000OU00 2017/03/21
PC506,PC507 change from SE093106K80 to SE000005T80 PC506,PC507 change from SE093106K80 to SE000005T80
PC935 change from SE093106M80 to SE000005T80 PC935 change from SE093106M80 to SE000005T80
22 Design change for delay adpi change PR324 from 0ohm to 499ohm for delay adpi change PR324 from 0ohm to 499ohm
A
change PQ201 from LBSS138 to LBSS139 for ESD proctct change PQ201 from LBSS138 to LBSS139 for ESD proctct A
23 Design change change PR515, PR1452, PR1453, PR815, PR915, PR1410, change PR515, PR1452, PR1453, PR815, PR915, PR1410,
PR1431, PR1424, PR1428 to R-short PR1431, PR1424, PR1428 to R-short
PWR_PIR1
Custom 1.0
5 4 3 2 1

Compal La-E903p R1.a (Diagramas - Com.br)

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Compal La-E903p R1.a (Diagramas - Com.br)

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A B C D E

AMD Bristol Ridge/Stoney Ridge Platform

APU 15W/35W + Radeon R17M-P1-50/70/G1-70 25W/40W/50W

Security Classification Compal Secret Data Compal Electronics, Inc.

(Channel A) page 13 (Channel B) *SR only Ch B page 14

page 15~23 Port 0 Port 1 Port 2 Port 3

3.0 Conn. 3.0 Conn.

page 10 Int. DMIC Int. Speaker UAJ

Power On/Off CKT.

Power Circuit DC/DC

page 38~51 Sub Board

Issued Date 2017/04/18 Deciphered Date 2019/04/18 Title

LS-E892 Hall Sensor/B BLOCK DIAGRAMS

PJP201 200mA +3VS

Security Classification Compal Secret Data Compal Electronics, Inc.

Bristol/Stoney Platform Power Sequence

AC-IN G3 --> S0 S0 --> S3 S3 --> S0

+5VALW 3.348ms, Tr = 637us +5VALW

+5VS 770us, Tr = 616us Tf = 13.95ms 733us, Tr = 575us Tf = 14.83ms +5VS

APU_RST# 6.709ms 13.51ns 6.708ms 36.63ns APU_RST#

VGA Sequence VGA Sequence

Security Classification Compal Secret Data Compal Electronics, Inc.

Voltage Rails BOARD ID Table Board ID / SKU ID Table for AD channel

+2.5V 2.5V power rail for APU and DDR ON ON OFF

+0.775VALW 0.775V always on power rail ON ON OFF

+5VALW 5V always on power rail ON ON AC:ON

I2C Port 0 T1@ Bristol Pop EC_ON

GS@ G-Sensor Circuits 3V_EN

2D@ For 2 SO-DIMM use +1.8VALW/+0.95VALW

TI@ SATA Redriver TI solution +APU_CORE_FCH

U10 P_GPP_RXP[0] P_GPP_TXP[0] R1 PCIE_ATX_DRX_P0 C19 1 2 .1U_0402_16V7K

P10 P_GFX_RXP[0] P_GFX_TXP[0] M2

FP4 REV 0.93

CPU PN Table CPU PN Table

UAPU1 BR_A10@ UAPU1 BR_A10R3@ UAPU1 BR_35W A10@

B UAPU1 BR_A12@ UAPU1 BR_A12R3@ UAPU1 BR_35W A12@ B

UAPU1 BR_FX@ UAPU1 BR_FXR3@ UAPU1 BR_35W FX@

UAPU1 SR_A6@ UAPU1 SR_A6R3@

G22 DDRA_SDQ16 E30 DDRB_SDQ16

FP4 REV 0.93 FP4 REV 0.93

Security Classification Compal Secret Data Compal Electronics, Inc.

R672 33_0402_5% APU_TEST18 4 5

EC_SMB_CK2 3 4 APU_SIC 17 18 1K_0804_8P4R_5%

1 2 EC_SMB_CK2 DMN63D8LDW _SOT363-6

1 2 EC_SMB_DA2 EC_SMB_DA2 6 1 APU_SID 0.01U_0402_16V7K

R3970 2.2K_0402_5% Q79B SAMTE_ASP-136446-07-B

www.vinafix.com Security Classification

C912 1 2 150P_0402_50V8J Length<1.0"

HDA_BITCLK AU6 BA17 APU_SPKR

BLINK/USB_OC7_L/AGPIO11 AN5 AGPIO11

R3927 1 2 10K_0402_5% EC_SCI# FP4 REV 0.93

R685 1 @ 2 10K_0402_5% APU_I2C3_SCL FP4_BGA968

R3975 1 @ 2 10K_0402_5% SSD_CLKREQ# 8 1

R3850 1 2 10K_0402_5% PEG_CLKREQ# SYS_RST#

R3879 1 @ 2 0_0402_5% HVB R346 AGPIO11

2 @ 1 CLKRUN# CLK_PEG_VGA U4 GFX_CLKP USB_HSD7P AK2 USB20_P7

FP4 REV 0.93

8MB SPI ROM FP4_BGA968

Security Classification Compal Secret Data Compal Electronics, Inc.

R119 +0.95VS_GFX AE6 VDDP_GFX_2 VDDCR_CPU_28 AE18

+3VALW AP15 VDD_33_S5_1

+APU_CORE_FCH AP13 VDDCR_FCH_S5_1 VDDCR_GFX_19 N7

C1007 AR12 N12

Stoney Platform will use 4H on JDIMM2