Journal of Engineering Research xxx (xxxx) xxx

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Journal of Engineering Research

journal homepage: www.journals.elsevier.com/journal-of-engineering-research

A novel design of 9 level cascade multi-level inverter for decoupled double

synchronous reference frame in state delay controller
T. Sengolrajana, , C. Kalaivanib, J. Ashokc, A. Manikandand
⁎

a
Department of Electrical and Electronics Engineering, Kongunadu College of Engineering and Technology, Thottiam, Tiruchirappalli 621215, India
b
Department of Electrical and Electronics Engineering, A.K.T Memorial College of Engineering and Technology, Kallakurichi (Dt), Tamilnadu - 606 213, India
c
Department of Electronics and Communication Engineering, V. S. B. Engineering College, Karur 639111, India
d
Department of Electronics and Communication Engineering, SSM Institute of Engineering and Technology, Dindugal 624002, India

A R T I C L E I N F O A B S T R A C T

Keywords: In this study, we investigate the performance and scheme of a Decoupled Dual Synchronous Reference Frame
Cascaded multi-level inverter (DDSRF) system, which is investigated for compensation power generation via Shunt Active Filter (SAF)).
Decoupled double synchronous reference frame Traditional direct power control theory and harmonic cancellation responsibilities are unreliable for unbalanced
Harmonic sources and loads. 9-level cascade multi-level inverter (NLC-MLI) ensures the establishment to generate suffi­
Instantaneous PQ theory
cient compensation power. In this paper, instantaneous active power and reactive power (PQ) are represented by
Positive negative and zero sequence
positive, negative, zero sequence and harmonic components. This is to counteract the unbalanced operation of
Shunt Active Filter
State delay controller the load, i.e. twice the frequency at which each reference signal is generated. Due to the delay properties of the
signal generation control loop, the compensation time can deviate from the reference signal measurement point.
A state delay controller (SDC) is proposed to reduce the intermediate delay between the inserted compensation
power and the acquired reference signal. The efficiency of the proposed mathematical analysis method is per­
formed using MATLAB/Simulink and verified by an experimental setup running under unbalanced conditions.

Introduction
Recently, the power quality problems are more attentiveness be­
cause of its more exploitation of power electronics equipments in in­
dustries and domestic products. These devices exhibits non-linear
characteristics because of the non-linear loads which bring the har­
monics and disturbance in the voltage and current in power electronic
system network. It is the source of various problems like low power
factor issue, real and reactive power problems, EMI, low profitable,
heating of components, increases the power losses which can cause
problem in the working. To minimize the power quality problems in the
power electronic system, out of numerous solutions the filtering tech­
nique are mostly used now a days [1–3]. Filters are divided into two
based on the components used for filtering. Namely, Active and Passive
filters. Active filter is confidential as series and Shunt active filters.
Capacitor and inductor are attached in lateral but in sequence with
the load in sequence filter. It allows maximum impedance of harmonics
and frequency of 50 Hz to pass through it to reach the power supply.
However, this type of filter has the disadvantage of passing full load
current. A shunt active filter has capacitors and inductors in series, but
configured in parallel with the load. Shunt filter has low prize as they
don’t carry complete output current on it. Passive filters are big in size
and high capital to maximum power rating.
In addition to that, it is essential for precise fine tuning to attain the
target due to resonance effect in wider control of frequency spectrum.
Shunt Active Filters (SAFs) regulates the power system harmonics by
inserting the wanted equipment and superior solution to retain ba­
lanced voltage and current profile are given by many studies and in­
dustries [4–7]. Normally, the reference signal is playing significant role
in extraction of harmonics from the unbalanced product of power ele­
ment of the irregular load. The targeted output is achieved by available
switching pulses by despotic the DC link voltage which is given to in­
verter system. Traditionally, the instant active and reactive power
control theory was developed under balanced operating condition.
In an unbalanced condition of load or source and harmonics content
are unsolved to remove the weakness in the area of an efficient func­
tioning state [8]. The synchronous reference frame (SRF) theory is
mostly implemented in balanced three phase power systems because of
its fast extraction of the distorted power content and harmonics. SRF
theory was widely applied for single phase circuit due to the reliability

⁎
Corresponding author.
E-mail address: sengolrajan@kongunadu.ac.in (T. Sengolrajan).

https://doi.org/10.1016/j.jer.2023.100106
Received 9 January 2023; Received in revised form 1 May 2023; Accepted 1 June 2023
2307-1877/© 2023 The Authors. Published by Elsevier B.V. on behalf of Kuwait University. This is an open access article under the CC BY-NC-ND license (http://
creativecommons.org/licenses/by-nc-nd/4.0/).

Please cite this article as: T. Sengolrajan, C. Kalaivani, J. Ashok et al., A novel design of 9 level cascade multi-level inverter for decoupled double
synchronous reference frame in state delay controller, Journal of Engineering Research, https://doi.org/10.1016/j.jer.2023.100106i
T. Sengolrajan, C. Kalaivani, J. Ashok et al.
Fig. 1. Advanced SDC with DDSRF-PQ for NLC-MLI SAF.
Fig. 2. State delay controllers.
Fig. 3. New state calculation signal diagram.
of phase locked loop (PLL) performance was unsatisfactory under un­
balanced and severely distorted conditions [9–14]. A double decoupled
synchronous reference frame (DDSRF) theory was introduced to over­
come the drawbacks and detect the positive, negative and harmonics
rotating reference components in unbalanced conditions. The figure of
merit of DDSRF is accurate estimation of all the sequences of compo­
nents without reduction of bandwidth. Signals likes dq1 and dq2 are
generated by the rotating double synchronous reference frame and αβ
is translated into β equal to zero.
Journal of Engineering Research xxx (xxxx) xxx
In this method compensation of reactive power was unsatisfactory
operation and there were complication in control due to highly com­
putation [15-17]. In this paper, the instantaneous PQ theory and har­
monics loss under the unbalanced condition is proposed to meet the
requirement of non-linear load. This paper has also proposed a de­
coupled double synchronous reference frame (DDSRF) theory, which
can find the P,N,Z sequence elements of load and sources in which the
power is consumed and find out the harmonics losses by inserting the
needed power to the grid under unbalanced load to generate the re­
ference signal. To warrant precise compensation from unbalanced
source and load distortion, the discrete PID controller is adopted to give
assessment of decoupling block. The 9 level cascaded MLI (NLC-MLI) is
given by gate signal circuit with feedback that is controlled by capacitor
DC link of inverter [25,26]. discusses the DTC based new switching
method for MLI fed wind systems.Intelligent control algorithms using
adaptive neuro fuzzy system and machine learning are utilized for MLI
switching with self-balancing ability [27–30].
Field-programmable gate array (FPGA) technology maintains to
obtain momentum, and its market around the world is expected to
reach to $3.5 billion USD by 2013. At the highest level, FPGAs are
reprogrammable silicon chips.
Six sections have been organized in this paper. Section II: Elaborates
the detailed analysis of PQ theory of three phase system under balanced
and unbalanced condition. Section III: Design procedure and perfor­
mance analysis of the proposed decoupled double synchronous re­
ference frame with effective controller. Section IV: The proposed
T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 4. Level MLI power circuit.

Fig. 5. Simulation of 9 level MLI with R load.

T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Table 1 From Fig. 1. the power equaling equation is given by instantaneous

Experimental setup parameters. PQ theorem
Descriptions Values Ss120 = Sl120 + Sf 120 (5)
RMS value of Unbalanced AC Source voltage (v) 70 P,N,Z sequence component are expressed as the values 1,2,and 0.
Supply frequency(Hz) 50
Total power taken by non-equal load is Sl120 and total power inserted
Power line inductance(mH) 2500
DC capacitance 2400 µf/600 V under input and output are disconnected character by SAF is Sf 120.The
Switching frequency (kHz) 18 reference current extraction in SRF is playing vital role. Both the place
DC-link voltage(volt) 300 of input and output establish the range of unbalanced power effectively.
Filter coupling inductance 2.5 mH/10 A The power grid inserted by the needed SAF is established by
Filter coupling resistance (Ω) 0.001
Sl120 = Ss120 + Sh120 = ps120 + qs120 + ph120 + qh120 (6)

where, active output- ps120 and reactive output-qs120 are the real and
reactive of load taken from input. Real and reactive power loss is ex­
pressed as ph120 andqh120 by the input harmonics element.

Fundamental transform theory

Fig. 1 shows the advanced system of five level cascaded MLI system
with state lag control technique DDSRF based instantaneous PQ theory.
The advanced DDSRF is established according to clark’s transformation
theory in the unsymmetrical 3 ⱷ power (abc into αβ0) can be expressed
as
1 1
1 2 2
2 33 33
V 0 = 0 Vs
3 2 2
1 1 1
2 2 2 (7)

1 1
Fig. 6. 3 Phase “abc” waveform before voltage compensation. 1 2 2
2 23 23
I 0 = 0 Is
3 2 2
1 1 1
theoretical solution is verified in simulation and validated in experi­ 2 2 2 (8)
mental setup. Section V: detailed analysis of FPGA adaptability for MLI
Implementation. The αβ - instantaneous voltage vector,is taken by cutting the zero
sequence component of voltage vector in αβ0 by having the positive
Re-examine of instantaneous power theory and unbalanced in sequence reference.
source and load 1 1
2 1 2 2
V = Vs
Basic unequal source and power 3 0 3 3
2 2 (9)

In 3 unequal supply system, which is represented as a zero, po­ 1 1

sitive and negative sequences of components are 2 1 2 2
I = Is
3 0 3 3
y (wt + 1) y (wt + 2) 2 2 (10)
Vas y (wt + 0)
Vbs = V0 y (wt + 0 ) + V1
y wt ( 2
3
+ 1 ) + V2 (
y wt +
2
3
+ 2 ) From Eq. (4), stationary reference of determined as follows instant
Vcs y (wt + 0 ) y (wt +
2
+ 1) y (wt
2
+ 2)
power, the real and imaginative power (p q) is,
3 3

(1) p v v i
q = v v i (11)
Where, y = cos, V0, V1 and V2 is the highest value of unbalanced
component which is simplified as,
The changed P and N sequence element obtained by voltage in αβ
Vas Va0 Va1 Va2 reference shape is expressed from
Vs = Vbs = Vb0 + Vb1 + Vb2
cos(wt + 1) cos( wt + 2)
Vcs Vc 0 Vc1 Vc 2 (2) V = V1 + V2
sin(wt + 1) sin( wt + 2) (12)
The unsymmetrical load current element is expressed as
Ias Ia0 Ia1 Ia2
DDSRF power theory and delay controlling
Is = Ibs = Ib0 + Ib1 + Ib2
Ics Ic 0 Ic1 Ic 2 (3)
Decoupled double synchronous reference frame theory in PQ calculation
The apparent power of load is
The frequency of voltage vector in static reference shape is equal to
Ss = Ps + jQs = Vs Is* (4)
the angular frequency of rotating coordinate system. By dividing the P
Where, Ss – Apparent power of load, Ps Real power of load, and and N sequence component from the park‟s transformation the state of
Qs Reactive power of load. DDSRSF is formed. The changed dq12 is expressed by
T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 7. Input current graph before compensa­

tion and current through , “a”, “b”, “c”.

cos(wt ) sin(wt ) iq 2
Vdq1 = V
sin(wt ) cos(wt ) (13) P1 =
3
[vd1 vq1 vd2 vq2]
i d2
2 iq1
cos(wt ) sin(wt ) id1 (18)
Vdq2 = V
sin(wt ) cos(wt ) (14)
i d2
cos 1 cos( 2) sin( 2) cos(2wt ) 3 iq2
Vdq1 = V1 + V2 Q1 = P2 = [vd1 vq1 vd2 vq2]
sin 1 sin( 2 ) cos( 2) sin(2wt ) (15) 2 id1
iq1 (19)
cos 1 cos(2wt ) sin(2wt )
Vdq1 = V1 + Vd2 + Vq2
sin 1 sin(2wt ) cos(2wt ) (16) iq2
3 i d2
Q2 = [vd1 vq1 vq2 vd2]
cos 1 cos(2wt ) sin(2wt ) 2 id1
Vdq2 = V2 Vd1 + Vq1 iq1
sin 1 sin(2wt ) cos(2wt ) (17) (20)

The Eqs. (13)–(17) states the P and N sequence from the park‟s By decoupling the voltage and current the reference signal gener­
theory. And replacing the voltage and current value that are decoupled ated is expressed by
in the instantaneous PQ theory equation
T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 8. Three phase output current with SAF phase compensation.

iq2 Fig. 3 By comparing the reference (k-1)* lag, current state sample
3 i d2 (k), reference (k)* delay and by taking the mean of pre-state sample (k-
P0 = [vd1 vq1 vd2 vq2]
2 iq1 1) the mistake or lag time of present state (k + 1) is found out. To cut
id1 (21) the signal lag mistake of reference to SAF output the positive and ne­
gative sequence of voltage and current is calculated. DDSRF with delay
i d2 compensation is validated by experimental setup.
3 iq 2
Q0 = [vd1 vq1 vd2 vq2]
2 id1 Level multi level inverter
iq1 (22)
The proposed 9-level voltage source inverter consists of three bi­
The q axis positive sequence component contains oscillations in the directional switches S1-S6 and two diodes Da1-Da2 added to the ex­
signal. When compared to the traditional SRF-PLL to the DDSRF the isting three-phase two-level bridge Q1-Q6, as shown in Fig. 4. The effect
main advantage is it don’t want to lower the bandwidth of PLL to cut of this bidirectional switch is to cut off the higher voltage and facilitate
the maximum order oscillations [18–22]. The Low Pass Filter (LPF) the current to reach the midpoint (o). It provides a fixed voltage of 4Vdc
established to repress the maximum disturbance in signal. from VSI, the voltage Vdc is not equal to the two cascade bridges, and
2Vdc is connected to the (+,-, o) terminals. Therefore, the proposed VSI
State delay controller generates nine identical voltage levels and different voltage levels, and
the cascaded H-bridge power supply circuit uses two series cells that do
Due to unbalance condition of operation there is ⱷ lag in the LPF not have the same voltage supply. Two switches are opened and closed
load while generating the signal. Finally, there is a delay in entire in each cell to output two voltage levels.
system for the calculated timing value to compensation PQ power from Corresponding voltages Vdc, 2Vdc, 3Vdc, 4Vdc. 0 –Vdc, −2Vdc,
the SAF. To eliminate the phase lag error the fine tuning is needed in when switch T1 is on and Vmg = Vdc, the first cell DC voltage supply
the full circuit [20–24]. Vdc is added. Where Vmg is the voltage (m) at the node, If the inverter
From the present state of PQ observation the state lag controller is is grounded (g) or switch T2 is open, it is bypassed and Vmg = 0.
defined before the state. Fig. 2 shows that the state delay controller Similarly, when switch T3 is on, the second battery DC supply 2Vdc is
operating and Eq. (20) state the delay calculation procedure in the in­ added, Vom = + 2Vdc. Here, Vom is bypassed when the voltage from
dividual blocks in diagram. The pre-state, current state, and signal time midpoint (o) to node (m) or switch T4 is turned on Vom = 0.
is shown as (k-1), (k) and (k + 1) state. The below equation is used to Traditional 2-level bridge (Q1 to Q6) switches are rated at 4Vdc peak,
estimate. while bidirectional switches (S1 to S6) are rated at 3Vdc peak. The peak
Pre-state: x (k 1) = x (k 1)* x (k 1) current state: voltage rating of the second cell switches (T3 and T4) in the CHB cell is
x (k ) = x (k )* x (k ) . 2Vdc, while the peak voltage rating of T1 and T2 in the first cell is Vdc.
Next state: x (k + 1) =
x (k 1) + x (k )
2
where, x = Vdq12, Idq12 de­ Corresponding voltage Vdc, 2Vdc, 3Vdc, 4Vdc.0 -Vdc, − 2Vdc, − 3Vdc,
coupled voltage and current. − 4Vdc and total Vab, Vbc, Vca as shown in Fig. 5.
T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 9. Performance of SAF in phase “a” with unbalanced load compensational).output voltage b).output current c). Inserted current from SAF and d). NLC-MLI load
voltage.

Fig. 10. Current waveform and harmonics before compensation.

T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 11. NLC-MLI based SAF compensation

under transient operation of 3 load at
t = 0.04 s a). input voltage b). input current c).
inserted current from SAF and d). NLC-MLI
load voltage.

Fig. 13. The output voltage of the nine levels inverter for RL load.

Fig. 12. After compensation of output current with THD spectrum.

T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 14. Three-phase voltage waveform without compensation.

Fig. 15. Voltage THD without SAF.

Fig. 16. Voltage THD with SAF.

T. Sengolrajan, C. Kalaivani, J. Ashok et al.
Fig. 17. Amplitudes of the weighted harmonics with respect to the fundamental.
Fig. 18. Hardware model of 9 Level Converter.
Results and discussions
Simulation results
The proposed DDSRF with delay time cancel out method was si­
mulated by using MATLAB/ Simulink in order to improve the simula­
tion speed, because of source and load is operated as unequal state are
tabulated in Table 1. The control scheme of simulated model conditions
was employed to validate by experimentally is shown the following
graphs. The unbalanced voltage and current across the input of source
is simulated and results shown in Figs. 6–17.
From Figs. 6 to 9 shows the effective ruling process to correct the
nonlinear character of input and output. To evaluate SAF proposed
algorithm the performance was built-up by using Nine level cascaded
multilevel inverter (NLC-MLI) structure.The appropriate gate signal is
generated for the three phase inverter by using DDSRF.
The unbalanced load is consisting of three phase diode rectifier
circuit and it provides the resistance and inductance circuit and THD is
26.40 % without SAF as shown in Fig. 10. The Figs. 10–14 shows the
quality of input and output current with voltage based equipment are
improved to THD 1.62 % by using the DDSRF with time lag controller
method. And the Figs. 6–14, shows the simulated diagram of NLC-MLI
Journal of Engineering Research xxx (xxxx) xxx
structure based SAF performances connected with unbalanced load
with and without SAF compensation.
The voltage waveforms and %THD are compared with and without
SAF and the simulated results are illustrated in Figs. 13–17. Fig. 17
shows the amplitude of.
Hardware model
An experimental setup of the shunt active filter for a multi-level
inverter is shown in Fig. 18. The three phase source voltages and dc-link
voltages are sensed by a Hall effect voltage sensor (LV25-P), and the
three phase source current, load current and filter current are sensed by
a Hall effect current sensor (LA25-P), along with three iron core in­
ductors (5 mh/15 A) that are used as filters. The switching signals for
the Insulated-Gate Bipolar Transistors (IGBTFGA40N120) are derived
from the SRF theory. A driver circuit (TLP250IC) is used to drive the
Pulse Width Modulation (PWM) pulses to the inverter. For the isolation
of the inverter output voltage from the power circuit of the SAF, six
toroidal core transformers are used in the hardware setup. The SRF
algorithm has been implemented using a Spartan 6 Field-Programmable
Gate Array (FPGA) processor. FPGA technology is suitable for a wider
range of applications. The Spartan 6 FPGA controller generates and
controls the PWM pulses for the inverte. The FPGA architecture is de­
signed on the basis of the control algorithm. The output results are
displayed on a CRO/Power quality analyzer to view the voltage and
current waveforms.
FPGA hardware structure is explained by the user as it is not fixed.
As it has logic cells fixed in it the inter connections and performance are
detected by the user. The process of FPGA cannot be defined before.
Ability of parallel processing of FPGA is the advantage that it has se­
parate process than other processor so it is used in most of the areas
[25]. In certain areas for the circuit the control purpose processors are
used. By using the XC3S500E device in the MLI the PWM generation are
performed. For the sequential plan of circuit a 50 MHz on board clock
oscillator is worn. Here, for the betterment of carrier and reference
waves. 40 % of look up tables, 25 % DSP based 18 × 18 multipliers are
worn. For the usage of power Xilinx power estimator tool is worn. Static
and dynamic power extracted in the MLI is, 78 mW and 52 mW. FPGA
extract 120 mW power. This power is used in the commercial purpose,
Vccint voltage is 1.2 V and the ambient temperature is 450 C.
Figs. 19–24 shows the three phase output current compensated
power under unbalanced condition of load voltage, and SAF output
T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 19. Current of “abc” and unbalanced voltage of

three phase.

Fig. 20. abc current with 3 .

T. Sengolrajan, C. Kalaivani, J. Ashok et al.
current at PCC with THD spectrum. The Figs. 14–16 shows the total
harmonic distortion of phase “a” with unbalanced three phase input
power profile with current harmonics. The phase and line magnitude of
unequal load RMS voltage and current are taken and it is explained in
Fig. 18. The load current THD is minimum of 24.785 % in phase “c” and
maximum value is 26.143 % in phase “a” without injection compen­
sation current in PCC or by not having the connection of SAF.
The unbalanced load voltage, current, injected current at PCC from
SAF and the NLC-MLI output voltage ahead of filter coupling
Journal of Engineering Research xxx (xxxx) xxx
Fig. 21. , “abc” and harmonics spectrum
phase “a” of source current with three phase.
Fig. 22. Three phase load current phase a, b, c
and output current harmonious spectrum of ,
“a” with SAF compensation.
inductance. The real (P) and reactive (Q) power values are 920.67 W
and 47.1Var. By this process the working load which consumes power is
improved with the time lag of dq1 and dq2 component having P and N
sequence PQ by the algorithm based on DDSRF. The SAF cancel out
the harmonics component from waveform Figs. 22–23 performance
analysis.
The unbalanced load high value of P and Q component is 410.22 W
and 127.43 V. At the normal condition, the least value of P and Q
component is 389.23 W and 119.66 V. More reactive power is taken due
T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 23. Output voltage, current, inserted current from SAF, load voltage THD, “b” phase current THD and injected current THD.

Fig. 24. Source voltage and current, injected current and voltage from output of (NLC-MLI) SAF.

Fig. 25. Phase measurements operating at 25 ms transient condition with load at three phases L-L.

to the unbalanced current graph. By using SAF as a configuration of five
levels cascaded multilevel inverter (NLC-MLI) the harmonics is mini­
mized in the disturbed source and load by inserting the compensation
power to the point of PCC.
From the observation of load current, the distortion of unbalanced
load current and voltage is reduced drastically as shown in Fig. 21.
The Figs. 23–24 shows NLC-MLI configuration based SAF compen­
sated load current waveform.
The objective of unbalanced load harmonics in phase “c” are re­
duced as minimum value of 1.425 %, that is minimum than IEEE
standards recommended value. Figs. 25–26 are show that the THD
profile unbalanced three phase load. SAF is also experimented in
T. Sengolrajan, C. Kalaivani, J. Ashok et al. Journal of Engineering Research xxx (xxxx) xxx

Fig. 26. Three phase load phase voltage, current and C phase current THD measurements with compensation (with SAF).

Fig. 27. Output Voltage and current, NLC-MLI based SAF compensation current and voltage under transient generating at 84 ms.

Fig. 28. NLC-MLI based SAF compensation with three phase load current and voltage under transient operating state at 25 ms.

transient operating condition to quicken bring back the unbalanced
load operation into balanced state. SAF is checked in two transient
operation at t = 25 ms and 84 ms as shown in Figs. 27–28.
The SAF connected at 25 ms and t = 84 ms, to compensate the
power required at the point PCC. The oscillation in the current
waveform is canceled out very quickly at both transient operated con­
ditions as explained in Fig. 28. THD in input current and voltage is
maximum of 3.09 % and 2.11 % at t = 84 ms respectively. The reactive
power consumption by unbalanced load and oscillations drastically
reduced as compared with unbalanced state operation.
T. Sengolrajan, C. Kalaivani, J. Ashok et al.
Conclusion
In this Study, the simulation model of NLC- MLI is developed. The
DDSRF mathematical model is designed to compensate power via SAF.
The suggested state delay controller (SDC) reduces the intermediate
delay between the inserted compensation power and the acquired re­
ference signal. By having the state delay controller of DDSRF with
unbalanced condition using PQ theory was investigated and verified.
NLC-MLI in transient operation based SAF is tested in the various
conditions and it is found that it has fast frequency response and is more
reliable in the normal operating state. In this advanced technique %
THD of the voltage and current obtained is of 2.823 and 2.065, which is
lesser than the IEEE standard value. The performance parameters vol­
tage, current and %THD are compared. The simulation results are va­
lidated using the hardware prototype. The closed loop control algo­
rithm in digital platform using FPGA control is developed and
presented. The simulation and experimental results with and without
compensation via SAF is presented. However, the feedback lineariza­
tion with state delay controller circuit is not much substantially reliable
and it is to be overcome in future work. Advantage of using FPGA is, it
takes minimum space and obtain low propagation lag with very less
power output.
Data Availability
Data sharing is not applicable to this article as no new data were
created or analyzed in this study.
Declaration of Competing Interest
The authors declare that they have no known competing financial
interests or personal relationships that could have appeared to influ­
ence the work reported in this paper.
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