INTERVIEW PREPSRATION BY ABHAY KUMAR @VLSIGURU, Physical Design - Placement

1. TARGETs:
1. Meeting timing (WNS {worst negative slack}, TNS{total negative slack}, FEP{failing
end points) mainly for REG2REG)
2. Congestion in limit (0.5% H, V; lower tech hotspot : Total < 10000, max < 200)
3. Cell density
4. Pin density
2. INPUTS
o FP completed design
o SDC, MMMC
o Design targets (max_trans, max_area)
3. RESULTs
o Legalized cell placement
o CONG
o density
4. CONSTRAINTS
o Placement blockage ( partial, soft, hard)
o Bounds (guide, region, fence)
o Magnet placement
o Relative placement
o Keepout_margin/ padding
5. CHECKS
o Legality of cell placement
o Timing
 Module placement
 Path by path
o Cong
 Congestion = (required tracks/available tracks)
 Required tracks : reduce cell density, pin density, cris-cross in cell signal
routing because of wrong cells placement for the path
 Cell density: soft , partial , hard. Guide, region, fence, keep_out_margin
o Density
 PIN DENSITY
 CELL DENSITY
 COND1: pin density is high and cell density is okay
 Keep_out_margin
 COND2: pin density is okay and cell density is high
 Soft, partial, hard
 COND3: pin and cell density both are high
6. Keep_out_margin, blockages
7. Design starting utilization and cong analysis
o Starting util depends on type of architecture
 Cell dominating , this will have more cell density
 Net dominating, this will have lesser cell density
o Cong = (Req/Avilable)
 REQ:
 Keeping placement constraints (BLK, Keepout)
 De-tour nets crossing the critical area by adding buffer
 Available :

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INTERVIEW PREPSRATION BY ABHAY KUMAR @VLSIGURU, Physical Design - Placement

 Spacing given between macros OR std cells area

 Type of power structure
o Thick power stripe
o Power stripes are not align to track
o Clock NDR
8. Placement Output:
o Timing
o Congestion
o Design density
o Area
o power
9. Commands:
o Visual check on the database
o check_legality -verbose > chk_lega.rpt
o report_qor > ./report_qor.rpt
o report_timing –from [all_registers –clock_pin] –to [all_registers –data_pin] –net –trans –
cap –nosplit –nworst 1 –max_path 1
10. What is need of early clock (estimation of clock in placement) flow in PD in lower technology?
o Early estimation of routing cong and skew
o It also reserve space for clock cells in CTS stage.
11. What is banking and de-banking in synth and how this will help in saving power?
o Banking : combining the REGs into one STD cell
o DE-banking : separating the registers from bank
o It is also called flop trays.
12. What are the power strap vios in design?
o How the power strap area treated for STD cells placement.
o ICC Tool has command called set_pnet_options
o This is very serious for CTS cells because it leads to CTS cells routing change.
o This command avoid shorts b/w cell internal blockage and power stripe
13. What is critical range in placement and explain with graph, how this help in fixing setup timing.
14. Why is incremental optimization help in vios fixing?
o Incr opt: is basically re-optimizing the optimized design
o By running this, tool will again seeing the top paths as per new histogram.
15. What is need of critical range?
o It save time of optimization
o As combinational logic is common to multiple paths, so tool need not to work on all
paths
16. Difference between Hier and flat?
o Flat designs are preferred because of easy for optimization
o Instance name is same in both the case (A/B/C/D)
o During flattening the design tool add hier as prefix to instance name
o In flat design, difficult to divide the design for multi-cpu, multi-thread
o In flat design, difficult to apply constraints for each module.
o Flat design are better for power , area, and timing.
o Flat design cannot be bigger in size
o SoC level also division of blocks happened base on their hierarchies
o Other checks like DFT, GLS also be having treble in identifying the constraints.
o Once design is flatten, it cannot be reverted back to original.

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INTERVIEW PREPSRATION BY ABHAY KUMAR @VLSIGURU, Physical Design - Placement

17. Why is DECAP called local supply source?

o They gets charge in normal cycle and supply the power in voltage drop condition
18.