2 - Introduction To Altera DE2-115-2022

1
ALTERA Basic Design Flow:

Introduction to FPGA
Altera DE2-115 Board and
Quartus II Design SW
CEG 2136 Computer Architecture I
Outline
2
 Introduction to Altera FPGA

 Fundamentals of Quartus II 13.0
 Detailed example of using Altera FPGA
HW/SW platform
 Lab admin specs
Altera FPGA DE2-115 3
A Field Programmable Gate Array (FPGA) is a Programmable Logic

Device (PLD) with higher densities and capable of implementing
different logic functions in a short period of time.
Altera Basic Design Flow: Logic Circuit Design

4
1. Schematics 4. Verification
Capture 3. Simulation
2. Compilation
VHDL Model UP-1 Development Board

Altera DE2-115
Development and Education Board
5
Introduction to Quartus II 13.0
 Quartus Version 13.0 web edition can be

downloaded from the Internet:
 https://www.intel.com/content/www/us/en/software-kit/711791/intel-
quartus-ii-web-edition-design-software-version-13-0sp1-for-windows.html
DO NOT try to download different versions.
 Other versions might not be compatible with the
University version.
 Install Quartus Version 13.0 web edition on your
personal computer as explained in Intro to Altera Lab
Platform
Design, simulate, implement and practically 6
verify a combinational logic circuit that

realizes the following logic function:
A B A B’ B A’ F
0 0 0 0 0
0 1 0 1 1 F = A B’ + B A’
1 0 1 0 1
1 1 0 0 0
•
•
A. Starting a
7
New Project
Create your project in an accessible location. Never create it in the original

software installation directory in C:\ drive !
At the end of the lab sessions make sure you save the project files on your
computer at home or another safe place, as the lab computers are reset!
Cyclone IV E
EP4CE115F29C7
New Project 8
Altera Quartus II 13.0
In the lab you can Start

QUARTUS II 13.0 sp1 (64-bit)
software under
Start  All Programs 
Software Development.
New Project Altera Quartus II 13.0 9


To create a new project,

go to the File menu and
select
‘New Project Wizard’.
New Project Altera Quartus II 13.0

12
New Project Altera Quartus II 13.0

13
Select or create another directory where you have

permissions to write to all files or create new files!
The top-level design entity must have the same name with the design file!
‘New Project Wizard’ dialog box asks for the name and
directory of the project. Set the working directory to be
… and choose (say) Test01 as the name for both the
project and the top-level entity (confirm creating the
new directory)
New Project
14
When the “Add Files” window pops

up just click Next, since there are
no previous files to be included in
the project.
New Project
15
In the “Family &

Device Settings”
select Cyclone IV E as
the device family
New Project
16
From the list of available devices, choose the

device called EP4CE115F29C7 which is used on
Altera’s DE2-115 board and press Next.
New Project
17
Since in this lab we will rely solely

on Quartus II tools, we will not
choose any other tools and we will
press Next, stepping to the final
window (Summary).
New Project
18
Press Finish to conclude and

return to the main Quartus
window
New Project
19
Altera Basic Design Flow: Quartus II 13.0 20
Step 1: Design Capturing
1. Schematics
1. Schematics
Capture
2. Compilation 3. Simulation 4. Verification
Capture The Quartus II
Graphic Editor is
used to capture the
schematic (logic
diagram) of a
previously designed
logic circuit.
VHDL Model
21
B. Design Using the Graphic Editor
Altera Quartus II 13.0 22
Step 1: Design
Capturing
Select File > New

Step 1: Design
Capturing
In the newly opened window

choose Block Diagram /
Schematic File, and click
OK to create a blank
schematic worksheet in the
Graphic Editor window.
Altera Quartus II 13.0 Step 1: Design 24
The first step is to specify a name for the file that will be
created. Select File > Save As.
In the box labelled Save as type choose Block
Diagram/Schematic File (*.bdf).
In the box labelled File name automatically will appear
Test01 or type Test01, to match the name given to the
top-level design entity when the project was created.
Put a checkmark in the box Add file to current project.
Click Save, which puts the file into the directory that you
selected or created as shown in slide 13 and leads to
the Graphic Editor window.
C. Creating the Schematic
Step 1: Design
25
To open the Symbol window

• Double click in the center of the worksheet of the Graphic Editor, or
• Right click in the center of the worksheet and then choose in the pop-up window
InsertSymbol.
In the Symbol window’s library box expand

…/altera/13.0sp1/quartus/libraries and scroll down in the primitives 
logic directory to select and2; the corresponding gate-symbol will appear
in the worksheet of the Symbol window. Click OK to close the Symbol
window and transfer the selected symbol to the center of the lab_1.bdf
worksheet of the Graphic Editor.
To the same effect just double click the gate’s name in the library
directory. Now drag the gate-symbol to the wanted position and fix it there
with a click.
NOTE: To avoid repetitive inserts, uncheck the Repeat-insert mode option in the Symbol window.
Altera Quartus II 13.0 Step 1: Design 26
Shortcut D. Input and Output Symbols

for I / O In the Symbol windows’ Libraries box,
double click on the Primitives  Pin and select and place an
Output symbol on the worksheet of the Graphic Editor.
Repeat these steps to place 4 Input symbols on the worksheet.
Avoid overlapping connections
E. Connecting the Symbols

• Go to the end of a symbol with the mouse and, when the arrow cursor changes to a cross-symbol,
press the left button of the mouse and drag the wire to the point to connect to;
as the cursor reaches the destination, the cursor changes again to a small square, and at that point
you can release the mouse; see diagram below for the connection.
• Repeat the previous step for all connections.
• If a wire is not properly run, just select it (wire turns red) and hit delete to remove it.
• If you have problem running the wire from one point completely to another, try running half way
from both devices.
• The mouse can also be used to move a wire to the desired position.
Step 2: Compilation
1. Schematics 3. Simulation 4. Verification
2. Compilation
Capture

Step 2: Compilation
G. Compiling your Project

• Select Processing  Start compilation or
• click on the toolbar icon ►
• or press Ctrl+L
Step 2: Compilation A similar window should appear

Step 2: Compilation
The project should compile

with 0 errors. If any errors
appear verify if you have
performed the entire steps
correctly. (Ignore the warning
about Timing)
Close the compiler window.
Altera Quartus II 13.0 Pins Assignment 31
 For functional simulation only, you can skip now to Step 3

 For timing simulation, FPGA programming and circuit practical
verification, you have to assign physical pins to your project by
connecting Inputs and Outputs to switches and LEDs,
respectively.
Altera Quartus II 13.0 Pins Assignment 32
F. Editing Pin Names can be done in two ways:

Assignment Editor Pin Planner
Illustrated in following slides Explained in lab manual

Altera Quartus II 13.0 Pins Assignment
 Launch Assignment Editor
33
Select the nodes to being assigned pins
1 click 3 select 4 click 2 click
3 click to transfer all 34


35
click

36
select
Pins Assignment
Type the names of the FPGA pins to which nodes of your circuit need to be connected
38
Pins Assignment
Recompile the project
Step 3: Simulation
2. Compilation
Capture

Step 3: Simulation
Select
File  New University Program VWF
and click OK
Step 3: Simulation pane
Waveform Editor has two sub-windows:

• time diagram with ns displayed on the
right hand, while on
• the left column the terminal signals
will be enlisted.
Step 3: Save the Simulation File
Save the file under the name

1. To populate the list of
terminals, right click in the Altera Quartus II 13.0
column under the Name
header and select Insert Step 3: Simulation
 Insert Node or Bus; 2. In the new window click on Node Finder
3. Select Filter  Pins: all
4. click on List
Functional
Simulation
not
Timing
Simulation
is • Select (highlight) A, B, C, D and X from the left column of
performed Nodes Found and then click on “>” to have all A, B, C, D, and
here Y copied to the right Selected Nodes column.
• The contents of the left column is entirely copied to the right
(without having to select them) by simply hitting “>>”
43
• Click OK to close Node Finder & Insert Node or Bus window.
Altera Quartus II 13.0 Step 3: Simulation

Click on Edit and select Set End Time
Set the desired simulation to run from

0 to 800 ns by selecting
Edit > End Time and entering 800 ns
in the dialog box that pops up.
Adjust end time to cover at least one full set

of input combinations
44
Altera Quartus II Step 3: Simulation 45

Choose Edit > Grid Size …
… and enter a Time Period of 100 ns in the dialog

box that pops up
Step 3: Simulation
Selecting View > Fit in Window

displays the entire simulation range
of 0 to 800 ns in the window.
Altera Quartus II 13.0 Step 3: Simulation 47
To cover all the logic combinations that can be generated by 4 input variables A,B,C,D,
you may want to apply test vectors whose binary equivalents count from 0-15, with
D mapped to the msb of the binary number (weight 23) while A mapped to lsb (20)
1. Click on A to highlight (select) the first row of the time diagram
2. select the clock

from the toolbar
3. Choose:
• a Period of 100 ns and
• a duty cycle of 50%
Step 3: Simulation
Then click
• on B and in Period of 200 ns and a duty cycle of 50%.
• on C and in Period of 400 ns and a duty cycle of 50%.
• on D and in Period of 800 ns and a duty cycle of 50%.
Save the file !
Step 3: Simulation
Under Simulation menu go to Options and select

Quartus II Simulator as the simulator
Step 3: Simulation
Simulation can be triggered

• by clicking
• or by selecting in the Waveform diagram menu
Simulation  Run Functional Simulation
Step 3: Simulation
Simulation can be triggered

by clicking , or…
Step 3: Simulation
… or by selecting in the Waveform diagram menu

Simulation  Run Functional Simulation
Altera Quartus II 13.0 Step 3: Simulation 53
Simulation Input
Simulation Output
Once simulation is done, a new window would appear with the simulation results.
Take a screenshot and save simulation output to include in lab report.

Do not put Simulation input instead!
Step 4: FPGA Programming & Verification

2. Compilation
Capture


Make sure the:
• USB-Blaster cable is attached to the board and to the USB port on
the PC.
• the RUN/PROG switch (SW19; leftmost toggle switch) is set to RUN.
Select Tools  Programmer in the Quartus II window


Might need to
close and open
this window few
times.
From Hardware Settings, in the Currently Selected

Hardware box, select USB-Blaster and click Close.
• In the Programmer window, check that the

…/output_files/Test01.sof file is listed. If it is
not, then click the Add File button on the left
panel and look for the Test01.sof file under the
…/output_files directory in the current working
directory.
• Make sure Program/Configure is checked-in.
• Click Start
After the FPGA is successfully programed,

verify your circuit according to the simulation,
using the DIP switch as input (SW0 is input A,
B is SW1, C is SW2 and D is SW3) and the
LEDR0 as output (Y). Remember that a LED
illuminates when its control input is 1.
NOTE: Once done, you do not need to save
the *.cdf file.
60
… observe the output (Y) on

LEDR0. Remember that on this
board a LED illuminates when its
control input is 1.
To verify your circuit, apply all 16 possible logic combinations to the circuit’s inputs A, B, C, D by
modifying the slide switches (SW0 is input A, B is SW1, C is SW2 and D is SW3)
Altera DE2-115 & Quartus II 13.0

In-lab activity 61
 Students are expected to work on labs in groups of two or three.

 Attendance shall be taken at all Labs.
 Students shall be prepared at the beginning of the lab sessions.
Pre-lab of each section will be taken per-group.
 If a group member is not shown, a ZERO mark will count for that student.
 Pre-lab preparation consists of:
 Prepare and draw the circuits before the lab,
 Prepare all truth tables and expressions before the lab,
 Answering all the related questions before the lab.
 The TAs will answer students’ questions about the labs without
disclosing the solution.
In-lab activity 62
 After completing the design, simulation and verification steps

for each part / circuit, please call a TA to demonstrate your
work. However, you are encouraged to capture and simulate
your logic circuit in advance before joining the lab session.
 Leaving the lab without showing your fully or partially
completed work will result in zero marks for those parts
 Group members must demonstrate correct operation of their
circuits.
 The TA will ask few questions to verify that the experiment was
done by group members with sound theoretical background.
 Failing to explain simulation and experimental results may
result in lesser marks
 Pre-lab and in-lab activity marks are awarded to each group
member based on their answers to questions asked by TAs
Laboratory Report
63
 Take screenshots of schematic designs and simulation

outputs to include into report
 The lab report format will be available in Virtual Campus
 Students shall submit one lab report per group on Virtual
Campus.
 Lab mark =
 Individual in-lab activity (including pre-lab + experiments
demonstration)
+
 Group’s final report.
64
Thank You

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1

ALTERA Basic Design Flow:

 Introduction to Altera FPGA

Altera FPGA DE2-115 3

A Field Programmable Gate Array (FPGA) is a Programmable Logic

Altera Basic Design Flow: Logic Circuit Design

VHDL Model UP-1 Development Board

 Quartus Version 13.0 web edition can be

Design, simulate, implement and practically 6

verify a combinational logic circuit that

Create your project in an accessible location. Never create it in the original

Altera Quartus II 13.0

In the lab you can Start

New Project Altera Quartus II 13.0 9

New Project Altera Quartus II 13.0 10

New Project Altera Quartus II 13.0 11

To create a new project,

New Project Altera Quartus II 13.0

New Project Altera Quartus II 13.0

Select or create another directory where you have

When the “Add Files” window pops

In the “Family &

From the list of available devices, choose the

Since in this lab we will rely solely

Press Finish to conclude and

Altera Quartus II 13.0 22

Select File > New

Altera Quartus II 13.0 23

In the newly opened window

Altera Quartus II 13.0 Step 1: Design 24

To open the Symbol window

In the Symbol window’s library box expand

Altera Quartus II 13.0 Step 1: Design 26

Shortcut D. Input and Output Symbols

Avoid overlapping connections

E. Connecting the Symbols

Altera Basic Design Flow: Quartus II 13.0 27

VHDL Model UP-1 Development Board

Altera Quartus II 13.0 28

G. Compiling your Project

Altera Quartus II 13.0 29

Step 2: Compilation A similar window should appear

Altera Quartus II 13.0 30

The project should compile

Altera Quartus II 13.0 Pins Assignment 31

 For functional simulation only, you can skip now to Step 3

Altera Quartus II 13.0 Pins Assignment 32

F. Editing Pin Names can be done in two ways:

Illustrated in following slides Explained in lab manual

Altera Quartus II 13.0 Pins Assignment

 Launch Assignment Editor

1 click 3 select 4 click 2 click

3 click to transfer all 34

Altera Quartus II 13.0 Pins Assignment

Altera Quartus II 13.0 Pins Assignment

Altera Quartus II 13.0 37

VHDL Model UP-1 Development Board

Altera Quartus II 13.0 40

Altera Quartus II 13.0 41

Step 3: Simulation pane

Waveform Editor has two sub-windows:

Altera Quartus II 13.0 42