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Integrado So8 IRF7309PbF
Integrado So8 IRF7309PbF
1243B
PRELIMINARY IRF7309
HEXFET® Power MOSFET
Generation V Technology
Ultra Low On-Resistance N-CHANNEL MOSFET
1 8 N-Ch P-Ch
S1 D1
Dual N and P Channel Mosfet
2 7
Surface Mount G1 D1
VDSS 30V -30V
Available in Tape & Reel S2
3 6
D2
Dynamic dv/dt Rating 4 5
G2 D2
Fast Switching P-CHANNEL MOSFET RDS(on) 0.050Ω 0.10Ω
Top View
Description
Fifth Generation HEXFETs from International Rectifier utilize advanced processing
techniques to achieve the lowest possible on-resistance per silicon area. This
benefit, combined with the fast switching speed and ruggedized device design for
which HEXFET Power MOSFETs are well known, provides the designer with an
extremely efficient device for use in a wide variety of applications.
The SO-8 has been modified through a customized leadframe for enhanced
thermal characteristics and multiple-die capability making it ideal in a variety of
power applications. With these improvements, multiple devices can be used in an SO-8
application with dramatically reduced board space. The package is designed for
vapor phase, infra-red, or wave soldering techniques. Power dissipation of greater
than 0.8W is possible in a typical PCB mount application.
Repetitive rating; pulse width limited by max. junction temperature. ( See fig. 23 )
N-Channel ISD ≤ 2.4A, di/dt ≤ 73A/µs, VDD ≤ V(BR)DSS, TJ ≤ 150°C
P-Channel ISD ≤ -1.8A, di/dt ≤ 90A/µs, VDD ≤ V(BR)DSS, TJ ≤ 150°C
Pulse width ≤ 300µs; duty cycle ≤ 2%.
148
IRF7309
N-Channel
6.0V 6.0V
5.5V 5.5V
5.0V 5.0V
BOTTOM 4.5V BOTTOM 4.5V
100 100
4.5V 4.5V
10 10
D
D
100 2.0
I D = 4.0A
R DS(on) , Drain-to-Source On Resistance
I D , Drain-to-Source Current (A)
TJ = 25°C 1.5
TJ = 150°C
(Normalized)
1.0
0.5
VDS = 15V
20µs PULSE WIDTH VGS = 10V
10 0.0 A
A
4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160
149
IRF7309
N-Channel
1000 20
V GS = 0V, f = 1MHz I D = 2.4A
C iss = C gs + C gd , Cds SHORTED VDS = 24V
C rss = C gd
Ciss
600 12
Coss
400 8
200 Crss 4
Fig 5. Typical Capacitance Vs. Drain-to- Fig 6. Typical Gate Charge Vs.
Source Voltage Gate-to-Source Voltage
100 100
OPERATION IN THIS AREA LIMITED
BY R DS(on)
ISD , Reverse Drain Current (A)
10 10 100µs
TJ = 150°C 1ms
TJ = 25°C
10ms
1 1
100ms
TA = 25°C
TJ = 150°C
VGS = 0V Single Pulse
0.1 A 0.1 A
0.0 0.5 1.0 1.5 2.0 2.5 0.1 1 10 100
150
IRF7309
N-Channel
4.0
ID, Drain Current (Amps)
3.0
2.0
0.0 A
25 50 75 100 125 150
TA , Ambient Temperature (°C)
Fig 9. Max. Drain Current Vs. Ambient Temp.
Fig 11a. Gate Charge Test Circuit Fig 11b. Basic Gate Charge Waveform
P-Channel
100 100
VGS VGS
TOP - 15V TOP - 15V
- 10V - 10V
- 8.0V - 8.0V
-ID , Drain-to-Source Current (A)
- 7.0V
-I D , Drain-to-Source Current (A)
- 7.0V
- 6.0V - 6.0V
- 5.5V - 5.5V
- 5.0V - 5.0V
BOTTOM - 4.5V BOTTOM - 4.5V
10 -4.5V 10
-4.5V
151
IRF7309
P-Channel
100 2.0
I D = -3.0A
TJ = 25°C
1.5
TJ = 150°C
(Normalized)
10 1.0
0.5
VDS = -15V
20µs PULSE WIDTH VGS = -10V
1 0.0 A
A
4 5 6 7 8 9 10 -60 -40 -20 0 20 40 60 80 100 120 140 160
1000 20
V GS = 0V, f = 1MHz ID = -3.0A
C iss = Cgs + C gd , Cds SHORTED VDS = -24V
-VGS , Gate-to-Source Voltage (V)
C rss = C gd
800 C oss = Cds + C gd 16
C, Capacitance (pF)
600 Ciss 12
Coss
400 8
200 Crss 4
152
IRF7309
P-Channel
100 100
OPERATION IN THIS AREA LIMITED
-ISD , Reverse Drain Current (A)
BY R DS(on)
TJ = 150°C
1ms
TJ = 25°C
1 1 10ms
100ms
TA = 25°C
TJ = 150°C
VGS = 0V Single Pulse
0.1 A 0.1 A
0.0 0.3 0.6 0.9 1.2 1.5 0.1 1 10 100
3.0
-ID, Drain Current (Amps)
2.0
1.0
0.0 A
25 50 75 100 125 150
TA , AmbientTemperature (°C)
153
IRF7309
P-Channel
Fig 22b. Gate Charge Test Circuit Fig 22b. Basic Gate Charge Waveform
N- and P-Channel
100
D = 0.50
Thermal Response (Z thJA )
0.20
10 0.10
0.05
0.02
PDM
1 0.01
t
1
SINGLE PULSE t2
(THERMAL RESPONSE)
Notes:
1. Duty factor D = t / t
1 2
2. Peak T =JP xZ
DM +thJA
T A
0.1 A
0.00001 0.0001 0.001 0.01 0.1 1 10 100 1000
Appendix A: Figure 24, Peak Diode Recovery dv/dt Test Circuit — See page 329.
Appendix B: Package Outline Mechanical Drawing — See page 332.
Appendix C: Part Marking Information — See page 332.
Appendix D: Tape and Reel Information — See page 336.
154