EMBEDDED SYSTEMS et guction to Embedded System Os and Communication Buses a4 ea Modelling Concepts ml Time Operating Systems 71 81 NOTE: WBUT course structure and syllabus of 7th Semester has been changed from 2013. EMBEDDED SYSTEMS [EC 704B] has been introduced as a new subject in Pesent curriculum. The syllabus of this subject is almost same as EMBEDDED SYSTEM [EC 803B] of old syllabus. Taking special care of this matter we are boviding the relevant WBUT questions and solutions of EMBEDDED SYSTEM [EC 8) Papers from 2009 to 2012 along with complete solutions of new university Ret, $0 that students can get an idea about university questions patterns,POPULAR PUBLICATIONS INTRODUCTION TO EMBEDDED sy._ he time to access ; 1. Let h be the hit rate, M the miss penalty, C ti O88 ing cache. The average access time experienced by the processor 4°, a) tavg = (1~h)C +(1—h)M ¢) tavp=(1-h)C + hM Answer: (b) 2. L1 Cache is made of b) tava =hC+ (tye May d) tavg =hC + hm %, a) DRAM b) SRAM c) Both of these 4 woe, Answer: (b) 3. Memory requirement of ARM in Thumb mode is a}leve” . b) same Wee, -¢) more 4) depends on the system Answer: (a) 4. Which one of the following address structures denotes Direct Mappeg a) Tag 5; Block 7; Word 4 ¢) Tag 6; Block 6; Word 4 Answer: (a) 7 b)Tag 12;Word4 Wa d) None of these 5. Which one is not embedded in a single chip in an embedded system? | a) Memory ¢) A to D converter Answer: (4) 6. VLIW processor means a) Vory Large Instruction Word ¢) Very Load Instruction Word Answer: (d) 7. Which of the followin, a) laptop b) cellular phone Answer: (a) 8. How many layers ars aj2- Answer: (b) 19 is not an embedded system? weurz: b) Processor | d) None of these | | went b) Very Low Integrated Word | d) None of these t | preur ans b) washing machine d) pacemaker (3. e there in an embedded system design? (weut™" )3 °)4 as EMBS.-2Scanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerPOPULAR PUBLICATIONS Answer: 1" part: : The buses are used to pass the messages between different components There are buses existing as: les Memory Bus: it is related to the processor connected 0 > (RAM) using the data bus. This bus inctudes the collection of wiggs series and runs parallel to each other to processor and vice versa. consumed in reading and writing of in the is the same bus, © De-multiplexed Bus: these consists of two wires In consists of the address that need to be passed and the other one ep data that need to be passed from one to another. This is a faster m » to other. ; t © Input/Output bus: it uses the multiplexing techniques to multiple; input and output signals. This creates the problem of having the slow processing of it. 2™ part: Suction No, 6 of Short Answer Type Questions. 14, List out various uses of timers in embedded system? What is infinite loop in embedded systems? 3 Answer: such as executing a periodic task, implementing a PWM output or capturing time between two events to name a few. Depending on the architecture, have specific purposes. For example, on ARM cores, there is a systick used to provide the tick for an operating system. On most ARM and cores, there is a PIT ~ periodic interval timer, which can be used for any t See a aes eee been eck Gb 1 d t hardware however, preity ‘operate usi Theme spe hae gece i ae divider etc.). On each clock pulse, the timer either increments or d ‘When the counter reaches some defined value, an interrupt occurs. Pig Scanned by CamScannerScanned by CamScannerPOPULAR PUBLICATIONS are the firs capacity than L2. Also, L1 can be accessed faster than L2. L2 is accesseq requested data in not found in LI, Lt is usually in-built to the chip, while 12 ‘on the motherboard very close to the chip. Therefore, LI has a very Tittle delay to L2. Because L! is implemented using SRAM and L2 is implemented using be refreshed. If the caches does not need refreshing, while L2 needs to in be found in L2 as well. However, the caches are inclusive, all data in L! same data will not be available in both Land L2. Long Answer TY] tions State the difference between 4. What is an embedded system? computer system and general purpose computer system. Answer: “Part: ‘An embedded system is some combination of computer hardware and software, fixed in capability or programmable, that is specifically designed for a function. “A system which is a combi hardware and a General the user (It is possible for the end user to re- install the operating system and also add or remove user applications). “amScannerScanned by CamScannerScanned by CamScannerF — : consumption of the SRAM unit is especiall pyramie POT high. The long interconnects with high cect when the a eee anou Sia oe soliage variation, Owi i stern predictable switching activity factor, ae Eyith the interconnects that undergo a full es ae sori calculated using the famous dynamic power consumption eee ore secur PDynamic = afCinterconnectV2dd ee fis the frequency of operation, Cinterconnect is the in yadis the supply voltage. Merconnect capacitance and and explain, different reading mechanisms of SRAM from the memory with bri aa {WBUT 2011) Duferent Methods for Reading Data pe are four fundamental ways in which data can be read from an SRAM. They are: o Flow thru Pipeline (also called Register to Register) fo Register to Latch o Burst with the exception of Burst mode, the main differences between these different types of RAMs are in the relationship of the data out to the clock signal .Burst mode may be ‘sed in conjunction with flow thru and pipeline features. Figure 1 can be used to compare the relative timings. For simplicity, only the address signal, the clock, and the data output (0Q) are used to explain these methods for reading SRAM data. Flow Thru On flow thru SRAMs, addresses and other control signals are set up before the clock switches. Then, when the clock switches from low to high, the inputs are registered, and the read cycle begins, Sometime after the clock transition, but within the same clock cycle, data appears at the outputs. The time at which the data appears depends only on the original clock transition and the speed of the internal circuitry, Pipeline (Register to Register) On the pipelined SRAM, after all of the control signals are set up, the clock switches and ‘teread cycle begins, As the data is read from the memory cells, it is stored in a series of otput registers. The data is transferred from the output registers to the data output pins afer the clock switches on the next cycle. Data at the output always appears one cycle ster the address for that data was selected. . Register to Latch all of IBM Microelectronics’ synchronous Rams feature register inputs, only a *v ofthem also offer latched outputs. On the Register to Latch RAM, the addresses and ‘er control signals are set up, then loaded into a register when the first clock transition we Td sm the memory cells is stored in a set of latches. When, later in from high to low, the data is transferred from the ‘method permits the designer to control the time at adjusting the width of the clock pulse. EMBS-19 Tamia a etal re | Scanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScanneristers are available. ‘arite mare code to[instructions are like macros in € languaie, A desired programmer can achieve the functionality with single instruction which in} um provides the effect of using more simpler single instructions in RISC. [ Variable Teng More silicon usage since mot decoder logic is required to imp complex instruction decod Can be Harvard or Von-Neu! iC processor now-a-days high performance ombodded systoms use oither an RISC Prosar 2 pone ‘with an RISC core with a code-optimized CISC te note 50! ‘as ysed compute design approach means ARM pr fever transistors than typical complex instruction set comp! in most personal computers. This approach reduces costs, heat and power use. ‘Such reductions are desirable traits for light, portable, battery-powered devices including smart phones, laptops, tablet and notepad computers, and other embedded in terms of functionality, along feadvantage of an RISC in terms of faster program implementation as well as reduced word instantly availability to fove lengths. It implements faster because the register teecution unit. Code lengths are reduced because most instruction use registers as cperands. Few bits in the instruction specify a register as operands. 8, 16 or 24 bits specify a memory address as ‘operand and the displacement bits in the instruction. Microprocessors like ARM7 and ARM9 have a combination of RISC and CISC features. ARM supports a complex addressing mod based instruction set. ARM processor has an RISC core for processing. ‘There is an in-built compilation unit, It first compiles the CISC ‘nstuction into RISC formats, which are then implemented by the RISC core of the processor. Internally, the implementation for many instructions is like in a RISC (without ‘temicro-programmed unit). 4.4) What are the differences among direct mapping, associative mapping and eaivaraees used in Gache Memory Organization? [WBUT 2014) Aswcitve mapping: In this it iat is : type of mapping the associative memory is used to store Etlind addresses both ofthe memory word. This enables the placement of the ay ‘ey 2 place in the cache, memory. It i considered to be the fastest and the most ocessors require significantly siting (CISC) x86 processors ens, ARM provides advantages of using CIsScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScannerScanned by CamScanner5 : : 5 2 3 : aScanned by CamScannerScanned by CamScannerScanned by CamScannerPOPULAR PUBLICATIONS d) Flash memory Itis electrically erasable and programmable permanent type approach as EEPROM. Just like an EEPROM cell, itis also s that is controlled by trapped charge. Also just like EEPROM, memory can be erased in one operation. The name ‘Flash memory very fast reprogramming capability. Uses: For its low power consumption, flash memories are used in equipment like hand-held computers, cell phones, digital camer ©) Microprocessors vs. Micro-controllers: Refer to Question No. 13 (a) of Long Answer Type Quest ) Characteristics of an embedded system: Single-functioned - An embedded system usually performs a does the same repeatedly. For example: A pager always Tightly constrained — All computing systems have in those on an embedded system can be especially tight. Design implementation’ features such as its cost, size, power, and rf size to fit on a single chip, must perform fast enough to pro ‘consume minimum power to extend battery life. Reactive and Real time - Many embedded systems must con the system's environment and must compute certain results delay. Consider an example of a car cruise controller; it conti to speed and brake sensors. It must compute acceleration or d within a limited time; a delayed computation can result in failure Microprocessors based — It must be microprocessor or microco Memory ~ It must have a memory, as its software usually en need any secondary memories in the computer. ‘Connected — It must have connected peripherals to connect inpt HW-SW systems — Software is used for more features and e for performance and security. 4 Embedded Systems Structure sensor into a digital signal. Processor & ASICs ~ Processors process the data to meas Scanned by CamScannerScanned by CamScanner