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Design test questions

electronics (Jawaharlal Nehru Technological University, Hyderabad)

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Design_Test

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Setting standards in VLSI Design

Table of Contents

Part- 1: Digital ....................................................................................................................................... 3

Part- 2: Verilog...................................................................................................................................... 4

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Setting standards in VLSI Design

Part- 1: Digital(25 Maks)

1. Design Half adders using only Half Subtractors. (3M)
2. Blocks X and Y with their truth tables are shown below.

Implement all the AOI gates (and, or, inv) using blocks X and Y only. (2+3+3 =8M)
3. If the time period is 4 time the pulse width then the duty cycle is _____ (2M)
4. How many minimum number of flip-flops are needed to count the states
7,9,11,13,…125? (4M)
5. Using a single DFF and 2×1 MUXes, implement the following xyz flip-flop. (8M)

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Setting standards in VLSI Design

Part- 2: Verilog (25 marks)

1. Display the waveform mode of output for the following piece of Verilog code. (5M)

2. Write RTL for 8x3 Priority Encoder using case. (5M)

3. Write RTL code for [n:1] Multiplexer. (5M)

4. Design a sequence detector that will detect a sequence <1011=.

[A] Draw the Mealey overlapping sequence. (2M)

[B] Write the RTL code for the design. (4M)
[C] Write the TB for verifying the design. (4M)

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