Chipledga Physical Design Course POWERPLAN Learning Objectives: 1. How to perform Logical Connections 2. Create a basic power distribution structure. 3. Verify the Powerplan structure ‘Tasks: 1. Invoke the tool . Open the Library and floorplan block Perform Logical connections Set the attributes for Tie cells Create Ring around PLL Macro Create Straps of VDD and VSS Preroute Instances Create Rails for standard cell placement . Create Vias between Rails and Straps 10. Verify the Powerplan erpyagsuep Invoke the Tool : Open the project directory Invoke the tool Linux > ice2 shell 1 Chipedge Technologies Pvt Ltd., BangaloreChipedge Physical Design Course Open the Graphical User Interface (GUI) 2 shell > start_gui Perform Logical Connections Let's connect power, ground pins and ports to the specified power and ground nets. First Create PG nets ?_ shell > create_net -ground vss shell > create_net -power VDD on inowt VDD on inout vss VDD [get_ports VDD] VSS [get_ports VSS] Logically connect PG nets with the pins icc2_shell > connect_pg_net -net VDD [get_pins */VDD] > connect_pg_net -net VSS [get_pins */VSS] ‘Activity 1 1. Verify whether logical connectivity is done or not, get_nets -of [get_pins */VDD] get_nets -of [get_ports VDD] get_nets -of [get_pins */VSS] get_nets -of [get_ports VSS] Set the attribute for Tie cells (insertion will be done during optimization) shell > set_attribute [get_lib_cells */TIE*] dont_touch false 2 Chipedge Technologies Pvt Ltd., BangalorePhysical Design Course >set_lib_cell_purpose -include optimization */TIE*] Activity 2: 1. What is the use of TIE cells? 2. Check for the different types of TIE cells present in the library, use report_lib_cells -objects */TIE* command 3. Run the following command : get_lib_cells */TIE* , note the difference between report_lib_cells and get_lib_cells Create ring around PLL Macro Let’s create a ring around PLL macro considering Avdd as Power net. First create the power net Avdd and perform logical connections between the Avdd port and AVDD pin of PLL. Avdd j_net -net Avdd “pg net -net Avdd yet_ports Avdd] “pins */AVDD] ‘To create a ring, we need to run three commands, first is to create the pattern, set the strategy and then finally compile to get the ring physically. 3 Chipedge Technologies Pvt Ltd., BangalorePhysical Design Course In the GUI, check whether ring is created around PLL as shown in figure 1 Figure 1 Activity 3 : 1. Study and understand about the working of PLL 2. List the applications of PLL. Create Straps of VDD and VSS In the following part we will get a basic understanding of how to create power straps for our design. 4 Chipedge Technologies Pvt Ltd., BangaloreChipledga Physical Design Course Create Horizontal straps of VDD and VSS using layer M9 with a pitch of 8 and width 0.5, Activity 4: 1. Why higher metal layers are preferred for Vdd and Vss? 5 Chipedge Technologies Pvt Ltd., BangaloreChipEdge Physical Design Course 2, Check what is the pitch and width of Metal 8 and 9 in technology file 3. Refer to manual page of remove_routes -stripe Preroute Instance : We should connect PG pins of macros to PG straps. To perform this, you need to first set the pattern, strategy and then compile. Create the pattern, 11 > cx Preroute Instances for PLL macro The PG pins of PLL macro are Avdd and VSS, hence a separate flow to perform preroute for this macro. Create the pattern, 6 Chipedge Technologies Pvt Ltd., BangaloreChipEdgé Physical Design Course hell > create_pg_macro_conn_pattern preroute_pattern_pll - pin_conn_type scattered_pin -layers (M7 M6} Set the strategy, ice2_shell > set_pg_strategy preroute_pattern_pl PLLCLK_INST -pattern {{name:preroute_pattern_pll VSS}}} Now, compile the strategy, ice2_shell > compile pg -strategies preroute_pattern_pll_s _s -macros {nets: {Avdd Creation of rails for standard cell placement Similar to above, first create pattern , strategy and compile. Since the PG pins of standard cells in the given library are in metal 1, rails are created in Mi only. shell > create_pg_std_cell_conn_pattern std ck_std_cell_dre true -mark as follow pi attern -layers false shell > set_pg strategy rail strat -core -pattern {{namers td_pattern} {nets:VDD VSS}) c2_shell > compile_pg -strategies rail_strat Vias b/w Straps and rails 2_shell > create pg vias -nets {VDD VSS) -from_layers MI - ers M8 -dre no_check 0 Once you have run the above step go to the GUI, zoom into the core area, make sure that you are able to see the metal layers like the below snapshot (fig 5). By the above step we have connected the standard cell rails and made them a part of the power distribution structure. 7 Chipedge Technologies Pvt Ltd., BangaloreChipedge Physical Design Course Fig 5 Verify PG Nets Let’s check for floating wires and vias in the powerplan that we performed. Open error browser window (in GUI, Tool bar > View > Error Browser), to view the locations of errors in the GUL Check for DRC errors in the design, i Open error browser window, to view the locations of errors in the GUI. aeeddate 8 Chipedge Technologies Pvt Ltd., Bangalore