Compiler Directive, System Tasks and Test bench

TEST BENCH

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Once a design block is completed, it must be tested g y y A design block needs to be tested for its functionality by applying stimulus and checking results. For testing the design block, a stimulus block or test bench can be created in Verilog itself. g In the test bench we provide some stimulus to the p corresponding inputs of the design module.

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Stimulus Block Instantiates Design Block

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Stimulus and Design Blocks Instantiated in a Dummy Top Level Module Top-Level

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TEST BENCH FLOW

Synthesis

Verilog Code (Gate Level Netlist) )

Verilog Code

Verilog Test Bench

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Example
module and_gate ( , ,y); _g (a,b,y); input a,b; output y; assign y= a & b; endmodule

module and_test (); reg a,b; wire y; and_gate and gate a1(a,b,y); initial begin a=1b0;b=1b0; 1b0 b 1b0 #100; a=1b0; b=1b0; #100; a=1b0; b=1b0; #100; a=1b0; b=1b0; end endmodule d d l
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 System tasks are meant for carrying out certain routine operations like displaying signals, nets, time, simulation control etc. Syntax : $<keyword> All the system tasks start with $ . These system tasks are behavioral constructs.
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Different Types of System Tasks

$display $ $monitor it $monitor on, $monitor off $strobe $write $finish $stop

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 These system functions will return the integer value of simulation time at which they are executed. $time : returns time (integer) in 64 bits $stime : returns time (integer) in 32 bits $realtime : returns time (real)

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 These system tasks are used for displaying and printing information. These system tasks are characterized into: Display and write tasks St b d monitoring t k Strobed it i tasks Continuous monitoring tasks

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Syntax: system task name (p1, p , p , p , p , , pn); y (p , p2, p3, p4, p5, , p ); The arguments p1 p2 p3 ,pn can be strings p1, p2, p3, pn strings, format specifications, variables etc. The system task name can be one of: $display or $displayb or $displayh or $displayo $write or $writeb or $writeh or $writeo
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FORMAT

DISPLAY

%d or %D ------------------------------- in decimal %h or %H ------------------------------- in hexa decimal %b or %B ------------------------------- in binary y %o or %O ------------------------------- in octal %s or %S ------------------------------- string %c or %C ------------------------------- ASCII %m or %M ------------------------------ Hierarchical name %e % ------------------------------- real in scientific li i ifi %f ------------------------------- real in decimal

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 These system tasks automatically inserts a new line at the end after printing the information. If no format specification exists for an argument then: $display : displays argument values in decimal. $displayb : displays argument values in binary. $displayh : displays argument values in hexadecimal. $displayo : displays argument values in octal.
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Example
module and_gate (a,b,y); input a,b; output y; p assign y= a & b; endmodule

TEST BENCH:
module and test (); and_test reg a,b; wire y; and_gate a1(a b y); and gate a1(a,b,y); initial begin a=1b0;b=1b0; 1b0 b 1b0 #100; a=1b0; b=1b0; #100; #100 a=1b0; b=1b0; #100; a=1b0; b 1b0 1b0 b=1b0; end

initial $display($time. The value of a=%b, b=%b, y=%b, a,b,y); endmodule

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 These system tasks prints the information without automatically inserting a new line at the end. If no format specification exists for an argument then: $write : displays argument values in decimal. $writeb : displays argument values in binary. $writeh : displays argument values in hexadecimal. $writeo : displays argument values in octal.
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 These system tasks display the data at the end of the simulation time at which they are executed. If no format specification exists for an argument then: $strobe : displays argument values in decimal. $strobeb : displays argument values in binary. $strobeh : displays argument values in hexadecimal. $strobeo :: displays argument values in octal.
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 These system tasks displays the data whenever there is a change of value in an argument in the argument list and displays at the end of the simulation time at which they are executed. If no format specification exists for an argument then: $monitor : displays argument values in decimal. $monitorb : displays argument values in binary. $monitorh :: displays argument values in hexadecimal. $monitoro : displays argument values in octal.
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// module D FF with synchronous d l D_FF i h h reset module D_FF(q, d, clk, reset); output q; input d, clk, reset; reg q; always @(posedge reset or negedge clk) if (reset) q <= 1'b0; ; else q <= d; endmodule

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module stimulus; reg clk; reg reset,d; wire[3:0] q; [ ]q D_FFd1(q,d,clk,reset); initial clk = 1'b0; always #5 clk = ~clk; initial begin reset = 1'b1; d=1b1; d 1b1 #15 reset = 1'b0; #50 d=1b0; #180 reset = 1 b1; 1'b1; #10 reset = 1'b0; #20 $finish; initial ta $monitor($time, " Output q = %d", q); endmodule VLSISYSTEMDESIGN 20

 $stop : causes the simulation to be suspended /

places in interactive mode, and the partial results can be analyzed. anal ed $finish : causes the simulation to terminate / exits p the simulator and pass the control back to the host operating system.

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initial forever #10 clock = ~ clock;

initial #700 $finish; initial i iti l

initial #100 $ 100 $stop;

clock = 1b0; initial

initial ; clock = 1b0;

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forever #10 clock = ~ clock;

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Compilerdirectives Compiler directives

Compiler directives
These are preceded by back quote (`) character. When compiled these directives in effect through the entire compilation. The effect of these directives can be felt across many different files. The effect stays till a different compiler directive supercedes it or the processing completes.

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`define & `undef

`define directive is used for text macro substitution. substitution The compiler substitutes the text of the macro for the string `macro_name in the source description of modules. A previously defined text macro can be undefined by using the ` d f di d fi d b i h `undef directive. i

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`timescale
This directive specifies the time unit and time precision of the modules that follow it. The time unit is the unit of measurement for time values such as the simulation time and delay values values. Syntax: `timescale time u t / t e p ec s o Sy tax: t esca e t e unit time precision Time unit: s, ms, us, ns, ps, fs. The magnitude can be scaled by: 1, 10 or 100.

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`timescale -Example timescale Example

`timescale 100 ns / 1 ns module dummy1; reg toggle; //initialize toggle initial toggle = 1'b0; always #5 b i l begin toggle = ~toggle; $display("%d , In %m toggle = %b ", $time, toggle); end endmodule

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`include
This compiler directive is used to insert/include the entire contents of a source file in another file during compilation. l Syntax: `include file name include file name The filename is the name of the file to be included in the source file. E Example: l `include mem_data.txt module mem1KB(.); endmodule

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Reference
1. Samir Palnitkar,Verilog HDL: A Guide to Digital , g g Design and Synthesis Prentice Hall, Second Edition,2003 2. T.R.Padmanabhan and B B l T i 2 TRP d bh d B.Bala Tripura S d i D i Sundari, Design Through Verilog HDL Wiley Student Edition

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