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CDC Signoff Using SDC
CDC Signoff Using SDC
Ravindra Nibandhe
Rangarajan Govindan
July 2018
CDC analysis with Synopsys Design Constraints (SDC) – challenges and solutions
CDC Analysis
Identify clock domains
CDC
Identify CDC paths Setup
Identify synchronizers
Persistent Interactive
Violation
Database Advanced CDC Checks
Divergence / Re-convergence
Reset Check
• Complete CDC analysis for reset synchronization and Reset Domain Crossing flops with
async reset to receive reset attributes
Black-
Box
A
Y
B
sel=0
SDC Reading
Understanding
Constraints
Clock
Interpretation
Propagation
Name Mapping
Name Mapping
• Debug Steps
– Use Instance Browser of SpyGlass GUI.
– The hierarchy or pin name could be different
– Or Add the following to your SDC file and capture the stdout
– Replace the non-alphanumeric characters with wildcards to more likely
achieve a match.
set myinst [get_cell mid/myregs/q_out*]
sdc_puts “\n\n####### instance names are:\n”
sdc_puts “$myinst\n\n\n########\n\n”
• For faster turn around you can create a goal that only
contains the rule SDCPARSE
• Names that are escaped by necessity in Verilog (and SpyGlass) should not be escaped in the
SDC
• The temptation would be to write the constraint as below with a space after the bracket.
set_false_path –from i1/\mycell[0]{space} /Z
• For Verilog 2K only the explicit label is • For SystemVerilog, an implicit label is produced in
part of the instance name the form “genblk#”. Where # is the number of the
– So the example shown above will have an
generated block in the module.
instance that looks like: g01.u0
• In this case, the generated instance name will be:
genblk1.g01.u0
test.sgdc
current_design test
sdc_data –file test.sdc
test.prj global.tcl
read_file test.v current_design test
read_file –type sgdc test.sgdc define_name_rule myrule \
current_methodology\ –allowed {a-z A-Z 0-9 _} \
$SPYGLASS_HOME/GuideWare/latest/block/rtl –replacement_char “%”
_handoff change_names –rules myrule -hierarchy
set_parameter pt supermode
test.sgdc test.sdc
current_design test current_design test
sdc_data –file global.tcl –file test.sdc set_false_path –from myreg_reg%3%/CP
Constraints Interpretation
• Certain commands, options, and legal points of application are different depending on whether
one is writing constraints for PrimeTime (STA) vs. Design Compiler (synthesis)
– For e.g.- The change_names command in SDC may only be applied in Design Compiler but not in
PrimeTime
• To accommodate users who wish to have the more strict enforcement of PrimeTime but also
allow the change_names command, yet another mode is available for this parameter:
“supermode” - This will enforce PT strictness yet allows change_names
Attribute pt = no pt = yes/supermode
direction Not Supported Supported
name Supported Not Supported
• There can be a top level single SDC file sourcing separate SDC files for setup, clocks, case analysis etc
– Specify the top level SDC file as shown below:
current_design test
sdc_data –file top.sdc
• Since SDC doesn’t contain all the constructs necessary for CDC analysis it becomes
necessary to augment the SDC with SGDC
• Since clock relationships are defined with the set_clock_group command in SDC, if you create
a NEW clock in SGDC, there is no way to say it is synchronous to any of the existing clocks
– The domain names assigned in the SDC could change based on a change in the SDC file
current_methodology $SPYGLASS_HOME/GuideWare/latest/block/rtl_handoff
set_parameter sdc_domain_mode sta_compliant; #(Optional) default value. Recommended parameter.
set_parameter pt no; #To allow names of design objects to be changed. This is
helpful to reduce noise present for design objects present
under generate blocks
set_parameter show_all_sdc_violations yes; #To enable reporting of all issues for the SDC
set_parameter tc_ignored_commands ./ignored_sdc_commands.txt
set_parameter tc_stop_parsing_ignored_commands yes; # To stop parsing of the nested/auxiliary commands
present in the SDC commands which are ignored
set_parameter sdc_generated_clocks yes; #To have the generated clock definitions translated to
clock constraint
set_parameter enable_generated_clocks yes; #To have the generated clock definitions translated in
uncommented format