JOURNAL OF LATEX CLASS FILES, VOL. X, NO.
X, AUGUST 202X
Crypto-Coding Scheme via Dynamic Interleaver for
New Communication Standards
Raúl Eduardo Lopresti, Jorge Castiñeira Moreira and Luciana De Micco
Abstract—Emerging communication standards prioritize both
the assurance of secure and reliable communications as well as
the reduction of transmission delay and latency. Nevertheless,
the task of achieving these objectives presents a complex and
demanding challenge. Ensuring secure transmissions while si-
multaneously minimizing error rates requires the implementation
of multi-stage information processing techniques that integrate
coding and encryption methods, which may unfortunately lead
to an undesired increase in transmission delay and latency. This
research presents an innovative crypto-coding framework capable
of concurrently achieving essential encryption and coding within
a single, streamlined process. By leveraging this approach, we
aim to address the trade-off between security, efficiency, and
transmission delay, thus contributing to the advancement of
secure and efficient communication standards. In this paper,
we present a comprehensive evaluation of the proposed scheme,
assessing its impact on final system error probability, encryption
efficacy, and the complexity of hardware implementation. Our
findings shed light on the potential benefits of this approach for
future communication standards.
Index Terms—Coding, Delay, Dynamic Interleaver, Encryption,
Latency, Non-systematic, Security, Turbo Codes.
I. I NTRODUCTION
Wireless communications networks have reached an un-
precedented level of development.
Turbo Codes (TC) possess the advantage of architectural
flexibility, enabling the incorporation of alternatives within
their structure. This adaptability allows for the enhancement
of security levels, potentially obviating the need for a separate
encryption block. The possibility of jointly implementing an
error control and data encryption scheme is attractive both to
avoid BER degradation of the cascading application of such
processes and to reduce the latency and delay of a system.
Recently, work has emerged proposing the incorporation
of security in codification, in particular focusing on TC. In
[1], a symmetric encryption scheme is suggested to improve
transmission security. The authors propose a system that per-
forms interleaving of the information bits and puncturing the
parity bits at the encoder. How both processes are performed
is controlled by a symmetric encryption private key. In [2],
the authors present a joint encryption and scrambling method
called CFB-AES-turbo, which combines the AES (Advanced
The authors are with Instituto de Investigaciones Cientı́ficas y Tecnológicas
en Electrónica (ICYTE) of Facultad de Ingenierı́a - Universidad Nacional de
Mar del Plata (FI-UNMdP) at Av. Juan B. Justo 4302, B7600 Mar del Plata,
Buenos Aires, Argentina, and Consejo Nacional de Investigaciones Cientı́ficas
y Técnicas (CONICET), Mar del Plata, Buenos Aires, Argentina at Av. Juan
B. Justo 4302, B7600 Mar del Plata, Buenos Aires, Argentina (e-mails:
raul.lopresti@fi.mdp.edu.ar; casti@fi.mdp.edu.ar; ldemicco@fi.mdp.edu.ar).
Manuscript received ; revised
1
Encryption Standard) algorithm and turbo encoding. In [3],
a modified turbo encoder is proposed whose building blocks
are finite state sequential machines in which a non-linear
function that varies its coefficients in time is inserted. Using
this configuration, the authors manage to increase the security
of the turbo system while maintaining its performance. In
[4], the authors introduced a second Interleaver and managed
it through secret keys to enhance information encryption.
They found that, from a reliability perspective, the proposed
system behaves equivalently to the classical one. To assess the
cryptographic strength of the system, they employed the linear
correlation coefficient.
This article introduces a novel crypto-encoder scheme en-
gineered to fortify the security of data transmission while
preserving the error correction capabilities inherent in turbo
encoders. The principal objective is to augment the entropy of
transmitted data within the channel without compromising the
Binary Error Probability (Pbe ) and evading a substantial rise
in implementation complexity. These objectives are attainable
by leveraging the adaptive framework of the proposed system,
which dynamically modulates the interleaving mechanism and
orchestrates data masking through a Pseudo Random Num-
ber Generator (PRNG). This continual adaptation ensures a
judicious equilibrium between heightened security measures
and streamlined implementation protocols. The use of various
PRNG with different statistical properties is examined here in
terms of security by using NIST tests and Binary Entropy in
the channel, Pbe at the receiver, and finally, comparing the
cycles and hardware complexity required of our proposal with
a classical one.
II. DYNAMIC I NTERLEAVER
The proposed scheme relies on a turbo encoder, wherein the
fundamental configuration comprises two encoders operating
concurrently. One of these encoders receives the data directly,
while the other does so through an Interleaver. Given that
the traditional turbo encoder is systematic, information is
also transmitted to the channel, and the transmission of each
code bit is alternated through a process of puncturing. In
the proposed case, the systematic data was replaced by the
outputs of both encoders, thus avoiding raw information being
available in the channel. In this way, decoding is simplified
concerning the classical scheme. A simplified structure of the
proposed scheme is shown in Fig. 1. In addition, the incoming
data to the crypto-encoder undergoes an initial XOR operation
with the output of the PRNG. It is important to note that,
unlike the classic turbo encoder, the Interleaver block is now
JOURNAL OF LATEX CLASS FILES, VOL. X, NO. X, AUGUST 202X
Fig. 1. Simplified scheme of the proposed crypto-encoder. The Interleaver
is generated by a PRNG and changes every time a data block is sent,
simultaneously masking the incoming data.
dynamic, meaning it varies over time based on a specified
PRNG. This PRNG is responsible for generating a sequence
of N numbers for each transmission, starting from an initial
seed that would operate as the key, where N is the size of the
Interleaver. Then, the choice of the PRNG is not trivial since
it must satisfy the following conditions:
1) To present high randomness in the channel in order to
enhance security against potential attacks.
2) To achieve a Pbe at the receiver that is equal to or
less than what would be obtained with a classic scheme
(encryption + encoding), considering that the sequential
use of the encryption algorithm would result in a Pbe
increase.
3) To enable hardware implementation that utilizes the
minimum amount of resources, offers low latency, and
allows for a high operating frequency.
On the receiver side, the decoder must be aware of the
employed rule and the seed; these are the keys of the system.
The three conditions mentioned above were evaluated as
follows:
1) The level of randomness in the data transmitted through
the channel was assessed using two methods: differential
entropy and by NIST tests [5].
2) The Pbe was calculated as a function of the signal-to-
noise ratio (SNR) in all cases at the receiver, considering
AWGN noise.
3) The proposed crypto-coder circuit was developed and
implemented in hardware using an FPGA, and the
required resources were reported. Also, a qualitative
analysis of the required cycles was conducted for both
the proposed case and a classic configuration.
Various configurations of the employed PRNG were evaluated
to ensure compliance with the predefined conditions. In all
cases, the vector generated by the PRNG was sorted in
ascending order, and the interchanges in the indices between
the unsorted vector and the sorted one were recorded to
construct the Interleaver.
III. E VALUATION OF THE PROPOSED C RYPTO -E NCODER
To assess the security and reliability of the proposed
scheme, considering different PRNG-based for the Interleaver,
we calculated the randomness of the crypto-coded data in the
channel and the Pbe at the receiver. A simulation that models
the transmitter, the channel and the receiver was developed.
To compare various configurations, the Interleaver was set
up in both, the traditional block (statically) manner, and the
2
dynamically evolving approach proposed here. In the static
Interleaver, the same order is maintained throughout the entire
transmission (designated as “S”), whereas in our proposed
approach, the Interleaver dynamically reconfigures every N
transmitted data (referred to as “D”). The Interleaver order
was established using various PRNGs, each characterized by
distinct statistical properties. The aim was to explore potential
relationships, if any, between these properties and the system’s
performance. The PRNGs tested are Linear Feedback Shift
Register (LFSR) with primitive polynomial x16 + x14 + x13 +
x11 + 1, Synchronous Cellular Automata network (CA) with
59 5-input cells with periodic boundary conditions and Rule
1771476585, Logistic Chaotic Map (LOG) [6], its fourth
iteration (LOG4) and a uniformly distributed random PRNG
was generated using a Matlab function. Table I compares
the proposed PRNGs in terms of implementation complexity,
randomness, and repetition period length.
TABLE I
P ROPERTIES OF THE PRNG S USED IN THE TESTED I NTERLEAVERS .
PRNG Hardware Complexity Statistical Properties Period
LFSR Low Very Low Long
CA Low Low Short
LOG Medium Medium Long
LOG4 Moderated Moderated Long
RAND High High Very Long
A. Randomness analysis
1) Differential entropy: We use a quantifier that is derived
from Shannon’s entropy [7] specifically designed for the
analysis of binary data. [8] The differential entropy (hb ) is
calculated as follows:
hb = Sw+1 − Sw , (1)
where Sw represents the well-known Shannon entropy, with
the subscript w denoting that the measure was applied to a
concatenated series of w digits. As w increases, the quantifier
converges toward the entropy of the source, indicating greater
randomness as its value increases.
Figure 2 illustrates that all the Interleavers based on dynamic
PRNGs (D LOG, D LOG4, D RAND, and D CA), except
for the LFSR, exhibit the highest level of randomness. They
overlap on the same upper curve, stabilizing at approximately
0.4. On the other hand, all the static versions of the mentioned
Interleavers, along with the dynamic version of the LFSR, ini-
tially maintain a low positive value before eventually reaching
zero. Finally, S LFSR presents a lower value for small w values
until it falls to zero. Additionally, the least random behavior
corresponds to the Block Interleaver, which never rises above
zero.
2) NIST tests: The Special Publication (SP) 800-22 of
the National Institute of Standards and Technology (NIST)
represents a robust statistical package encompassing 15 dis-
tinct tests for assessing the randomness of sequences [5].
Capitalizing on the comprehensive nature of this suite, we
employ all 15 tests to evaluate the encryption capabilities
inherent in the proposed crypto-encoder.
JOURNAL OF LATEX CLASS FILES, VOL. X, NO. X, AUGUST 202X
Fig. 2. Differential Entropy on the bits transmitted via the Block, CA, RAND,
LOG, LOG4 and LFSR Interleavers in their Static and Dynamic versions.
Dynamic versions, except for the LFSR, maintain a nonzero entropy value as
w increases, while static versions and the dynamic version of the LFSR go
to zero as w increases.
Fig. 3. Error probability for different signal-to-noise ratios using Block, CA,
RAND, LOG, LOG4 and LFSR Interleavers in their Static and Dynamic
versions.
In the Dynamic case, only the logistic, its fourth iteration,
and the random approach passed the NIST tests when digitiz-
ing was involved from the 15th bit onward and considering
the two least significant bits for the XOR masking. The rest
of the dynamic methods, LSFR and CA, do not pass the tests.
Meanwhile, none of the static methods pass them. Table II
displays the results of the test applied to the Dynamic Inter-
leaver, utilizing LOG4 and LFSR as the PRNG. Additionally,
it presents the results applied to the Static version of LOG4.
This table illustrates that only the D LOG4 passes the tests.
B. Error probability
The calculation of Pbe followed simulations akin to those
conducted in [9], involving the transmission of 2.5 × 106
data units within GF(4) using Interleavers sized at 10 000.
This process was repeated five times, and the results were
subsequently averaged. In Figure 3, it is observed that the
traditional Block Interleaver exhibits the poorest performance
among the studied scenarios. For SNR greater than 2 dB, both
3
the Dynamic and Static logistic Interleavers display inferior
behavior, only surpassed by dynamic CA at 1.5 dB. It can
be observed that both Static and Dynamic LFSR, LOG4,
and Rand Interleavers demonstrate the best and relatively
comparable performance among themselves.
C. Hardware Implementation
This design was implemented on a Xilinx Zedboard FPGA
to verify its feasibility. The resources used in the implemen-
tation when the PRNG is a LFSR with primitive polynomial
x16 + x14 + x13 + x11 + 1 can be seen in Table III. Fig. 4
shows the block diagram of the implemented crypto-encoder.
It consists of the following blocks:
• PRNG → Provides a pseudo-random number at each
clock cycle.
• SIPO (Serial-Input Parallel-Output) → Shift register with
serial input and parallel output. Serves as an interface to
the pipeline stages.
• EIPO →It is similar to a SIPO, but writes can occur at
arbitrary positions rather than incrementally.
• PISO (Parallel-Input Serial-Output) → Shift register with
parallel input and serial output. Serves as an interface to
the pipeline stages.
• PIRO. → It is similar to a PISO, but the data is rotated
in the registry instead of discarded.
• Sorting → Order the numbers and provide indexes of the
new positions.
• FSSM → It performs the encoding. In particular, the e0
FSSM block also provides its trellis state via the s signal.
• Ending → Performs trellis termination relevant to TCs.
• Indexing → Provides the index for the EIPO block.
• Control (not shown in the diagram for legibility reasons)
→ Synchronises the system through enable and control
signals.
The design has 4 pipeline stages identified in the diagram by
S0 , S1 , S2 and S3 .
IV. C ONCLUSIONS
Results showed that it is feasible to realize a communication
system with a single encryption-coding process using a time-
varying Interleaver with good security properties and transmis-
sion reliability. This scheme has the advantage of reducing the
cycles required in both the transmitter and the receiver, thus
reducing delays and latencies. Among the PRNGs studied, the
Interleaver based on the fourth iteration of the logistic map is
the one that presented the best performance in terms of error
probability and randomness in the channel. Moreover, it was
demonstrated that the hardware implementation of this design
does not require a significant amount of extra resources.
ACKNOWLEDGMENTS
This work was partially funded by ICTP (the Abdus Salam
International Centre for Theoretical Physics), the ANPCyT
(Agencia Nacional de Promoción Cientı́fica y Tecnológica,
PICT2019-03024) and the NVIDIA Academic Hardware Grant
Program.
JOURNAL OF LATEX CLASS FILES, VOL. X, NO. X, AUGUST 202X 4

TABLE II
R ESULTS OF THE APPLICATION OF THE 15 NIST SP800-22 TESTS ON 100 BITSTREAMS ( EACH WITH 107 BITS ) GENERATED
BY THE PROPOSED SYSTEM USING THREE DIFFERENT PRNG S : LOG4 DYNAMIC , LOG4 STATIC AND LFSR DYNAMIC .

PRNG D LOG4 S LOG4 D LFSR

Tests p-value Rate p-value Rate p-value Rate
Frequency 0.096578 97/100 0.350485 100/100 0.978072 98/100
BlockFrequency 0.719747 98/100 0.008879 99/100 0.534146 100/100
CumulativeSums 0.181557 97/100 0.213309 100/100 0.637119 100/100
Runs 0.275709 99/100 0.350485 100/100 0.455937 100/100
LongestRun 0.955835 99/100 0.213309 100/100 0.816537 100/100
Rank 0.383827 98/100 ∗ 0.000000 13/16 ∗ 0.000000 0/100
FFT 0.366918 98/100 0.534146 100/100 0.066882 99/100
NonOverlappingTemplate 0.455937 99/100 ∗ 0.000089 100/100 ∗ 0.897763 94/100
OverlappingTemplate 0.419021 97/100 0.066882 100/100 0.048716 98/100
Universal 0.000114 99/100 0.350485 100/100 0.437274 100/100
ApproximateEntropy 0.595549 98/100 ∗ 0.000000 7/16 0.637119 99/100
Serial 0.867692 99/100 ∗ 0.000000 4/16 ∗ 0.000000 0/100
LinearComplexity 0.048716 99/100 0.066882 100/100 0.108791 98/100
RandomExcursions 0.162606 86/88 0.162606 62/62 0.201069 95/96
RandomExcursionsVariant 0.227773 87/88 0.006196 62/62 0.447593 96/96

Fig. 4. Design diagram of the crypto-encoder implementation.

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