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Unit 1: IC Fabrication

Lecture 1.4:
Fabrication of Typical Circuit

Dr. Ganesh Samudra, Dr. Shajith Ali & Dr. R.

Ramaprabha
Department of EEE
SSN College of Engineering, Chennai

IIYear / 4th Sem: UEE2402– Analog Electronic Circuits (AEC)

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Learning Objective

To apply the knowledge gained through Lecture 1. 1 to 1.3

for a circuit fabrication
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TYPICAL CIRCUIT
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VARIOUS STEPS INVOLVED IN
FABRICATION OF THE CIRCUIT
➢Wafer Preparation and buried layer formation
➢Epitaxial Growth
➢Oxidation
➢Isolation Diffusion
➢Base Diffusion
➢Emitter Diffusion
➢Contact and Aluminium metallization
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Step 1: Wafer Preparation and Buried
Layer Formation
• A p-type silicon wafer is prepared by
• Crystal growth and doping
• Ingot Trimming and grinding
• Ingot slicing
• Wafer polishing and etching
• Wafer cleaning
• Size-10 cm to 30 cm in diameter and 0.4-0.5
mm thickness
• Resistivity is 10 ohm cm corresponding to
concentration of acceptor atom.
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Layer Formation
• The masks for the whole circuit are included in
the summary slide at the end. Here only mask
openings are shown.
• A heavily doped buried n-type layer is formed
by Sb or As implant and diffusion(No P?)
• It is formed below only the bipolar transistors
to lower collector resistance.
• Sheet Resistivity is ~50 ohm per square.
• Not included in the follow-up slides due to
many components shown to avoid crowding.
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Step 1: Wafer Preparation

and Buried Layer Formation

n++
P-type substrate 400 µm
10 Ω-cm resistivity;NA =1.4 * 1015 atoms / cm3
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Step 2:Epitaxial Growth

• A n-type epitaxial film (epi in short) is grown
on the p-type substrate which becomes the
collector region of the transistor.
• All active and passive components are
fabricated within this layer.
• Resistivity – 0.1 to 0.5 ohm cm
• Only way to form high doped layer below
lower doped epi is the way the buried layer is
formed. Why?
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Step 2:Epitaxial Growth

n-epi layer 0.1 – 0.5 Ω-cm 5-25 µm

P-type substrate 10 Ω-cm

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Step 3: Oxidation
• A SiO2 layer of thickness of the order of 0.02
to 2 µm is grown on the n-epitaxial layer.
SiO2

0.02 – 2 µm
n-epi layer 0.1 – 0.5 Ω-cm

P-type substrate 10 Ω-cm

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Step 4:Isolation Diffusion

• SiO2 is removed from 5 different places by
photolithographic technique.
• Wafer -> subjected to heavy p-type diffusion so
that p-type impurities penetrate the n-type
epitaxial layer and reach the p-type substrate.
• Area under SiO2 =n-type islands(covered by p-
type moats) (Why 4 islands are needed?)
• The isolation p-collector n junctions are held at
reverse bias so that they are electrically isolated.
Hence these form isolation regions.
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Step 4:Isolation Diffusion

• The concentration in isolation islands >> p-
type substrate.
• The isolation p-regions are not shown in the
diagram for simplicity as they are very deep
joining p-substrate. However their locations
are clearly marked.
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Step 4:Isolation Diffusion

Diffusion of p-type impurities

Island -1 Island -2 Island -3 Island -4

n - epi n - epi n - epi n - epi

P-type substrate
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Step 5:Base Diffusion

• A new layer of SiO2 is grown over entire wafer and 4
smaller openings are make within 4 n-islands.
• P-type impurities like boron are diffused within islands
of n-type epitaxial silicon.
• This diffusion is controlled so that it does not penetrate
through n epi layer and confined within it. Also, it
provides room for a contact and emitter for BJT.
• This diffusion is used to form the Base of the transistor,
resistor, the anode of the diode and the junction
capacitor. (What decides doping?)
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Step 5:Base Diffusion

p p p p
nnn
n n n n

P-type substrate

Capacitor Diode Transistor Resistor

Region
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Step 6:Emitter Diffusion

• A new layer of SiO2 is again grown on the
entire wafer and n-type impurity is diffused
through selected patterned areas, which form
the emitter and cathode of diode.
• Normally heavily doped n-regions are used.
• Al ->used for interconnection.
• Heavy doping of phosphorous in Si-lattice
makes it semi-metallic which makes a good
ohmic contact with Al –layer.
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Step 6:Emitter Diffusion

Window
W1 n+ Window W2 n+

n+ n+ n+ n+
p p p p
nnn
n n n n

P-type substrate
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Step 7: Aluminium Metallization

• A new layer of SiO2 is formed again. The
contact mask is patterned to open Al
connection areas.
• A thin even coating of Al is vacuum deposited
on the wafer.
• The interconnection pattern is then formed
between transistor, resistor, diode and
capacitor.
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Step 7: Aluminium Metallization

n+ n
n+ n+ +

p p
p p
nnn
n n n n

Buried
P-type substrate Layer

Capacitor Diode Transistor Resistor

Region
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Summary of processes
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Practice Questions

(1) You can take any circuit with up to 5

components in UEE2303 bipolar circuits and
develop full process and illustrate with
description and cross sections. Do this for
the circuit below without capacitor C2.
(2) Is epitaxial layer needed in MOSFET
fabrication?
(3) How will you form a diode in MOSFET
fabrication process without adding any new
process step?
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Practice Questions
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Summary

• The fabrication of a typical circuit has been discussed

with the knowledge of all the fabrication procedures.

References

1. D. Roy Choudhury, Shail B. Jain, ‘Linear Integrated Circuits’, II edition,

New Age, 2003.
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Outcome of the module

✓ The students are able to explain fabrication

procedure for any circuit consisting of
transistors, diodes and passive components.