1

Unit 1: IC Fabrication

Lecture 1.1: ICs and Semiconductor

Fabrication Processes

Dr. Ganesh Samudra, Dr. Shajith Ali, Dr. R.

Ramaprabha, Dr. Premanand
Department of EEE
SSN College of Engineering, Chennai

IIYear / 4th Sem: UEE1405– Analog Electronic Circuits (AEC)

 2
Learning Objective

To understand the basic process steps used in IC

fabrication.
 3
Structure of BJT
• What NPN processing Symbol:
unit Transistor steps are needed
and function you can expect from each of
the unit processing steps to fabricate the
Bipolar Junction Transistor (BJT)
structure you have learnt in UEE2303?
 4
Outline
In this lecture, you will learn about
• Basic process steps used in fabrication.
• Starting Si wafer growth
• Brief usage of surface topography steps like lithography,
etching and deposition.
• Brief usage of doping/thermal steps like epitaxy, oxidation,
diffusion and ion implantation.
• A process sequence that normally occurs when one
fabrication step using a mask layer is processed to
achieve desired results.
 5
Semiconductor Manufacturing Process

CIM-Computer Integrated Manufacturing.

 6
MONOLITHIC Ics - Basic Fabrication Steps

• Silicon wafer preparation

• Epitaxial growth.
• Photolithography/Etching
• Metallization/Deposition
• Oxidation
• Ion implantation
• Diffusion
• Isolation technique
• Assembly processing and packaging
 7
Crystal Growth and Wafer Manufacturing
• Quartz, or Silica, Consists of Silicon Dioxide
• Sand Contains Many Tiny Grains of Quartz
• Silicon Can be Artificially Produced by Combining Silica
and Carbon in Electric Furnace
• Gives Polycrystalline Silicon (multitude of crystals)
• Practical Integrated Circuits Can Only be Fabricated from
Single-Crystal Material
• Crystal growth and uniform doping of whole wafer are done
together.
• Highly purified polycrystalline silicon is put in a crucible
along with dopant .
 8
Crystal Growth and Wafer Manufacturing

• It is kept in a quartz crucible and heated in a furnace

(14200C) till the silicon melts
• Silicon single crystal rod (called seed crystal) is dipped into
it and pulled out slowly to form solidified mass of single
crystal silicon.
• During this pulling process, the seed crystal and crucible
are rotated in opposite directions to produce circular cross
sectioned ingots.
• Requires Careful Control to Give Crystals Desired Purity
and Dimensions.
 9
Crystal Growth and Wafer Manufacturing
 10
Crystal Growth and Wafer Manufacturing
• The ingots can be of a meter or two meters in height and
up to 16 inches in diameter.
• Trimming grinding and slicing – crystal is then trimmed and
sliced using diamond tip saw to get a definite shape
• Wafer polishing and etching is done to remove any
damage during sawing.
• Wafer cleaning to remove contaminants.
• Most state-of-the-art fabrication facilities use 12 inch
diameter Si wafers. One meter long Si ingot can yield up to
2000 wafers as a wafer typically is 0.5 mm thick.
• Compound semiconductor wafers are much smaller in
diameter.
 11
Crystal Growth and Wafer Manufacturing
 12
Epitaxial growth
• The process of growing a thin layer of single-crystal silicon
over the silicon substrate in an epitaxial growth furnace
with right percentage of dopant compound gas to achieve
uniform doping during growth.
• For n type silicon layer (silicon tetrachloride + PH3).
• For p type silicon layer (silicon tetrachloride + B2H6)
• Basic chemical reaction
SiCl4 + 2H2 -> Si + 4HCl
• Typical temperature :~12000c
• Mostly used in bipolar and compound semiconductor
processes. Hence it is optional.
 13
Lithography

• Consider fabrication of bipolar transistor in Si as shown.

• Each of the regions like the emitter, base, collector,
contact, metal and isolation need to be formed in the
specific volume of Si in a fabrication process.
• The depth dimension is normally achieved by using a well
designed fabrication sequence using many process steps
typically used.
• The surface areas of these regions are mainly dictated by
design requirements like how much area is needed for the
emitter, or length or width are needed for MOSFET to get
desired bias current, gain and frequency response.
 14
Structure of BJT
NPN Transistor Symbol:
 15
Lithography

• These areas for all the regions are drawn by designers by

following certain design rules in a layout where they color
code and label each area drawing called mask by its
function or material name e.g. emitter, metal, contact.
• These areas are then transferred to a physical mask in
which usually the region of interest is transparent and
outside region is blocked with appropriate layer.
• MOS or diode or BJT or any device structure is
implemented in silicon with help of layout masks. The
layout has mask names that usually indicate either a
function or a material layer.
 16
Lithography

• These geometrical patterns for each layer on the layout are

transferred to Silicon. This is achieved by the lithography
step in processing.
• The basic principle is to use a photosensitive material for
optical (X ray sensitive-X-ray lithography, e-beam sensitive-
e-beam lithography) for exposing the layout geometries.
• We will use simple cross-sectional drawings to learn about
each of the processing steps using masks and an
integrated sequence to fabricate Diode, BJT and MOSFET.
• What feature sizes you expect for visible, UV, Extreme UV,
electron beam, X-Ray?
 17
Lithography

• The photosensitive material called resist is deposited on

Silicon Wafer which possibly has one or more materials
grown or deposited on it as shown.

Resist
Mat 2
Mat 1

Si Wafer

Figure: Silicon Cross Section after resist deposition

 Lithography 18
• The resist is deposited on Silicon wafer by topping it with droplets of
dissolved resist by spinning the wafer at high speed. The solvent is
then evaporated by baking the wafer at about 50 - 60 C (Soft bake).
The resist is typically 0.1-1m thick. Then ultraviolet light is shone
through the mask plate as shown to expose the resist in open areas.
Post exposure bake is done after the exposure for better resist
UV Light
adhesion.

Mask

Resist

Mat 2
Mat 1

Si Wafer

Figure : The process of exposure

 19
Lithography

Negative Resists
• Prior to 1985 or so, negative resist was popular. (Do you
know negatives of photo films?)
• Consists of inert polyisoprene rubber and photoactive
agent.
• Exposed resist forms cross linkages between rubber
molecules to enlarge it, making it less soluble.
• Oxygen is to be avoided.
• Exposed resist swells and distorts. Thus, it is not good for
small features.
 Lithography 20

Positive Resist
• Consists of a resin and a photoactive compound (PAC) for
UV (i-line and g-line) ~400nm wavelength.
• Photoactive compound is dissolution inhibitor for
development step which does not dissolve unexposed resist.
• Exposure destroys inhibitor (makes inhibiter ineffective).
• Exposure makes exposed resist more soluble in developer.
• Very sensitive (energy-100mJcm-2, 300 to 400nm light).
• No swelling problem and hence better features (dimensions).
• The cross-sections above and most later use positive resist.
 21
Lithography
Deep or Extreme UV (EUV 13.5nm wavelength) resists
• Chemically Amplified (CA) Resists are used.
• Very sensitive
• Here photons interact with Photo Acid Generator (PAG) in
the resist creating an acid molecule.
• Acid molecules are catalysts for changing resist properties
as required depending on positive or negative resist. Occurs
during post exposure bake (PEB). Hence PEB is a very
critical step here.
• Acid molecules are regenerated after each chemical reaction
and may participate in further reaction. Hence sensitivity is
excellent.
 22
Lithography

Lithography Exposure Techniques

• Photomasks are used for exposure of resist.
• Most masks for projection/stepper lithography are 5X the
actual size so actual features on the mask are 5 times larger.
• This is a square glass plate with a patterned emulsion of
metal film on one side. The first mask is aligned with the
wafer, so that the pattern can be transferred onto the wafer
surface. Each mask after the first one must be aligned one of
the previous pattern. Why?
• When an image on the photomask is projected several times
side by side onto the wafer, this is known as stepping and
the photomask is called a reticle.
 23
Lithography

Contact Printing
• Mask plate pressed against and directly in contact with resist
as shown in the figure. Here mask features are 1X.
• A thin 0.2mm flexible mask for better contact.
• In practice, up to 0.3μm features are possible in contact
printing.
• The major problem is that mask gathers defects.
13 defects/cm2 after 5 exposures.
37 defects/cm2 after 15 exposures.
 24
Lithography

Proximity Printing
• Mask separated in 20 to 50μm range from resist. Mask life
increases. Here also mask features are 1X.
• Image is not very good.
• Minimum feature size achievable is about 2μm. Not so good.
 25
Lithography

Projection Printing
• Fancy optics used for focusing. Aberrations must be
controlled in part per million (PPM). Image is focused.
• In practice, up to 0.1μm features are possible in stepper
projection printing when enhancement methods are used.
• Step and repeat projection in the figure is commonly used
in technologies today.
 26
Lithography
 27
Lithography
 28
Lithography
 29
Lithography
The positive resist exposed to UV light softens and can be dissolved in a developer to expose mat 2.
30
Lithography
Development
• The positive resist exposed to UV light softens and can be
dissolved in a developer to expose mat 2. Now, mat 2 and
mat 1 in the exposed area can be selectively
etched(removed) to do processing in the masked Silicon.
Exposed resist developed away

Resist

Mat 2

Mat 1

Si Wafer

Figure 2: Cross Section after development

 Lithography/Etching 31

• However, due to diffraction of light around mask edges, non-

planar surfaces and slight over or under exposures, it is
difficult to get exact replica of open feature transferred to the
resist. Hence actual mask sizes on layout are not transferred
to silicon exactly and there is always variability. This
variability has become a serious concern below 90nm
technology where impact on circuit performance due to this
variability is significant.
• The normal step, which follows lithography, is etching.
Etching is a selective removal of a material from the wafer.
The basic principle is that the material to be etched will only
be removed from exposed areas and will not be removed
from the areas protected by unexposed resist.
 Etching 32
• Ideally, any material other than the material to be etched should not be
affected in this process (Selectivity). However, this is rare and there is a
finite selectivity. The silicon wafer is in the state shown after mat 2 has
been etched following the development previously shown. Note that
sometimes the edge of the etched material is not vertical and there is
significant undercut in mat 2 under resist.
Resist

Mat 2
Mat 1

Si Wafer

figure : The process of development

• This undercut in etching is a problem which increases some features and

decreases others and hence some adjustments to layout are needed as
a consequence.
 Etching 33

• The undercut is a very common problem in wet chemical

etching. Hence it is not used today in short channel
technologies. But it is still very useful for blanket removal of
materials everywhere or when features are large and not
critical.
• Wet etches:
- are in general isotropic
(not used to etch features less than ≈ 3 µm)
- achieves high selectivity for most film combinations
- capable of high throughputs due to batch process
- use comparably cheap equipment
- can have resist adhesion problems
- can etch just about anything
- Highly selective
 Etching 34

•Example Chemistries for wet etching

For SiO2 etching : - HF + NH4F+H20 (buffered oxide etch or BOE)
For Si3N4
- Hot phosphoric acid: H3PO4 at 180 °C
- need to use oxide hard mask as resists cannot sustain high
Temperature.
Silicon
- Nitric, HF, acetic acids
- HNO3 + HF + CH3COOH + H2O
Aluminum
- Acetic, nitric, phosphoric acids at 35-45 °C
- CH3COOH+HNO3+H3PO4
 35
Etching
Dry or Plasma Etching
• Uses Plasma.
• A plasma is a partially ionized gas made up of equal parts positively and
negatively charged particles.
• Plasmas are generated by flowing gases through an electric and/or
magnetic field.
• These fields remove electrons from some of the gas molecules. The
liberated electrons are accelerated, or energized, by the fields.
• The energetic electrons slam into other gas molecules, liberating more
electrons, which are accelerated and liberate more electrons from gas
molecules, thus sustaining the plasma.
 36
Etching
Dry or Plasma Etching

• Selectivity is ratio of the removal rate

of the material to be etched to the
removal rate of other materials.
Ideally, infinite or > 100.
 37
Etching
Dry or Plasma Etching
 38
Etching
Dry Etching
Combination of chemical and physical etching – Reactive Ion
Etching (RIE)
• Directional etching due to ion assistance.
• In RIE processes, the wafers sit on the powered electrode.
This placement sets up a negative bias on the wafer which
accelerates positively charge ions toward the surface. These
ions enhance the chemical etching mechanisms and allow
anisotropic etching.
• Wet etches are simpler, but dry etches provide better line width
control since it is anisotropic.
• Generally dry plasma etching or RIE are used in short channel
processes today.
 Metallization/Deposition 39
• There are many deposition methods available in processing. One
would like to have uniform cover of deposited material on the surface
of the wafer. It is quite easy to get uniformity if the surface on which
deposition is done is planar. However, a typical deposition pattern
with a Chemical Vapor Deposition (CVD) isotropic deposition system
on nonplanar surfaces will be as shown (Notice?).
Deposited material
layer

Initial Wafer surface

Figure : Profile after deposition on non-planar surface

• One can easily notice non-uniformity of the deposited layer. In fact,

the layer is very thin on the vertical walls of initial surface. This may
pose some problems for metal layer reliability due to higher current
density.
 Metallization/Deposition 40

• Metallization is the process to produce a thin metal film layer

to complete the interconnections.
• Aluminum was widely used.
• the Al deposition process takes place in the vacuum
pressure range-10-6 to 10-7 tor
• evaporating material is placed in resistance heated tungsten
crucible and a high power beam is focused at the material to
be heated.
• The material is vaporized and travels in straight line paths
and then condenses to form thin film coating
• New technologies use Cu with small percentage of Al. It
uses electroplating of Cu.
• 6 or more metal layers are available for very complex chips.
 Oxidation 41

• This is one of the most important steps in Silicon Processing as oxide

can be used as
– a block for impurity diffusion,
– as a dielectric for capacitance or interlayer insulation, or
– as a protective layer to guard Silicon against contamination.
• Oxide can also be selectively grown using nitride as a mask as nitride
oxidation is much slower than Silicon oxidation. Thus the areas of
Silicon covered by nitride will not oxidize.
• The oxide is normally grown in dry oxygen, steam, or high-pressure
oxygen in 750c to 1200c range. The main reactions are
Si + O 2 → SiO 2
Si + 2H 2O → SiO 2 + 2H 2

• The wet oxidation is much faster (about 10 times) than dry oxidation.
 Oxidation 42

• The stability and ease of formation of SiO2 was one of the reasons that
Si replaced Ge as the semiconductor of choice.
• Batch processing of wafers is another benefit which increases
throughput as shown below.
 Oxidation 43

There are certain general guidelines on which methods to use.

• When very high quality, thin oxide is needed such as gate
oxide in MOS processing, only dry oxidation is used.
Nowadays Nitrated oxides or High-k dielectrics are used.
• When good thick oxide is needed dry oxidation followed by
wet oxidation is used. This reduces the time for oxidation by
a factor of about 10. This is the only method for growth of
good quality thick oxides of thickness around 1m in practice.
The high-pressure oxidation can also be used to enhance the
growth rate.
• Deposited oxide layers are normally used for inter-metal
isolation, since metals such as Aluminum cannot sustain high
oxidation temperatures.
 Oxidation 44
• Deposited oxides can be produced by various reactions between
gaseous silicon compounds and gaseous oxidizers. Deposited oxides
tend to possess low densities and large numbers of defect sites. Not
suitable for use as gate dielectrics for MOS transistors but still
acceptable for use as insulating layers between multiple conductor
layers, or as protective overcoats.
• Key Oxidation Parameters
• Temperature
- reaction rate
- solid state diffusion
• Oxidizing species
- wet oxidation is much faster than dry oxidation (Why?)
• Surface cleanliness
- metallic contamination can catalyze reaction
- quality of oxide grown (interface states)
 Oxidation 45

• There are many consequences of oxidation which affect designers or

alter processing somewhat. These will now be discussed briefly.
Oxidation

(1) While oxidizing, about 50% of Si layer is consumed. Hence the oxide
Si
layer will have higher elevation than original Si and will eventually lead to
non-planar starting surfaces.

Added thickness
Oxide

Si
Si

Figure : Increased Elevation due to oxidation

 Oxidation 46
(2) Nitride is an effective mask for oxidation. If it were a perfect mask,
the oxidation after patterning nitride will look as shown.

Oxide Grown
Nitride Nitride

Oxide
Oxidation
Si
Si

Figure : Selective Oxidation with Perfect Nitride

 Oxidation 47
In reality, oxide encroaches under nitride and lifts it off to produce bird’s
beak structure. (Why?)
Oxidation

Oxide Grown
Nitride Nitride

Oxide
Oxidation
Si
Si

Figure: bird’s beak structure.

 Oxidation 48
This has very profound implications for width of MOS devices as
shown. W
Oxidation
Poly
Isolation
Thick
Oxide

Weff
Thin gate oxide

Figure : Width Reduction due to Bird’s Beak in LOCOS Isolation

• Normally cross section of MOSFET is drawn with source and drain

showing channel length. The cross section along the width direction has
oxide thickness transition from gate oxide to isolation oxide.
• The thickness of oxide away from Weff is larger than gate oxide
thickness. Since the threshold voltage increases with increasing oxide
thickness, there will be width reduction. For technology below 0.18m,
shallow trench isolation is used instead to avoid this problem.
 49
Realistic MOSFET Structure
Both P and N channel MOSFETs are fabricated together in IC Technology. The
length L of the MOSFET is as drawn with two-sided arrow.

1000nm PETEOS

50nm Nitride
350nm SABPSG

P+ P+ N+ N+

N-Well P-Well
 Oxidation 50
(3) Impurity Segregation: Due to high temperature during oxidation, the
impurities tend to diffuse deeper. The redistribution, however, is affected
by the presence of oxide – Si interface.
The concentration of Boron near the interface is reduced in Si compared to
normal concentration and affects the threshold voltage of MOSFET as it
depends on doping withing small depth below oxide.

Boron
Conc

Oxide

Si
Depth
Boron redistribution due to Segregation
 51
Oxidation
The concentration of P and As is increased as shown.

Oxide
P
Conc

Si
Depth

As and P redistribution due to Segregation

 52
Ion Implantation
• This is a process of introducing impurity (typically dopants) or
other ions into Si by giving them enough energy to penetrate
into Si.
• Higher energy ions will penetrate deeper into Silicon. Hence
the ion energy and number of ions to be introduced measured
by dose determine the dopant profile.
• Normally this step is used to selectively dope silicon after
lithography step where the parts of Si covered by resist will
not allow implant to pass through to Si. Only the exposed Si
will receive implant.
 53
Ion Implantation
Dopant Ions

Figure : Single Crystal Si

 54
Ion Implantation
• Implantation principle.
 55
Ion Implantation
• If the scattering of dopant ions by Si atoms is random, it is
easy to find the average depth of penetration (range Rp)
(This is also normally the location of the largest
concentration), standard deviation in the depth (RP) in the
direction of the ion beam, and standard deviation
perpendicular to the beam direction (RL).
• The typical values of range are in 0.01m - 2m interval.
• For P, As and Sb, the distribution of ions is a Gaussian. For
Boron, it is found that the distribution has a long tail and
deviation near surface from Gaussian which is modeled by a
Pearson IV or V distribution function.
 56
Ion Implantation

• Relatively precise control of doping profile and integrated

doping concentration (this is actually the implant dose
typically specified in cm-2) is possible by ion implants.
• However, it is not totally free of problems, which will be
discussed in brief.

Ion Implantation
(1)Channeling: Black dots
Impurity ion here
will not scatter often
One Crystal plane
Another set of
Planes
Figure : Channeling in Single Crystal Si
57
here show regularly
arranged Si atom nuclei
in a single crystal. The
incident ion beam could
sometimes be
perpendicular to one of
the crystallographic
planes in Si. In this case,
due to less scattering
along the path, the ion
may penetrate 2 times
deeper than the normal
depth predicted by
random scattering.
To avoid this, the beam
may be sent at 3 - 7 to
the normal.
 58
Ion Implantation
• (2) Damage – Crystalline structure of Si is damaged by
implants as Silicon atoms are scattered randomly and
displaced from their normal positions in the periodic crystal
lattice. Also, impurity (dopant) atoms will automatically be in
random positions in Si.
• This damage is to the extent that Silicon becomes
amorphous after a part of the dose has been implanted.
• Hence a post implant anneal, which gives thermal energy
for Si to restore to the lowest energy single crystal state
starting from single crystal wafer seed, becomes essential.
 59
Ion Implantation
• Normally, an anneal of about 30 minutes at 850c is
adequate to remove the crystalline damage and activate
impurities by moving them into substitutional sites.
• Nowadays, Rapid Thermal Annealing (RTA) is often used as
thermal budget is quite limited for short channel MOSFETs.
RTA for 30 seconds at around 1020c is typically sufficient.
SPIKE or FLASH or LASER anneal is also used in case of
even tighter thermal budget.
• This, however, will redistribute the impurities by diffusion and
some of the implant advantages are adversely affected.
 Diffusion 60
• This is a natural phenomenon due to the tendency for impurities to
move from a region of high concentration to a region of low
concentration. Hence if some impurities are introduced near Silicon
surface, at higher temperature they will diffuse deeper into Silicon.
• Diffusion was a very popular way of selectively introducing impurities
in Silicon before implants came along. Diffusion is a batch process
like oxidation and uses the furnace and hence very efficient.
• Due to slow impurity diffusion in SiO2, oxide was used as a mask for
selected introduction of impurities.
Impurity ambient

Oxide
Slight lateral
Impurities enter diffusion
here
No impurities
Si Under oxide
 61
Diffusion
• Even if this technique is not so much used in the present
implant age, the diffusion is still a part of processing life.
• The post implant anneal makes the implanted impurities
redistribute by diffusion and lateral (sideways) penetration of
dopants becomes worse compared to implant.

Impurity Oxide
profile after Redistribution

implant with after diffusion

30% lateral with 70% lateral

penetration. penetration.
Si

Figure : Redistribution of Implanted Impurities after anneal

 62
Diffusion
• The diffusion takes place any time Silicon is heated. The presence
of lateral diffusion at about 70% of depth decides some of the
critical device features and inherently limits some of the device
features and properties.
• For very deep diffusions, the profile is a near Gaussian. For very
shallow ones, it is a near error function.
• The characteristic depths for the functions are determined by the
diffusion coefficient D which is a primary exponential function of the
temperature and the time t of diffusion. Dt is typically the standard
deviation in the depth for the distribution. The diffusion coefficient D
is a very strong function of concentration of vacancies (occasional
missing Si atom) and interstitial (Si atom squeezed with Si
neighbors) within the crystal. It also depends on the presence of
other impurities and materials.
 63
Diffusion
• One such effect we saw in segregation before due to presence of oxide.
The other one is shown in the figure below and has strong implications
on Bipolar Junction Transistors (BJTs) .

P-diffusion pushed deeper

under N+

P N+ P

n Si n Si

Figure : Effect of Impurity on Diffusion

 64
Diffusion/Implant comparison
• Diffusion is a cheaper and more simplistic method, but can
only be performed from the surface of the wafers. Dopants
also diffuse unevenly, and interact with each other altering
the diffusion rate.
• Ion implantation is more expensive and complex. It does not
require high temperatures and also allows for greater control
of dopant concentration and profile. It is an anisotropic
process and therefore does not spread the dopant implant
as much as diffusion. This aids in the manufacture of self-
aligned structures (covered later in MOSFET fabrication)
which greatly improves the performance of MOS and Bipolar
transistors.
 Device Isolation 65

• P-N JUNCTION ISOLATION

Used mainly in Bipolar Junction Transistors (BJTs) and diodes

which we will study later.

• DIELECTRIC ISOLATION

Used mainly in MOSFETs as Local Oxidation of

Silicon(LOCOS) in the past and Shallow Trench Isolation
presently which we will study later.
 Device Isolation 66
Device isolation is needed to ensure that there is no leakage between
neighboring unrelated MOSFETs like the one shown below. The normal
MOSFETs are on the left and right.

Parasitic FOX device

n+ n+ n+ n+

p-substrate (bulk)
 Device Isolation 67

• The unwanted MOS Source and drains are from existing

source and drains of two unrelated but wanted devices.
The following details are for the unwanted parasitic device.
• The gate oxide layer is Field or isolation oxide (FOX) for the
unwanted parasitic device.
• Gates are metal and polysilicon interconnects on top of
Fox as all the region outside MOSFET gate-source-drain
can have interconnects.
• Parasitic MOS should not conduct under normal operation.
• So, the threshold voltage of FOX FET’s should be higher
(e.g. 8V if power supply voltage is 5V). This requires higher
doped substrate under interconnect through a field implant.
 68
Assembly processing and packaging:

1. Metal can package

2. Ceramic flat package
3. Dual in line package.
We will discuss these more later.
 69
Process Sequence with Mask
• The process sequence is best understood with inverter cross
sections for CMOS and a single device diode or bipolar
transistors. Normally, inverter layout with different mask
layers to be transferred to Si is done to implement desired
circuit. The mask names typically reflect materials or process
steps involved.
• Here the masks will be just shown as mask layout is not in
the scope of this course.
• A common process sequence is normally done for each
mask transfer to Si. This sequence is given here and will not
be repeated when the cross-sections are progressively
developed with a mask set. Only masks will be shown.
 70
Process Sequence with Mask
• Process Step: Selective Removal of material – 1 (Mat-1) to
dope Si with Boron (p type). Inside of the rectangle is
transparent area.
• Process Sequence:
Starting Material Mask

Line of cross-section

Mat-1

Si
 71
Process Sequence with Mask
i) Deposit Resist

Starting Material Mask

Line of cross-section

Resist
Mat-1

Si
 72
Process Sequence with Mask
ii) Softbake Resist ~ 600c, 1-3 minutes
iii) Exposure – Expose Resist through the mask. Either
the mask or its complement used depending on the effect
desired.

Mask
Resist

Mat-1

Si
 73
Process Sequence with Mask
• iv) Hard Bake Resist ~ 800c, 1 - 6 minutes

• v) Develop Resist: Dissolves the exposed resist

Resist
Remaining Resist

Mat-1

Si
 74
Process Sequence with Mask

• vi) Etch Material-1 selecting a chemical which does not

attack resist and silicon or do a plasma etch.

Remaining Resist

Mat-1

Si
 75
Process Sequence with Mask
• vii) If Boron is implanted, it can be done now with resist
present. If diffusion or oxidation is involved, the resist must
be removed at this stage. Implant Boron.

Boron

Remaining Resist

Mat- 1
P+
Si
 76
Process Sequence with Mask
• If selective diffusion or oxidation is involved, the resist must
be removed at this stage.
• In selective oxidation case, material-1 must block oxidation
(material-1 -> Nitride).
• For selective diffusion (material-1-> Oxide).

Remaining Resist

-
Mat 1
P+
Si
 77
Process Sequence with Mask
• viii) Remove the resist as selective job is finished
• ix) Wafer ready for the next step. The cross-section after
(viii) will be normally shown.

Mat-1
P+
Si

• The lines of mask in each step in the exposure step shows

the regions of chrome which blocks light. Positive resist,
which is developed away after exposure, is used.
 78
Self study

• Search on the web or in books for details on principles

and important characteristics/specifications of
lithography stepper equipment and submit a report less
than 4 pages on it.
 79
Sample questions

• Why ion implantation is preferred over diffusion?

• Explain damage in ion implantation process and how it

is cured.

• What is benefit of oxidation?

• Explain importance of SiO2 in Silicon technology.

• Text book questions 1.10, 1.12, 1.13.

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Summary

• The basic processes involved in the IC fabrication have

been discussed.
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References

1. D. Roy Choudhury, Shail B. Jain, ‘Linear Integrated

Circuits’, II edition, New Age, 2003.
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Outcome of the module
✓ The students are able to understand the
steps/processes involved in the IC fabrication.
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Thank You