UVM

(Neccessary use the code snippets as example)

1) What is the purpose of UVM and explain the UVM testbench with block diagram?
2) Explain the UVM hierarchy with flow diagram
3) Explain the Phases in UVM
4) What is virtual sequence and difference b/w p_sequencer & m_sequencer?
5) What is the 'uvm_do and explain the use of macro
6) How to print testbench topology
7) Explain driver-sequence handshake mechanism
8) Explain about UVM factory and override methods
9) Difference b/w uvm_config_db and uvm_resource_db
10) What are TLM ports and requirements in Testbench
11) Explain RAL Model
12) Write a Testbench code for SPI Protocol should include Top, Environment,
Interface, Agent, Driver, Sequence, Sequencer, Monitor, Scoreboard(if neccessary
required)

SPI Protocol contains 4 slaves (CS0, CS1, CS2, CS3)

Interface Pins - MISO, MOSI, CLK (100MHz), CS0, CS1, CS2, CS3.

System Verilog
(Neccessary use the code snippets as example)

1) What is shallow and deep copy with example?

2) What is the difference of virtual and pure virtual function
3) Explain the SV thread process methods?
4) Explain the Polymorphism and virtual methods?
5) Explain the weighted distrbution constraints?
6) What are immediate and concurrent assertion and three methods?
7) Explain the useage of scope resolution operator?
8) What is functional coverage and coverpoint, covergroups?
9) Explain the associative, dynamic and queues?
10) Write a Testbench code for I2C protocol? - Only in System Verilog Concepts